xref: /gem5/src/arch/arm/isa/templates/mem.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines


def template LoadExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                  Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
                %(memacc_code)s;
            }

            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template StoreExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                  Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(memacc_code)s;
            }

            if (fault == NoFault) {
                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                  memAccessFlags, NULL);
                if (traceData) { traceData->setData(Mem); }
            }

            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template StoreInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(memacc_code)s;
            }

            if (fault == NoFault) {
                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                                  memAccessFlags, NULL);
                if (traceData) { traceData->setData(Mem); }
            }

            // Need to write back any potential address register update
            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template LoadInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Addr EA;
        Fault fault = NoFault;

        %(op_src_decl)s;
        %(op_rd)s;
        %(ea_code)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
            }
        }

        return fault;
    }
}};

def template LoadCompleteAcc {{
    Fault %(class_name)s::completeAcc(PacketPtr pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            // ARM instructions will not have a pkt if the predicate is false
            Mem = pkt->get<typeof(Mem)>();

            if (fault == NoFault) {
                %(memacc_code)s;
            }

            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template StoreCompleteAcc {{
    Fault %(class_name)s::completeAcc(PacketPtr pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                %(op_wb)s;
            }
        }

        return fault;
    }
}};

def template LoadStoreImmDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      public:

        /// Constructor.
        %(class_name)s(ExtMachInst machInst,
                uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);

        %(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s
    };
}};

def template LoadStoreRegDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      public:

        /// Constructor.
        %(class_name)s(ExtMachInst machInst,
                uint32_t _dest, uint32_t _base, bool _add,
                int32_t _shiftAmt, uint32_t _shiftType,
                uint32_t _index);

        %(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s
    };
}};

def template InitiateAccDeclare {{
    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};

def template CompleteAccDeclare {{
    Fault completeAcc(PacketPtr,  %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};

def template LoadStoreImmConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
            uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
    {
        %(constructor)s;
    }
}};

def template LoadStoreRegConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
            uint32_t _dest, uint32_t _base, bool _add,
            int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
                 _shiftAmt, (ArmShiftType)_shiftType,
                 (IntRegIndex)_index)
    {
        %(constructor)s;
    }
}};