mem.isa revision 10666
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 310666SAli.Saidi@ARM.com// Copyright (c) 2010, 2012, 2014 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 4510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 5410196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 637646Sgene.wu@arm.com Fault %(class_name)s::completeAcc(PacketPtr pkt, 6410196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 657646Sgene.wu@arm.com Trace::InstRecord *traceData) const 667646Sgene.wu@arm.com { 677646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 687646Sgene.wu@arm.com return NoFault; 697646Sgene.wu@arm.com } 707646Sgene.wu@arm.com}}; 717646Sgene.wu@arm.com 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edudef template SwapExecute {{ 7410196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 757205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 767205Sgblack@eecs.umich.edu { 777205Sgblack@eecs.umich.edu Addr EA; 787205Sgblack@eecs.umich.edu Fault fault = NoFault; 797205Sgblack@eecs.umich.edu 807205Sgblack@eecs.umich.edu %(op_decl)s; 817205Sgblack@eecs.umich.edu uint64_t memData = 0; 827205Sgblack@eecs.umich.edu %(op_rd)s; 837205Sgblack@eecs.umich.edu %(ea_code)s; 847205Sgblack@eecs.umich.edu 857205Sgblack@eecs.umich.edu if (%(predicate_test)s) 867205Sgblack@eecs.umich.edu { 877205Sgblack@eecs.umich.edu %(preacc_code)s; 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu if (fault == NoFault) { 908442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 918442Sgblack@eecs.umich.edu &memData); 927205Sgblack@eecs.umich.edu } 937205Sgblack@eecs.umich.edu 947205Sgblack@eecs.umich.edu if (fault == NoFault) { 957205Sgblack@eecs.umich.edu %(postacc_code)s; 967205Sgblack@eecs.umich.edu } 977205Sgblack@eecs.umich.edu 987205Sgblack@eecs.umich.edu if (fault == NoFault) { 997205Sgblack@eecs.umich.edu %(op_wb)s; 1007205Sgblack@eecs.umich.edu } 1017597Sminkyu.jeong@arm.com } else { 1027597Sminkyu.jeong@arm.com xc->setPredicate(false); 1037205Sgblack@eecs.umich.edu } 1047205Sgblack@eecs.umich.edu 1057205Sgblack@eecs.umich.edu return fault; 1067205Sgblack@eecs.umich.edu } 1077205Sgblack@eecs.umich.edu}}; 1087205Sgblack@eecs.umich.edu 1097205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 11010196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 1117205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1127205Sgblack@eecs.umich.edu { 1137205Sgblack@eecs.umich.edu Addr EA; 1147205Sgblack@eecs.umich.edu Fault fault = NoFault; 1157205Sgblack@eecs.umich.edu 1167205Sgblack@eecs.umich.edu %(op_decl)s; 1177205Sgblack@eecs.umich.edu uint64_t memData = 0; 1187205Sgblack@eecs.umich.edu %(op_rd)s; 1197205Sgblack@eecs.umich.edu %(ea_code)s; 1207205Sgblack@eecs.umich.edu 1217205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1227205Sgblack@eecs.umich.edu { 1237205Sgblack@eecs.umich.edu %(preacc_code)s; 1247205Sgblack@eecs.umich.edu 1257205Sgblack@eecs.umich.edu if (fault == NoFault) { 1268442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1278442Sgblack@eecs.umich.edu &memData); 1287205Sgblack@eecs.umich.edu } 1297597Sminkyu.jeong@arm.com } else { 1307597Sminkyu.jeong@arm.com xc->setPredicate(false); 1317205Sgblack@eecs.umich.edu } 1327205Sgblack@eecs.umich.edu 1337205Sgblack@eecs.umich.edu return fault; 1347205Sgblack@eecs.umich.edu } 1357205Sgblack@eecs.umich.edu}}; 1367205Sgblack@eecs.umich.edu 1377205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 1387205Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 13910196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 1407205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1417205Sgblack@eecs.umich.edu { 1427205Sgblack@eecs.umich.edu Fault fault = NoFault; 1437205Sgblack@eecs.umich.edu 1447205Sgblack@eecs.umich.edu %(op_decl)s; 1457205Sgblack@eecs.umich.edu %(op_rd)s; 1467205Sgblack@eecs.umich.edu 1477205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1487205Sgblack@eecs.umich.edu { 1497205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1508442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1518442Sgblack@eecs.umich.edu uint64_t memData = Mem; 1527205Sgblack@eecs.umich.edu 1537205Sgblack@eecs.umich.edu %(postacc_code)s; 1547205Sgblack@eecs.umich.edu 1557205Sgblack@eecs.umich.edu if (fault == NoFault) { 1567205Sgblack@eecs.umich.edu %(op_wb)s; 1577205Sgblack@eecs.umich.edu } 1587205Sgblack@eecs.umich.edu } 1597205Sgblack@eecs.umich.edu 1607205Sgblack@eecs.umich.edu return fault; 1617205Sgblack@eecs.umich.edu } 1627205Sgblack@eecs.umich.edu}}; 1637205Sgblack@eecs.umich.edu 1647119Sgblack@eecs.umich.edudef template LoadExecute {{ 16510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 1667119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1677119Sgblack@eecs.umich.edu { 1687119Sgblack@eecs.umich.edu Addr EA; 1697119Sgblack@eecs.umich.edu Fault fault = NoFault; 1707119Sgblack@eecs.umich.edu 1717119Sgblack@eecs.umich.edu %(op_decl)s; 1727119Sgblack@eecs.umich.edu %(op_rd)s; 1737119Sgblack@eecs.umich.edu %(ea_code)s; 1747119Sgblack@eecs.umich.edu 1757119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1767119Sgblack@eecs.umich.edu { 1777119Sgblack@eecs.umich.edu if (fault == NoFault) { 1788442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1797119Sgblack@eecs.umich.edu %(memacc_code)s; 1807119Sgblack@eecs.umich.edu } 1817119Sgblack@eecs.umich.edu 1827119Sgblack@eecs.umich.edu if (fault == NoFault) { 1837119Sgblack@eecs.umich.edu %(op_wb)s; 1847119Sgblack@eecs.umich.edu } 1857597Sminkyu.jeong@arm.com } else { 1867597Sminkyu.jeong@arm.com xc->setPredicate(false); 1877119Sgblack@eecs.umich.edu } 1887119Sgblack@eecs.umich.edu 1897119Sgblack@eecs.umich.edu return fault; 1907119Sgblack@eecs.umich.edu } 1917119Sgblack@eecs.umich.edu}}; 1927119Sgblack@eecs.umich.edu 1937639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1947639Sgblack@eecs.umich.edu template <class Element> 1957639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 19610196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1977639Sgblack@eecs.umich.edu { 1987639Sgblack@eecs.umich.edu Addr EA; 1997639Sgblack@eecs.umich.edu Fault fault = NoFault; 2007639Sgblack@eecs.umich.edu 2017639Sgblack@eecs.umich.edu %(op_decl)s; 2027639Sgblack@eecs.umich.edu %(mem_decl)s; 2037639Sgblack@eecs.umich.edu %(op_rd)s; 2047639Sgblack@eecs.umich.edu %(ea_code)s; 2057639Sgblack@eecs.umich.edu 2067639Sgblack@eecs.umich.edu MemUnion memUnion; 2077639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2087639Sgblack@eecs.umich.edu 2097639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2107639Sgblack@eecs.umich.edu { 2117639Sgblack@eecs.umich.edu if (fault == NoFault) { 2128444Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 2137639Sgblack@eecs.umich.edu %(memacc_code)s; 2147639Sgblack@eecs.umich.edu } 2157639Sgblack@eecs.umich.edu 2167639Sgblack@eecs.umich.edu if (fault == NoFault) { 2177639Sgblack@eecs.umich.edu %(op_wb)s; 2187639Sgblack@eecs.umich.edu } 2198072SGiacomo.Gabrielli@arm.com } else { 2208072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2217639Sgblack@eecs.umich.edu } 2227639Sgblack@eecs.umich.edu 2237639Sgblack@eecs.umich.edu return fault; 2247639Sgblack@eecs.umich.edu } 2257639Sgblack@eecs.umich.edu}}; 2267639Sgblack@eecs.umich.edu 2277120Sgblack@eecs.umich.edudef template StoreExecute {{ 22810196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 2297120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2307120Sgblack@eecs.umich.edu { 2317120Sgblack@eecs.umich.edu Addr EA; 2327120Sgblack@eecs.umich.edu Fault fault = NoFault; 2337120Sgblack@eecs.umich.edu 2347120Sgblack@eecs.umich.edu %(op_decl)s; 2357120Sgblack@eecs.umich.edu %(op_rd)s; 2367120Sgblack@eecs.umich.edu %(ea_code)s; 2377120Sgblack@eecs.umich.edu 2387120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2397120Sgblack@eecs.umich.edu { 2407120Sgblack@eecs.umich.edu if (fault == NoFault) { 2417120Sgblack@eecs.umich.edu %(memacc_code)s; 2427120Sgblack@eecs.umich.edu } 2437120Sgblack@eecs.umich.edu 2447120Sgblack@eecs.umich.edu if (fault == NoFault) { 2458442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2468442Sgblack@eecs.umich.edu memAccessFlags, NULL); 2477120Sgblack@eecs.umich.edu } 2487120Sgblack@eecs.umich.edu 2497120Sgblack@eecs.umich.edu if (fault == NoFault) { 2507120Sgblack@eecs.umich.edu %(op_wb)s; 2517120Sgblack@eecs.umich.edu } 2527597Sminkyu.jeong@arm.com } else { 2537597Sminkyu.jeong@arm.com xc->setPredicate(false); 2547120Sgblack@eecs.umich.edu } 2557120Sgblack@eecs.umich.edu 2567120Sgblack@eecs.umich.edu return fault; 2577120Sgblack@eecs.umich.edu } 2587120Sgblack@eecs.umich.edu}}; 2597120Sgblack@eecs.umich.edu 2607639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2617639Sgblack@eecs.umich.edu template <class Element> 2627639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 26310196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 2647639Sgblack@eecs.umich.edu { 2657639Sgblack@eecs.umich.edu Addr EA; 2667639Sgblack@eecs.umich.edu Fault fault = NoFault; 2677639Sgblack@eecs.umich.edu 2687639Sgblack@eecs.umich.edu %(op_decl)s; 2697639Sgblack@eecs.umich.edu %(mem_decl)s; 2707639Sgblack@eecs.umich.edu %(op_rd)s; 2717639Sgblack@eecs.umich.edu %(ea_code)s; 2727639Sgblack@eecs.umich.edu 2737639Sgblack@eecs.umich.edu MemUnion memUnion; 2747639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2757639Sgblack@eecs.umich.edu 2767639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2777639Sgblack@eecs.umich.edu { 2787639Sgblack@eecs.umich.edu if (fault == NoFault) { 2797639Sgblack@eecs.umich.edu %(memacc_code)s; 2807639Sgblack@eecs.umich.edu } 2817639Sgblack@eecs.umich.edu 2827639Sgblack@eecs.umich.edu if (fault == NoFault) { 2838444Sgblack@eecs.umich.edu fault = xc->writeMem(dataPtr, %(size)d, EA, 2848444Sgblack@eecs.umich.edu memAccessFlags, NULL); 2857639Sgblack@eecs.umich.edu } 2867639Sgblack@eecs.umich.edu 2877639Sgblack@eecs.umich.edu if (fault == NoFault) { 2887639Sgblack@eecs.umich.edu %(op_wb)s; 2897639Sgblack@eecs.umich.edu } 2908072SGiacomo.Gabrielli@arm.com } else { 2918072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2927639Sgblack@eecs.umich.edu } 2937639Sgblack@eecs.umich.edu 2947639Sgblack@eecs.umich.edu return fault; 2957639Sgblack@eecs.umich.edu } 2967639Sgblack@eecs.umich.edu}}; 2977639Sgblack@eecs.umich.edu 2987303Sgblack@eecs.umich.edudef template StoreExExecute {{ 29910196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 3007303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3017303Sgblack@eecs.umich.edu { 3027303Sgblack@eecs.umich.edu Addr EA; 3037303Sgblack@eecs.umich.edu Fault fault = NoFault; 3047303Sgblack@eecs.umich.edu 3057303Sgblack@eecs.umich.edu %(op_decl)s; 3067303Sgblack@eecs.umich.edu %(op_rd)s; 3077303Sgblack@eecs.umich.edu %(ea_code)s; 3087303Sgblack@eecs.umich.edu 3097303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3107303Sgblack@eecs.umich.edu { 3117303Sgblack@eecs.umich.edu if (fault == NoFault) { 3127303Sgblack@eecs.umich.edu %(memacc_code)s; 3137303Sgblack@eecs.umich.edu } 3147303Sgblack@eecs.umich.edu 3157303Sgblack@eecs.umich.edu uint64_t writeResult; 3167303Sgblack@eecs.umich.edu 3177303Sgblack@eecs.umich.edu if (fault == NoFault) { 3188442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3198442Sgblack@eecs.umich.edu &writeResult); 3207303Sgblack@eecs.umich.edu } 3217303Sgblack@eecs.umich.edu 3227303Sgblack@eecs.umich.edu if (fault == NoFault) { 3237303Sgblack@eecs.umich.edu %(postacc_code)s; 3247303Sgblack@eecs.umich.edu } 3257303Sgblack@eecs.umich.edu 3267303Sgblack@eecs.umich.edu if (fault == NoFault) { 3277303Sgblack@eecs.umich.edu %(op_wb)s; 3287303Sgblack@eecs.umich.edu } 3297597Sminkyu.jeong@arm.com } else { 3307597Sminkyu.jeong@arm.com xc->setPredicate(false); 3317303Sgblack@eecs.umich.edu } 3327303Sgblack@eecs.umich.edu 3337303Sgblack@eecs.umich.edu return fault; 3347303Sgblack@eecs.umich.edu } 3357303Sgblack@eecs.umich.edu}}; 3367303Sgblack@eecs.umich.edu 3377303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 33810196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 3397303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3407303Sgblack@eecs.umich.edu { 3417303Sgblack@eecs.umich.edu Addr EA; 3427303Sgblack@eecs.umich.edu Fault fault = NoFault; 3437303Sgblack@eecs.umich.edu 3447303Sgblack@eecs.umich.edu %(op_decl)s; 3457303Sgblack@eecs.umich.edu %(op_rd)s; 3467303Sgblack@eecs.umich.edu %(ea_code)s; 3477303Sgblack@eecs.umich.edu 3487303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3497303Sgblack@eecs.umich.edu { 3507303Sgblack@eecs.umich.edu if (fault == NoFault) { 3517303Sgblack@eecs.umich.edu %(memacc_code)s; 3527303Sgblack@eecs.umich.edu } 3537303Sgblack@eecs.umich.edu 3547303Sgblack@eecs.umich.edu if (fault == NoFault) { 3558442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3568442Sgblack@eecs.umich.edu NULL); 3577303Sgblack@eecs.umich.edu } 3587597Sminkyu.jeong@arm.com } else { 3597597Sminkyu.jeong@arm.com xc->setPredicate(false); 3607303Sgblack@eecs.umich.edu } 3617408Sgblack@eecs.umich.edu 3627303Sgblack@eecs.umich.edu return fault; 3637303Sgblack@eecs.umich.edu } 3647303Sgblack@eecs.umich.edu}}; 3657303Sgblack@eecs.umich.edu 3667120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 36710196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 3687120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3697120Sgblack@eecs.umich.edu { 3707120Sgblack@eecs.umich.edu Addr EA; 3717120Sgblack@eecs.umich.edu Fault fault = NoFault; 3727120Sgblack@eecs.umich.edu 3737120Sgblack@eecs.umich.edu %(op_decl)s; 3747120Sgblack@eecs.umich.edu %(op_rd)s; 3757120Sgblack@eecs.umich.edu %(ea_code)s; 3767120Sgblack@eecs.umich.edu 3777120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3787120Sgblack@eecs.umich.edu { 3797120Sgblack@eecs.umich.edu if (fault == NoFault) { 3807120Sgblack@eecs.umich.edu %(memacc_code)s; 3817120Sgblack@eecs.umich.edu } 3827120Sgblack@eecs.umich.edu 3837120Sgblack@eecs.umich.edu if (fault == NoFault) { 3848442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3858442Sgblack@eecs.umich.edu NULL); 3867120Sgblack@eecs.umich.edu } 3877597Sminkyu.jeong@arm.com } else { 3887597Sminkyu.jeong@arm.com xc->setPredicate(false); 3897120Sgblack@eecs.umich.edu } 3907120Sgblack@eecs.umich.edu 3917120Sgblack@eecs.umich.edu return fault; 3927120Sgblack@eecs.umich.edu } 3937120Sgblack@eecs.umich.edu}}; 3947120Sgblack@eecs.umich.edu 3957639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3967639Sgblack@eecs.umich.edu template <class Element> 3977639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 39810196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 3997639Sgblack@eecs.umich.edu { 4007639Sgblack@eecs.umich.edu Addr EA; 4017639Sgblack@eecs.umich.edu Fault fault = NoFault; 4027639Sgblack@eecs.umich.edu 4037639Sgblack@eecs.umich.edu %(op_decl)s; 4047639Sgblack@eecs.umich.edu %(mem_decl)s; 4057639Sgblack@eecs.umich.edu %(op_rd)s; 4067639Sgblack@eecs.umich.edu %(ea_code)s; 4077639Sgblack@eecs.umich.edu 4087639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4097639Sgblack@eecs.umich.edu { 4107639Sgblack@eecs.umich.edu MemUnion memUnion; 4117639Sgblack@eecs.umich.edu if (fault == NoFault) { 4127639Sgblack@eecs.umich.edu %(memacc_code)s; 4137639Sgblack@eecs.umich.edu } 4147639Sgblack@eecs.umich.edu 4157639Sgblack@eecs.umich.edu if (fault == NoFault) { 4168444Sgblack@eecs.umich.edu fault = xc->writeMem(memUnion.bytes, %(size)d, EA, 4178444Sgblack@eecs.umich.edu memAccessFlags, NULL); 4187639Sgblack@eecs.umich.edu } 4198072SGiacomo.Gabrielli@arm.com } else { 4208072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4217639Sgblack@eecs.umich.edu } 4227639Sgblack@eecs.umich.edu 4237639Sgblack@eecs.umich.edu return fault; 4247639Sgblack@eecs.umich.edu } 4257639Sgblack@eecs.umich.edu}}; 4267639Sgblack@eecs.umich.edu 4277119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 42810196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, 4297119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4307119Sgblack@eecs.umich.edu { 4317119Sgblack@eecs.umich.edu Addr EA; 4327119Sgblack@eecs.umich.edu Fault fault = NoFault; 4337119Sgblack@eecs.umich.edu 4347119Sgblack@eecs.umich.edu %(op_src_decl)s; 4357119Sgblack@eecs.umich.edu %(op_rd)s; 4367119Sgblack@eecs.umich.edu %(ea_code)s; 4377119Sgblack@eecs.umich.edu 4387119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4397119Sgblack@eecs.umich.edu { 4407119Sgblack@eecs.umich.edu if (fault == NoFault) { 4418442Sgblack@eecs.umich.edu fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 4427119Sgblack@eecs.umich.edu } 4437597Sminkyu.jeong@arm.com } else { 4447597Sminkyu.jeong@arm.com xc->setPredicate(false); 4457119Sgblack@eecs.umich.edu } 4467119Sgblack@eecs.umich.edu 4477119Sgblack@eecs.umich.edu return fault; 4487119Sgblack@eecs.umich.edu } 4497119Sgblack@eecs.umich.edu}}; 4507119Sgblack@eecs.umich.edu 4517639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4527639Sgblack@eecs.umich.edu template <class Element> 4537639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 45410196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 4557639Sgblack@eecs.umich.edu { 4567639Sgblack@eecs.umich.edu Addr EA; 4577639Sgblack@eecs.umich.edu Fault fault = NoFault; 4587639Sgblack@eecs.umich.edu 4598207SAli.Saidi@ARM.com %(op_decl)s; 4608207SAli.Saidi@ARM.com %(mem_decl)s; 4617639Sgblack@eecs.umich.edu %(op_rd)s; 4627639Sgblack@eecs.umich.edu %(ea_code)s; 4637639Sgblack@eecs.umich.edu 4648207SAli.Saidi@ARM.com MemUnion memUnion; 4658207SAli.Saidi@ARM.com uint8_t *dataPtr = memUnion.bytes; 4668207SAli.Saidi@ARM.com 4677639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4687639Sgblack@eecs.umich.edu { 4697639Sgblack@eecs.umich.edu if (fault == NoFault) { 4708444Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 4717639Sgblack@eecs.umich.edu } 4728072SGiacomo.Gabrielli@arm.com } else { 4738072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4747639Sgblack@eecs.umich.edu } 4757639Sgblack@eecs.umich.edu 4767639Sgblack@eecs.umich.edu return fault; 4777639Sgblack@eecs.umich.edu } 4787639Sgblack@eecs.umich.edu}}; 4797639Sgblack@eecs.umich.edu 4807119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 4817119Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 48210196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 4837119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4847119Sgblack@eecs.umich.edu { 4857119Sgblack@eecs.umich.edu Fault fault = NoFault; 4867119Sgblack@eecs.umich.edu 4877119Sgblack@eecs.umich.edu %(op_decl)s; 4887119Sgblack@eecs.umich.edu %(op_rd)s; 4897119Sgblack@eecs.umich.edu 4907119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4917119Sgblack@eecs.umich.edu { 4927119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4938442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 4947119Sgblack@eecs.umich.edu 4957119Sgblack@eecs.umich.edu if (fault == NoFault) { 4967119Sgblack@eecs.umich.edu %(memacc_code)s; 4977119Sgblack@eecs.umich.edu } 4987119Sgblack@eecs.umich.edu 4997119Sgblack@eecs.umich.edu if (fault == NoFault) { 5007119Sgblack@eecs.umich.edu %(op_wb)s; 5017119Sgblack@eecs.umich.edu } 5027119Sgblack@eecs.umich.edu } 5037119Sgblack@eecs.umich.edu 5047119Sgblack@eecs.umich.edu return fault; 5057119Sgblack@eecs.umich.edu } 5067119Sgblack@eecs.umich.edu}}; 5077119Sgblack@eecs.umich.edu 5087639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5097639Sgblack@eecs.umich.edu template <class Element> 5107639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 51110196SCurtis.Dunham@arm.com PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 5127639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5137639Sgblack@eecs.umich.edu { 5147639Sgblack@eecs.umich.edu Fault fault = NoFault; 5157639Sgblack@eecs.umich.edu 5167639Sgblack@eecs.umich.edu %(mem_decl)s; 5177639Sgblack@eecs.umich.edu %(op_decl)s; 5187639Sgblack@eecs.umich.edu %(op_rd)s; 5197639Sgblack@eecs.umich.edu 5207639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5217639Sgblack@eecs.umich.edu { 5227639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5237639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5247639Sgblack@eecs.umich.edu 5257639Sgblack@eecs.umich.edu if (fault == NoFault) { 5267639Sgblack@eecs.umich.edu %(memacc_code)s; 5277639Sgblack@eecs.umich.edu } 5287639Sgblack@eecs.umich.edu 5297639Sgblack@eecs.umich.edu if (fault == NoFault) { 5307639Sgblack@eecs.umich.edu %(op_wb)s; 5317639Sgblack@eecs.umich.edu } 5327639Sgblack@eecs.umich.edu } 5337639Sgblack@eecs.umich.edu 5347639Sgblack@eecs.umich.edu return fault; 5357639Sgblack@eecs.umich.edu } 5367639Sgblack@eecs.umich.edu}}; 5377639Sgblack@eecs.umich.edu 5387120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 5397120Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 54010196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 5417120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5427120Sgblack@eecs.umich.edu { 5437712Sgblack@eecs.umich.edu return NoFault; 5447120Sgblack@eecs.umich.edu } 5457120Sgblack@eecs.umich.edu}}; 5467120Sgblack@eecs.umich.edu 5477639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5487639Sgblack@eecs.umich.edu template <class Element> 5497639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 55010196SCurtis.Dunham@arm.com PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 5517639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5527639Sgblack@eecs.umich.edu { 5537712Sgblack@eecs.umich.edu return NoFault; 5547639Sgblack@eecs.umich.edu } 5557639Sgblack@eecs.umich.edu}}; 5567639Sgblack@eecs.umich.edu 5577303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 5587303Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 55910196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT *xc, 5607303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5617303Sgblack@eecs.umich.edu { 5627303Sgblack@eecs.umich.edu Fault fault = NoFault; 5637303Sgblack@eecs.umich.edu 5647303Sgblack@eecs.umich.edu %(op_decl)s; 5657303Sgblack@eecs.umich.edu %(op_rd)s; 5667303Sgblack@eecs.umich.edu 5677303Sgblack@eecs.umich.edu if (%(predicate_test)s) 5687303Sgblack@eecs.umich.edu { 5697303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5707303Sgblack@eecs.umich.edu %(postacc_code)s; 5717303Sgblack@eecs.umich.edu 5727303Sgblack@eecs.umich.edu if (fault == NoFault) { 5737303Sgblack@eecs.umich.edu %(op_wb)s; 5747303Sgblack@eecs.umich.edu } 5757303Sgblack@eecs.umich.edu } 5767303Sgblack@eecs.umich.edu 5777303Sgblack@eecs.umich.edu return fault; 5787303Sgblack@eecs.umich.edu } 5797303Sgblack@eecs.umich.edu}}; 5807303Sgblack@eecs.umich.edu 5817291Sgblack@eecs.umich.edudef template RfeDeclare {{ 5827291Sgblack@eecs.umich.edu /** 5837291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5847291Sgblack@eecs.umich.edu */ 5857291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5867291Sgblack@eecs.umich.edu { 5877291Sgblack@eecs.umich.edu public: 5887291Sgblack@eecs.umich.edu 5897291Sgblack@eecs.umich.edu /// Constructor. 5907291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5917291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5927291Sgblack@eecs.umich.edu 5937291Sgblack@eecs.umich.edu %(BasicExecDeclare)s 5947291Sgblack@eecs.umich.edu 5957291Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 5967291Sgblack@eecs.umich.edu 5977291Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 5987291Sgblack@eecs.umich.edu }; 5997291Sgblack@eecs.umich.edu}}; 6007291Sgblack@eecs.umich.edu 6017312Sgblack@eecs.umich.edudef template SrsDeclare {{ 6027312Sgblack@eecs.umich.edu /** 6037312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6047312Sgblack@eecs.umich.edu */ 6057312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6067312Sgblack@eecs.umich.edu { 6077312Sgblack@eecs.umich.edu public: 6087312Sgblack@eecs.umich.edu 6097312Sgblack@eecs.umich.edu /// Constructor. 6107312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6117312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6127312Sgblack@eecs.umich.edu 6137312Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6147312Sgblack@eecs.umich.edu 6157312Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6167312Sgblack@eecs.umich.edu 6177312Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6187312Sgblack@eecs.umich.edu }; 6197312Sgblack@eecs.umich.edu}}; 6207312Sgblack@eecs.umich.edu 6217205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6227205Sgblack@eecs.umich.edu /** 6237205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6247205Sgblack@eecs.umich.edu */ 6257205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6267205Sgblack@eecs.umich.edu { 6277205Sgblack@eecs.umich.edu public: 6287205Sgblack@eecs.umich.edu 6297205Sgblack@eecs.umich.edu /// Constructor. 6307205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6317205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6327205Sgblack@eecs.umich.edu 6337205Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6347205Sgblack@eecs.umich.edu 6357205Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6367205Sgblack@eecs.umich.edu 6377205Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6387205Sgblack@eecs.umich.edu }; 6397205Sgblack@eecs.umich.edu}}; 6407205Sgblack@eecs.umich.edu 6417279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6427279Sgblack@eecs.umich.edu /** 6437279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6447279Sgblack@eecs.umich.edu */ 6457279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6467279Sgblack@eecs.umich.edu { 6477279Sgblack@eecs.umich.edu public: 6487279Sgblack@eecs.umich.edu 6497279Sgblack@eecs.umich.edu /// Constructor. 6507279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6517279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6527279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6537279Sgblack@eecs.umich.edu 6547279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6557279Sgblack@eecs.umich.edu 6567279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6577279Sgblack@eecs.umich.edu 6587279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6597279Sgblack@eecs.umich.edu }; 6607279Sgblack@eecs.umich.edu}}; 6617279Sgblack@eecs.umich.edu 6627303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6637303Sgblack@eecs.umich.edu /** 6647303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6657303Sgblack@eecs.umich.edu */ 6667303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6677303Sgblack@eecs.umich.edu { 6687303Sgblack@eecs.umich.edu public: 6697303Sgblack@eecs.umich.edu 6707303Sgblack@eecs.umich.edu /// Constructor. 6717303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6727303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6737303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6747303Sgblack@eecs.umich.edu 6757303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6767303Sgblack@eecs.umich.edu 6777303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6787303Sgblack@eecs.umich.edu 6797303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 6807303Sgblack@eecs.umich.edu }; 6817303Sgblack@eecs.umich.edu}}; 6827303Sgblack@eecs.umich.edu 6837119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6847119Sgblack@eecs.umich.edu /** 6857119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6867119Sgblack@eecs.umich.edu */ 6877119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6887119Sgblack@eecs.umich.edu { 6897119Sgblack@eecs.umich.edu public: 6907119Sgblack@eecs.umich.edu 6917119Sgblack@eecs.umich.edu /// Constructor. 6927119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6937119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6947119Sgblack@eecs.umich.edu 6957119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 6967119Sgblack@eecs.umich.edu 6977119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 6987119Sgblack@eecs.umich.edu 6997119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 70010037SARM gem5 Developers 70110037SARM gem5 Developers virtual void 70210037SARM gem5 Developers annotateFault(ArmFault *fault) { 70310037SARM gem5 Developers %(fa_code)s 70410037SARM gem5 Developers } 7057119Sgblack@eecs.umich.edu }; 7067119Sgblack@eecs.umich.edu}}; 7077119Sgblack@eecs.umich.edu 7087303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 7097303Sgblack@eecs.umich.edu /** 7107303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7117303Sgblack@eecs.umich.edu */ 7127303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7137303Sgblack@eecs.umich.edu { 7147303Sgblack@eecs.umich.edu public: 7157303Sgblack@eecs.umich.edu 7167303Sgblack@eecs.umich.edu /// Constructor. 7177303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7187303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7197303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7207303Sgblack@eecs.umich.edu 7217303Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7227303Sgblack@eecs.umich.edu 7237303Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7247303Sgblack@eecs.umich.edu 7257303Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7267303Sgblack@eecs.umich.edu }; 7277303Sgblack@eecs.umich.edu}}; 7287303Sgblack@eecs.umich.edu 7297646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 7307279Sgblack@eecs.umich.edu /** 7317279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7327279Sgblack@eecs.umich.edu */ 7337279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7347279Sgblack@eecs.umich.edu { 7357279Sgblack@eecs.umich.edu public: 7367279Sgblack@eecs.umich.edu 7377279Sgblack@eecs.umich.edu /// Constructor. 7387279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7397279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7407279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7417279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7427279Sgblack@eecs.umich.edu uint32_t _index); 7437279Sgblack@eecs.umich.edu 7447279Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7457279Sgblack@eecs.umich.edu 7467279Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7477279Sgblack@eecs.umich.edu 7487279Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 7497279Sgblack@eecs.umich.edu }; 7507279Sgblack@eecs.umich.edu}}; 7517279Sgblack@eecs.umich.edu 7527646Sgene.wu@arm.comdef template StoreRegDeclare {{ 7537119Sgblack@eecs.umich.edu /** 7547119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7557119Sgblack@eecs.umich.edu */ 7567119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7577119Sgblack@eecs.umich.edu { 7587119Sgblack@eecs.umich.edu public: 7597119Sgblack@eecs.umich.edu 7607119Sgblack@eecs.umich.edu /// Constructor. 7617119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7627119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7637119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7647119Sgblack@eecs.umich.edu uint32_t _index); 7657119Sgblack@eecs.umich.edu 7667119Sgblack@eecs.umich.edu %(BasicExecDeclare)s 7677119Sgblack@eecs.umich.edu 7687119Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 7697119Sgblack@eecs.umich.edu 7707119Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 77110037SARM gem5 Developers 77210037SARM gem5 Developers virtual void 77310037SARM gem5 Developers annotateFault(ArmFault *fault) { 77410037SARM gem5 Developers %(fa_code)s 77510037SARM gem5 Developers } 7767119Sgblack@eecs.umich.edu }; 7777119Sgblack@eecs.umich.edu}}; 7787119Sgblack@eecs.umich.edu 7797646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 7807646Sgene.wu@arm.com /** 7817646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7827646Sgene.wu@arm.com */ 7837646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7847646Sgene.wu@arm.com { 7857646Sgene.wu@arm.com public: 7867646Sgene.wu@arm.com 7877646Sgene.wu@arm.com /// Constructor. 7887646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 7897646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 7907646Sgene.wu@arm.com uint32_t _base, bool _add, 7917646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 7927646Sgene.wu@arm.com uint32_t _index); 7937646Sgene.wu@arm.com 7947646Sgene.wu@arm.com %(BasicExecDeclare)s 7957646Sgene.wu@arm.com 7967646Sgene.wu@arm.com %(InitiateAccDeclare)s 7977646Sgene.wu@arm.com 7987646Sgene.wu@arm.com %(CompleteAccDeclare)s 7997646Sgene.wu@arm.com }; 8007646Sgene.wu@arm.com}}; 8017646Sgene.wu@arm.com 8027646Sgene.wu@arm.comdef template LoadRegDeclare {{ 8037646Sgene.wu@arm.com /** 8047646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8057646Sgene.wu@arm.com */ 8067646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8077646Sgene.wu@arm.com { 8087646Sgene.wu@arm.com public: 8097646Sgene.wu@arm.com 8107646Sgene.wu@arm.com /// Constructor. 8117646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8127646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 8137646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 8147646Sgene.wu@arm.com uint32_t _index); 8157646Sgene.wu@arm.com 8167646Sgene.wu@arm.com %(BasicExecDeclare)s 8177646Sgene.wu@arm.com 8187646Sgene.wu@arm.com %(InitiateAccDeclare)s 8197646Sgene.wu@arm.com 8207646Sgene.wu@arm.com %(CompleteAccDeclare)s 82110037SARM gem5 Developers 82210037SARM gem5 Developers virtual void 82310037SARM gem5 Developers annotateFault(ArmFault *fault) { 82410037SARM gem5 Developers %(fa_code)s 82510037SARM gem5 Developers } 8267646Sgene.wu@arm.com }; 8277646Sgene.wu@arm.com}}; 8287646Sgene.wu@arm.com 8297646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8307646Sgene.wu@arm.com /** 8317646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8327646Sgene.wu@arm.com */ 8337646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8347646Sgene.wu@arm.com { 8357646Sgene.wu@arm.com public: 8367646Sgene.wu@arm.com 8377646Sgene.wu@arm.com /// Constructor. 8387646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8397646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8407646Sgene.wu@arm.com 8417646Sgene.wu@arm.com %(BasicExecDeclare)s 8427646Sgene.wu@arm.com 8437646Sgene.wu@arm.com %(InitiateAccDeclare)s 8447646Sgene.wu@arm.com 8457646Sgene.wu@arm.com %(CompleteAccDeclare)s 84610037SARM gem5 Developers 84710037SARM gem5 Developers virtual void 84810037SARM gem5 Developers annotateFault(ArmFault *fault) { 84910037SARM gem5 Developers %(fa_code)s 85010037SARM gem5 Developers } 8517646Sgene.wu@arm.com }; 8527646Sgene.wu@arm.com}}; 8537646Sgene.wu@arm.com 8547119Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 8557119Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 8567119Sgblack@eecs.umich.edu}}; 8577119Sgblack@eecs.umich.edu 8587119Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 8597119Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 8607119Sgblack@eecs.umich.edu}}; 8617119Sgblack@eecs.umich.edu 8627291Sgblack@eecs.umich.edudef template RfeConstructor {{ 86310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8648140SMatt.Horsnell@arm.com uint32_t _base, int _mode, bool _wb) 8658140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8668140SMatt.Horsnell@arm.com (IntRegIndex)_base, (AddrMode)_mode, _wb) 8677291Sgblack@eecs.umich.edu { 8687291Sgblack@eecs.umich.edu %(constructor)s; 8697848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8707848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8717848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8727848SAli.Saidi@ARM.com } 8737848SAli.Saidi@ARM.com } 8747646Sgene.wu@arm.com#if %(use_uops)d 8758140SMatt.Horsnell@arm.com uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8768140SMatt.Horsnell@arm.com int uopIdx = 0; 8778140SMatt.Horsnell@arm.com uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8788140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8798140SMatt.Horsnell@arm.com#if %(use_wb)d 8808140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(wb_decl)s; 8818140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8828140SMatt.Horsnell@arm.com#endif 8838140SMatt.Horsnell@arm.com#if %(use_pc)d 8848140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(pc_decl)s; 8858140SMatt.Horsnell@arm.com#endif 88610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 8878140SMatt.Horsnell@arm.com uops[uopIdx]->setLastMicroop(); 8887646Sgene.wu@arm.com#endif 8897291Sgblack@eecs.umich.edu } 8907291Sgblack@eecs.umich.edu}}; 8917291Sgblack@eecs.umich.edu 8927312Sgblack@eecs.umich.edudef template SrsConstructor {{ 89310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8947312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8957312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8967312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8977312Sgblack@eecs.umich.edu { 8987312Sgblack@eecs.umich.edu %(constructor)s; 8997848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9007848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9017848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9027848SAli.Saidi@ARM.com } 9037848SAli.Saidi@ARM.com } 9047646Sgene.wu@arm.com#if %(use_uops)d 9057646Sgene.wu@arm.com assert(numMicroops >= 2); 9067646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9077646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 9087724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 90910666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9107646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9117646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9127646Sgene.wu@arm.com#endif 9137312Sgblack@eecs.umich.edu } 9147312Sgblack@eecs.umich.edu}}; 9157312Sgblack@eecs.umich.edu 9167205Sgblack@eecs.umich.edudef template SwapConstructor {{ 91710184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9187205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 9197205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9207205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 9217205Sgblack@eecs.umich.edu { 9227205Sgblack@eecs.umich.edu %(constructor)s; 9237848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9247848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9257848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9267848SAli.Saidi@ARM.com } 9277848SAli.Saidi@ARM.com } 9287205Sgblack@eecs.umich.edu } 9297205Sgblack@eecs.umich.edu}}; 9307205Sgblack@eecs.umich.edu 9317279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 93210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9337279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9347279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9357279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9367279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9377279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9387279Sgblack@eecs.umich.edu { 9397279Sgblack@eecs.umich.edu %(constructor)s; 9407848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9417848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9427848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9437848SAli.Saidi@ARM.com } 9447848SAli.Saidi@ARM.com } 9457646Sgene.wu@arm.com#if %(use_uops)d 9467646Sgene.wu@arm.com assert(numMicroops >= 2); 9477646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9487646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 94910666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9507724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9517646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9527646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9537646Sgene.wu@arm.com#endif 9547279Sgblack@eecs.umich.edu } 9557279Sgblack@eecs.umich.edu}}; 9567279Sgblack@eecs.umich.edu 9577303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 95810184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9597303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9607303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9617303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9627303Sgblack@eecs.umich.edu (IntRegIndex)_result, 9637303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9647303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9657303Sgblack@eecs.umich.edu { 9667303Sgblack@eecs.umich.edu %(constructor)s; 9677848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9687848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9697848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9707848SAli.Saidi@ARM.com } 9717848SAli.Saidi@ARM.com } 9727646Sgene.wu@arm.com#if %(use_uops)d 9737646Sgene.wu@arm.com assert(numMicroops >= 2); 9747646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9757646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9767646Sgene.wu@arm.com _base, _add, _imm); 9777724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 97810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9797646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9807646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9817646Sgene.wu@arm.com#endif 9827303Sgblack@eecs.umich.edu } 9837303Sgblack@eecs.umich.edu}}; 9847303Sgblack@eecs.umich.edu 9857119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 98610184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9877119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9887119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9897119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9907119Sgblack@eecs.umich.edu { 9917119Sgblack@eecs.umich.edu %(constructor)s; 9927848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9937848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9947848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9957848SAli.Saidi@ARM.com } 9967848SAli.Saidi@ARM.com } 9977646Sgene.wu@arm.com#if %(use_uops)d 9987646Sgene.wu@arm.com assert(numMicroops >= 2); 9997646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10007646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 10017724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 100210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10037646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10047646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10057646Sgene.wu@arm.com#endif 10067119Sgblack@eecs.umich.edu } 10077119Sgblack@eecs.umich.edu}}; 10087119Sgblack@eecs.umich.edu 10097303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 101010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10117303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 10127303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 10137303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10147303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 10157303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 10167303Sgblack@eecs.umich.edu { 10177303Sgblack@eecs.umich.edu %(constructor)s; 10187848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10197848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10207848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10217848SAli.Saidi@ARM.com } 10227848SAli.Saidi@ARM.com } 10237646Sgene.wu@arm.com#if %(use_uops)d 10247646Sgene.wu@arm.com assert(numMicroops >= 2); 10257646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10267646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10277646Sgene.wu@arm.com _base, _add, _imm); 10287724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 102910666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10307646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10317646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10327646Sgene.wu@arm.com#endif 10337303Sgblack@eecs.umich.edu } 10347303Sgblack@eecs.umich.edu}}; 10357303Sgblack@eecs.umich.edu 10367646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 103710184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10387279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10397279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10407279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10417279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10427279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10437279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10447279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10457279Sgblack@eecs.umich.edu { 10467279Sgblack@eecs.umich.edu %(constructor)s; 10477848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10487848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10497848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10507848SAli.Saidi@ARM.com } 10517848SAli.Saidi@ARM.com } 10527646Sgene.wu@arm.com#if %(use_uops)d 10537646Sgene.wu@arm.com assert(numMicroops >= 2); 10547646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10557646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10567646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10577724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 105810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10597646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10607646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10617646Sgene.wu@arm.com#endif 10627279Sgblack@eecs.umich.edu } 10637279Sgblack@eecs.umich.edu}}; 10647279Sgblack@eecs.umich.edu 10657646Sgene.wu@arm.comdef template StoreRegConstructor {{ 106610184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10677119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10687119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10697119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10707119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10717119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10727119Sgblack@eecs.umich.edu (IntRegIndex)_index) 10737119Sgblack@eecs.umich.edu { 10747119Sgblack@eecs.umich.edu %(constructor)s; 10757848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10767848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10777848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10787848SAli.Saidi@ARM.com } 10797848SAli.Saidi@ARM.com } 10807646Sgene.wu@arm.com#if %(use_uops)d 10817646Sgene.wu@arm.com assert(numMicroops >= 2); 10827646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10837646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10847646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10857724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 108610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10877646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10887646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10897646Sgene.wu@arm.com#endif 10907119Sgblack@eecs.umich.edu } 10917119Sgblack@eecs.umich.edu}}; 10927646Sgene.wu@arm.com 10937646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 109410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10957646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10967646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10977646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10987646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 10997646Sgene.wu@arm.com (IntRegIndex)_base, _add, 11007646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11017646Sgene.wu@arm.com (IntRegIndex)_index) 11027646Sgene.wu@arm.com { 11037646Sgene.wu@arm.com %(constructor)s; 11047848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11057848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11067848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11077848SAli.Saidi@ARM.com } 11087848SAli.Saidi@ARM.com } 11097646Sgene.wu@arm.com#if %(use_uops)d 11107646Sgene.wu@arm.com assert(numMicroops >= 2); 11117646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11127646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 11137646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11147646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11157724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 111610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11177646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11187646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11197724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11207646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11217646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11227646Sgene.wu@arm.com } else { 11237646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11247646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11257646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11267724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 112710666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11287646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11297646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11307646Sgene.wu@arm.com } 11317646Sgene.wu@arm.com#endif 11327646Sgene.wu@arm.com } 11337646Sgene.wu@arm.com}}; 11347646Sgene.wu@arm.com 11357646Sgene.wu@arm.comdef template LoadRegConstructor {{ 113610184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 11377646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11387646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11397646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11407646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11417646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11427646Sgene.wu@arm.com (IntRegIndex)_index) 11437646Sgene.wu@arm.com { 11447646Sgene.wu@arm.com %(constructor)s; 11458607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11467848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11478203SAli.Saidi@ARM.com conditional = true; 11487848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11497848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11507848SAli.Saidi@ARM.com } 11517848SAli.Saidi@ARM.com } 11527646Sgene.wu@arm.com#if %(use_uops)d 11537646Sgene.wu@arm.com assert(numMicroops >= 2); 11547646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 11559573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 11567646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11577646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11587646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11597724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 116010666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11617646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11627724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11637646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11648203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 11658203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11668203SAli.Saidi@ARM.com if (conditional) 11678203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 11688203SAli.Saidi@ARM.com else 11698203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 11707646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11717646Sgene.wu@arm.com } else if(_dest == _index) { 11727646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11737646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11747724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 117510666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11767646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11777646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11787724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11797646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11807646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11817646Sgene.wu@arm.com } else { 11827646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11837646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11847646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11857724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 118610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11877646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11887646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11897646Sgene.wu@arm.com 11907646Sgene.wu@arm.com } 11919250SAli.Saidi@ARM.com#else 11929573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 11939250SAli.Saidi@ARM.com flags[IsControl] = true; 11949250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 11959250SAli.Saidi@ARM.com if (conditional) 11969250SAli.Saidi@ARM.com flags[IsCondControl] = true; 11979250SAli.Saidi@ARM.com else 11989250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 11999250SAli.Saidi@ARM.com } 12007646Sgene.wu@arm.com#endif 12017646Sgene.wu@arm.com } 12027646Sgene.wu@arm.com}}; 12037646Sgene.wu@arm.com 12047646Sgene.wu@arm.comdef template LoadImmConstructor {{ 120510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 12067646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 12077646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 12087646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 12097646Sgene.wu@arm.com { 12107646Sgene.wu@arm.com %(constructor)s; 12118607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 12127848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 12138203SAli.Saidi@ARM.com conditional = true; 12147848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 12157848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 12167848SAli.Saidi@ARM.com } 12177848SAli.Saidi@ARM.com } 12187646Sgene.wu@arm.com#if %(use_uops)d 12197646Sgene.wu@arm.com assert(numMicroops >= 2); 12207646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 12219573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 12227646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 12237646Sgene.wu@arm.com _imm); 12247724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 122510666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12267646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12277724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12287646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12298203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 12308203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 123110199SAndrew.Bardsley@arm.com /* Also set flags on the macroop so that pre-microop decomposition 123210199SAndrew.Bardsley@arm.com branch prediction can work */ 123310199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsControl); 123410199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsIndirectControl); 123510199SAndrew.Bardsley@arm.com if (conditional) { 12368203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 123710199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsCondControl); 123810199SAndrew.Bardsley@arm.com } else { 12398203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 124010199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsUncondControl); 124110199SAndrew.Bardsley@arm.com } 124210199SAndrew.Bardsley@arm.com if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) { 12438203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsReturn); 124410199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsReturn); 124510199SAndrew.Bardsley@arm.com } 12467646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12477646Sgene.wu@arm.com } else { 12487646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12497724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 125010666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12517646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12527646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12537646Sgene.wu@arm.com } 12549250SAli.Saidi@ARM.com#else 12559573Ssaidi@eecs.umich.edu if (_dest == INTREG_PC && !isFloating()) { 12569250SAli.Saidi@ARM.com flags[IsControl] = true; 12579250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 12589250SAli.Saidi@ARM.com if (conditional) 12599250SAli.Saidi@ARM.com flags[IsCondControl] = true; 12609250SAli.Saidi@ARM.com else 12619250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 12629250SAli.Saidi@ARM.com } 12637646Sgene.wu@arm.com#endif 12647646Sgene.wu@arm.com } 12657646Sgene.wu@arm.com}}; 12667646Sgene.wu@arm.com 1267