macromem.isa revision 7848
19243SN/A// -*- mode:c++ -*-
210206Sandreas.hansson@arm.com
39243SN/A// Copyright (c) 2010 ARM Limited
49243SN/A// All rights reserved
59243SN/A//
69243SN/A// The license below extends only to copyright in the software and shall
79243SN/A// not be construed as granting a license to any other intellectual
89243SN/A// property including but not limited to intellectual property relating
99243SN/A// to a hardware implementation of the functionality of the software
109243SN/A// licensed hereunder.  You may use the software subject to the license
119243SN/A// terms below provided that you ensure that this notice is replicated
129243SN/A// unmodified and in its entirety in all distributions of the software,
139243SN/A// modified or unmodified, in source code or in binary form.
149831SN/A//
159831SN/A// Copyright (c) 2007-2008 The Florida State University
169831SN/A// All rights reserved.
179243SN/A//
189243SN/A// Redistribution and use in source and binary forms, with or without
199243SN/A// modification, are permitted provided that the following conditions are
209243SN/A// met: redistributions of source code must retain the above copyright
219243SN/A// notice, this list of conditions and the following disclaimer;
229243SN/A// redistributions in binary form must reproduce the above copyright
239243SN/A// notice, this list of conditions and the following disclaimer in the
249243SN/A// documentation and/or other materials provided with the distribution;
259243SN/A// neither the name of the copyright holders nor the names of its
269243SN/A// contributors may be used to endorse or promote products derived from
279243SN/A// this software without specific prior written permission.
289243SN/A//
299243SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
309243SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
319243SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
329243SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
339243SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
349243SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
359243SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
369243SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
379243SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
389243SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
399243SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
409243SN/A//
419243SN/A// Authors: Stephen Hines
429967SN/A//          Gabe Black
439243SN/A
449243SN/A////////////////////////////////////////////////////////////////////
4510146Sandreas.hansson@arm.com//
469356SN/A// Load/store microops
4710146Sandreas.hansson@arm.com//
4810247Sandreas.hansson@arm.com
4910208Sandreas.hansson@arm.comdef template MicroMemDeclare {{
509352SN/A    class %(class_name)s : public %(base_class)s
5110146Sandreas.hansson@arm.com    {
529814SN/A      public:
539243SN/A        %(class_name)s(ExtMachInst machInst,
549243SN/A                       RegIndex _ura, RegIndex _urb, bool _up,
559243SN/A                       uint8_t _imm);
5610146Sandreas.hansson@arm.com        %(BasicExecDeclare)s
579243SN/A        %(InitiateAccDeclare)s
589243SN/A        %(CompleteAccDeclare)s
599243SN/A    };
6010211Sandreas.hansson@arm.com}};
6110208Sandreas.hansson@arm.com
6210208Sandreas.hansson@arm.comdef template MicroMemConstructor {{
6310208Sandreas.hansson@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst,
649831SN/A                                   RegIndex _ura,
659831SN/A                                   RegIndex _urb,
669831SN/A                                   bool _up,
679831SN/A                                   uint8_t _imm)
689831SN/A        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
6910140SN/A                         _ura, _urb, _up, _imm)
7010286Sandreas.hansson@arm.com    {
719243SN/A        %(constructor)s;
7210394Swendy.elsasser@arm.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
7310394Swendy.elsasser@arm.com            for (int x = 0; x < _numDestRegs; x++) {
749566SN/A                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
759243SN/A            }
769243SN/A        }
7710140SN/A    }
7810140SN/A}};
7910147Sandreas.hansson@arm.com
8010147Sandreas.hansson@arm.com////////////////////////////////////////////////////////////////////
8110393Swendy.elsasser@arm.com//
8210394Swendy.elsasser@arm.com// Neon load/store microops
8310394Swendy.elsasser@arm.com//
8410394Swendy.elsasser@arm.com
859243SN/Adef template MicroNeonMemDeclare {{
869243SN/A    template <class Element>
8710141SN/A    class %(class_name)s : public %(base_class)s
889726SN/A    {
899726SN/A      public:
9010208Sandreas.hansson@arm.com        %(class_name)s(ExtMachInst machInst, RegIndex _dest,
9110208Sandreas.hansson@arm.com                       RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
9210393Swendy.elsasser@arm.com            : %(base_class)s("%(mnemonic)s", machInst,
9310393Swendy.elsasser@arm.com                              %(op_class)s, _dest, _ura, _imm)
949243SN/A        {
959243SN/A            memAccessFlags |= extraMemFlags;
969243SN/A            %(constructor)s;
979243SN/A            if (!(condCode == COND_AL || condCode == COND_UC)) {
989969SN/A                for (int x = 0; x < _numDestRegs; x++) {
999243SN/A                    _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1009243SN/A                }
1019969SN/A            }
1029243SN/A        }
1039243SN/A
10410246Sandreas.hansson@arm.com        %(BasicExecDeclare)s
10510246Sandreas.hansson@arm.com        %(InitiateAccDeclare)s
10610246Sandreas.hansson@arm.com        %(CompleteAccDeclare)s
10710246Sandreas.hansson@arm.com    };
10810246Sandreas.hansson@arm.com}};
10910394Swendy.elsasser@arm.com
11010394Swendy.elsasser@arm.com////////////////////////////////////////////////////////////////////
11110394Swendy.elsasser@arm.com//
11210394Swendy.elsasser@arm.com// Integer = Integer op Integer microops
11310394Swendy.elsasser@arm.com//
11410394Swendy.elsasser@arm.com
11510394Swendy.elsasser@arm.comdef template MicroIntDeclare {{
11610394Swendy.elsasser@arm.com    class %(class_name)s : public %(base_class)s
11710394Swendy.elsasser@arm.com    {
11810394Swendy.elsasser@arm.com      public:
11910394Swendy.elsasser@arm.com        %(class_name)s(ExtMachInst machInst,
12010394Swendy.elsasser@arm.com                       RegIndex _ura, RegIndex _urb, RegIndex _urc);
12110394Swendy.elsasser@arm.com        %(BasicExecDeclare)s
12210246Sandreas.hansson@arm.com    };
12310246Sandreas.hansson@arm.com}};
12410246Sandreas.hansson@arm.com
12510140SN/Adef template MicroIntConstructor {{
12610140SN/A    %(class_name)s::%(class_name)s(ExtMachInst machInst,
12710140SN/A                                   RegIndex _ura,
12810140SN/A                                   RegIndex _urb,
12910140SN/A                                   RegIndex _urc)
1309243SN/A        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1319243SN/A                         _ura, _urb, _urc)
1329567SN/A    {
1339243SN/A        %(constructor)s;
1349243SN/A        if (!(condCode == COND_AL || condCode == COND_UC)) {
1359243SN/A            for (int x = 0; x < _numDestRegs; x++) {
1369831SN/A                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1379831SN/A            }
1389831SN/A        }
1399831SN/A    }
1409831SN/A}};
1419243SN/A
14210286Sandreas.hansson@arm.comdef template MicroNeonMemExecDeclare {{
1439566SN/A    template
1449566SN/A    Fault %(class_name)s<%(targs)s>::execute(
14510143SN/A            %(CPU_exec_context)s *, Trace::InstRecord *) const;
1469566SN/A    template
1479566SN/A    Fault %(class_name)s<%(targs)s>::initiateAcc(
14810136SN/A            %(CPU_exec_context)s *, Trace::InstRecord *) const;
1499831SN/A    template
15010286Sandreas.hansson@arm.com    Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
15110136SN/A            %(CPU_exec_context)s *, Trace::InstRecord *) const;
1529566SN/A}};
15310286Sandreas.hansson@arm.com
15410286Sandreas.hansson@arm.comdef template MicroNeonExecDeclare {{
15510286Sandreas.hansson@arm.com    template
15610286Sandreas.hansson@arm.com    Fault %(class_name)s<%(targs)s>::execute(
15710286Sandreas.hansson@arm.com            %(CPU_exec_context)s *, Trace::InstRecord *) const;
15810286Sandreas.hansson@arm.com}};
15910286Sandreas.hansson@arm.com
16010286Sandreas.hansson@arm.com////////////////////////////////////////////////////////////////////
16110286Sandreas.hansson@arm.com//
16210286Sandreas.hansson@arm.com// Neon (de)interlacing microops
16310286Sandreas.hansson@arm.com//
16410286Sandreas.hansson@arm.com
16510286Sandreas.hansson@arm.comdef template MicroNeonMixDeclare {{
16610286Sandreas.hansson@arm.com    template <class Element>
16710286Sandreas.hansson@arm.com    class %(class_name)s : public %(base_class)s
16810286Sandreas.hansson@arm.com    {
1699669SN/A      public:
17010286Sandreas.hansson@arm.com        %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
17110286Sandreas.hansson@arm.com                       uint8_t _step) :
17210286Sandreas.hansson@arm.com            %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
17310286Sandreas.hansson@arm.com                           _dest, _op1, _step)
17410286Sandreas.hansson@arm.com        {
17510286Sandreas.hansson@arm.com            %(constructor)s;
17610286Sandreas.hansson@arm.com            if (!(condCode == COND_AL || condCode == COND_UC)) {
17710286Sandreas.hansson@arm.com                for (int x = 0; x < _numDestRegs; x++) {
1789566SN/A                    _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1799566SN/A                }
18010207Sandreas.hansson@arm.com            }
18110207Sandreas.hansson@arm.com        }
18210207Sandreas.hansson@arm.com
18310207Sandreas.hansson@arm.com        %(BasicExecDeclare)s
18410207Sandreas.hansson@arm.com    };
18510207Sandreas.hansson@arm.com}};
18610394Swendy.elsasser@arm.com
18710394Swendy.elsasser@arm.comdef template MicroNeonMixExecute {{
18810394Swendy.elsasser@arm.com    template <class Element>
18910394Swendy.elsasser@arm.com    Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
19010394Swendy.elsasser@arm.com            Trace::InstRecord *traceData) const
19110394Swendy.elsasser@arm.com    {
19210394Swendy.elsasser@arm.com        Fault fault = NoFault;
19310394Swendy.elsasser@arm.com        uint64_t resTemp = 0;
19410394Swendy.elsasser@arm.com        resTemp = resTemp;
19510394Swendy.elsasser@arm.com        %(op_decl)s;
19610394Swendy.elsasser@arm.com        %(op_rd)s;
19710394Swendy.elsasser@arm.com
19810394Swendy.elsasser@arm.com        if (%(predicate_test)s)
19910394Swendy.elsasser@arm.com        {
20010394Swendy.elsasser@arm.com            %(code)s;
20110394Swendy.elsasser@arm.com            if (fault == NoFault)
20210394Swendy.elsasser@arm.com            {
20310394Swendy.elsasser@arm.com                %(op_wb)s;
20410394Swendy.elsasser@arm.com            }
20510394Swendy.elsasser@arm.com        }
20610394Swendy.elsasser@arm.com
20710394Swendy.elsasser@arm.com        if (fault == NoFault && machInst.itstateMask != 0) {
20810394Swendy.elsasser@arm.com            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
20910394Swendy.elsasser@arm.com        }
21010394Swendy.elsasser@arm.com
21110394Swendy.elsasser@arm.com        return fault;
21210394Swendy.elsasser@arm.com    }
21310394Swendy.elsasser@arm.com}};
21410394Swendy.elsasser@arm.com
2159243SN/A////////////////////////////////////////////////////////////////////
2169243SN/A//
2179243SN/A// Neon (un)packing microops using a particular lane
21810146Sandreas.hansson@arm.com//
21910140SN/A
22010140SN/Adef template MicroNeonMixLaneDeclare {{
22110146Sandreas.hansson@arm.com    template <class Element>
22210140SN/A    class %(class_name)s : public %(base_class)s
22310140SN/A    {
22410140SN/A      public:
22510140SN/A        %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
22610140SN/A                       uint8_t _step, unsigned _lane) :
22710140SN/A            %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
22810146Sandreas.hansson@arm.com                           _dest, _op1, _step, _lane)
2299243SN/A        {
23010143SN/A            %(constructor)s;
23110143SN/A            if (!(condCode == COND_AL || condCode == COND_UC)) {
23210208Sandreas.hansson@arm.com                for (int x = 0; x < _numDestRegs; x++) {
23310143SN/A                    _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
23410206Sandreas.hansson@arm.com                }
23510206Sandreas.hansson@arm.com            }
23610206Sandreas.hansson@arm.com        }
23710206Sandreas.hansson@arm.com
23810206Sandreas.hansson@arm.com        %(BasicExecDeclare)s
23910206Sandreas.hansson@arm.com    };
24010207Sandreas.hansson@arm.com}};
24110207Sandreas.hansson@arm.com
24210207Sandreas.hansson@arm.com////////////////////////////////////////////////////////////////////
2439243SN/A//
2449243SN/A// Integer = Integer
2459243SN/A//
24610146Sandreas.hansson@arm.com
2479243SN/Adef template MicroIntMovDeclare {{
2489243SN/A    class %(class_name)s : public %(base_class)s
2499243SN/A    {
2509243SN/A      public:
2519243SN/A        %(class_name)s(ExtMachInst machInst,
2529243SN/A                       RegIndex _ura, RegIndex _urb);
2539243SN/A        %(BasicExecDeclare)s
2549243SN/A    };
2559243SN/A}};
2569243SN/Adef template MicroIntMovConstructor {{
2579243SN/A    %(class_name)s::%(class_name)s(ExtMachInst machInst,
2589243SN/A                                   RegIndex _ura,
2599243SN/A                                   RegIndex _urb)
2609243SN/A        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
2619243SN/A                         _ura, _urb)
2629243SN/A    {
26310146Sandreas.hansson@arm.com        %(constructor)s;
2649243SN/A        if (!(condCode == COND_AL || condCode == COND_UC)) {
2659831SN/A            for (int x = 0; x < _numDestRegs; x++) {
2669831SN/A                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
2679831SN/A            }
2689243SN/A        }
2699831SN/A    }
2709831SN/A}};
2719243SN/A
2729243SN/A////////////////////////////////////////////////////////////////////
2739243SN/A//
27410146Sandreas.hansson@arm.com// Integer = Integer op Immediate microops
2759243SN/A//
2769831SN/A
2779831SN/Adef template MicroIntImmDeclare {{
2789831SN/A    class %(class_name)s : public %(base_class)s
2799243SN/A    {
2809243SN/A      public:
28110146Sandreas.hansson@arm.com        %(class_name)s(ExtMachInst machInst,
28210146Sandreas.hansson@arm.com                       RegIndex _ura, RegIndex _urb,
28310143SN/A                       int32_t _imm);
2849243SN/A        %(BasicExecDeclare)s
2859669SN/A    };
28610136SN/A}};
28710136SN/A
2889243SN/Adef template MicroIntImmConstructor {{
2899967SN/A    %(class_name)s::%(class_name)s(ExtMachInst machInst,
29010245Sandreas.hansson@arm.com                                   RegIndex _ura,
29110245Sandreas.hansson@arm.com                                   RegIndex _urb,
29210245Sandreas.hansson@arm.com                                   int32_t _imm)
2939243SN/A        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
29410286Sandreas.hansson@arm.com                         _ura, _urb, _imm)
29510286Sandreas.hansson@arm.com    {
2969831SN/A        %(constructor)s;
2979243SN/A        if (!(condCode == COND_AL || condCode == COND_UC)) {
2989491SN/A            for (int x = 0; x < _numDestRegs; x++) {
2999831SN/A                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
30010136SN/A            }
3019491SN/A        }
3029491SN/A    }
3039831SN/A}};
3049243SN/A
3059669SN/Adef template MicroIntRegDeclare {{
3069566SN/A    class %(class_name)s : public %(base_class)s
3079566SN/A    {
3089669SN/A      public:
3099669SN/A        %(class_name)s(ExtMachInst machInst,
3109669SN/A                       RegIndex _ura, RegIndex _urb, RegIndex _urc,
3119669SN/A                       int32_t _shiftAmt, ArmShiftType _shiftType);
3129669SN/A        %(BasicExecDeclare)s
3139669SN/A    };
3149669SN/A}};
3159669SN/A
3169669SN/Adef template MicroIntRegConstructor {{
3179669SN/A    %(class_name)s::%(class_name)s(ExtMachInst machInst,
3189669SN/A                                   RegIndex _ura, RegIndex _urb, RegIndex _urc,
3199669SN/A                                   int32_t _shiftAmt, ArmShiftType _shiftType)
3209669SN/A        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
32110136SN/A                         _ura, _urb, _urc, _shiftAmt, _shiftType)
32210286Sandreas.hansson@arm.com    {
32310286Sandreas.hansson@arm.com        %(constructor)s;
32410286Sandreas.hansson@arm.com        if (!(condCode == COND_AL || condCode == COND_UC)) {
3259669SN/A            for (int x = 0; x < _numDestRegs; x++) {
3269669SN/A                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
3279669SN/A            }
32810286Sandreas.hansson@arm.com        }
32910286Sandreas.hansson@arm.com    }
3309669SN/A}};
3319669SN/A
3329491SN/A////////////////////////////////////////////////////////////////////
3339243SN/A//
3349243SN/A// Macro Memory-format instructions
3359243SN/A//
3369491SN/A
3379491SN/Adef template MacroMemDeclare {{
3389243SN/A/**
3399243SN/A * Static instructions class for a store multiple instruction
3409243SN/A */
3419491SN/Aclass %(class_name)s : public %(base_class)s
3429243SN/A{
3439243SN/A    public:
34410136SN/A        // Constructor
3459491SN/A        %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
3469491SN/A                bool index, bool up, bool user, bool writeback, bool load,
3479491SN/A                uint32_t reglist);
34810286Sandreas.hansson@arm.com        %(BasicExecPanic)s
34910286Sandreas.hansson@arm.com};
35010286Sandreas.hansson@arm.com}};
3519566SN/A
3529566SN/Adef template MacroMemConstructor {{
3539566SN/A%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
3549566SN/A        bool index, bool up, bool user, bool writeback, bool load,
3559566SN/A        uint32_t reglist)
3569491SN/A    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
3579491SN/A                     index, up, user, writeback, load, reglist)
3589243SN/A{
3599243SN/A    %(constructor)s;
3609243SN/A    if (!(condCode == COND_AL || condCode == COND_UC)) {
3619491SN/A        for (int x = 0; x < _numDestRegs; x++) {
3629243SN/A            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
3639243SN/A        }
3649243SN/A    }
36510286Sandreas.hansson@arm.com}
36610286Sandreas.hansson@arm.com
3679243SN/A}};
3689491SN/A
3699243SN/Adef template VMemMultDeclare {{
3709243SN/Aclass %(class_name)s : public %(base_class)s
3719243SN/A{
3729243SN/A    public:
3739243SN/A        // Constructor
3749243SN/A        %(class_name)s(ExtMachInst machInst, unsigned width,
3759243SN/A                RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
3769243SN/A                uint32_t size, uint32_t align, RegIndex rm);
37710245Sandreas.hansson@arm.com        %(BasicExecPanic)s
3789243SN/A};
3799243SN/A}};
3809831SN/A
3819243SN/Adef template VMemMultConstructor {{
3829243SN/A%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
3839567SN/A        RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
3849567SN/A        uint32_t size, uint32_t align, RegIndex rm)
3859967SN/A    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
3869967SN/A                     rn, vd, regs, inc, size, align, rm)
3879967SN/A{
3889243SN/A    %(constructor)s;
3899243SN/A    if (!(condCode == COND_AL || condCode == COND_UC)) {
3909243SN/A        for (int x = 0; x < _numDestRegs; x++) {
39110146Sandreas.hansson@arm.com            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
3929243SN/A        }
3939243SN/A    }
3949243SN/A}
3959243SN/A}};
3969243SN/A
3979831SN/Adef template VMemSingleDeclare {{
3989831SN/Aclass %(class_name)s : public %(base_class)s
3999831SN/A{
4009831SN/A    public:
4019831SN/A        // Constructor
4029831SN/A        %(class_name)s(ExtMachInst machInst, bool all, unsigned width,
4039831SN/A                RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
4049831SN/A                uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
4059243SN/A        %(BasicExecPanic)s
4069831SN/A};
4079831SN/A}};
4089831SN/A
4099831SN/Adef template VMemSingleConstructor {{
4109831SN/A%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
4119831SN/A        RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
4129831SN/A        uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
4139243SN/A    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
4149831SN/A                     rn, vd, regs, inc, size, align, rm, lane)
4159831SN/A{
4169831SN/A    %(constructor)s;
4179833SN/A    if (!(condCode == COND_AL || condCode == COND_UC)) {
4189832SN/A        for (int x = 0; x < _numDestRegs; x++) {
4199832SN/A            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
4209832SN/A        }
4219832SN/A    }
4229831SN/A}
4239831SN/A}};
4249831SN/A
4259831SN/Adef template MacroVFPMemDeclare {{
4269831SN/A/**
4279975SN/A * Static instructions class for a store multiple instruction
4289831SN/A */
4299831SN/Aclass %(class_name)s : public %(base_class)s
4309243SN/A{
4319831SN/A    public:
4329831SN/A        // Constructor
4339831SN/A        %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
4349831SN/A                RegIndex vd, bool single, bool up, bool writeback,
4359831SN/A                bool load, uint32_t offset);
4369831SN/A        %(BasicExecPanic)s
4379831SN/A};
4389831SN/A}};
4399831SN/A
4409831SN/Adef template MacroVFPMemConstructor {{
4419831SN/A%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
4429831SN/A        RegIndex vd, bool single, bool up, bool writeback, bool load,
4439966SN/A        uint32_t offset)
4449831SN/A    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
4459831SN/A                     vd, single, up, writeback, load, offset)
4469831SN/A{
4479831SN/A    %(constructor)s;
4489831SN/A    if (!(condCode == COND_AL || condCode == COND_UC)) {
4499831SN/A        for (int x = 0; x < _numDestRegs; x++) {
4509831SN/A            _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
4519831SN/A        }
4529831SN/A    }
4539831SN/A}
4549831SN/A
4559831SN/A}};
4569831SN/A