macromem.isa revision 7169:6cc400372260 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Copyright (c) 2007-2008 The Florida State University
16// All rights reserved.
17//
18// Redistribution and use in source and binary forms, with or without
19// modification, are permitted provided that the following conditions are
20// met: redistributions of source code must retain the above copyright
21// notice, this list of conditions and the following disclaimer;
22// redistributions in binary form must reproduce the above copyright
23// notice, this list of conditions and the following disclaimer in the
24// documentation and/or other materials provided with the distribution;
25// neither the name of the copyright holders nor the names of its
26// contributors may be used to endorse or promote products derived from
27// this software without specific prior written permission.
28//
29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40//
41// Authors: Stephen Hines
42//          Gabe Black
43
44////////////////////////////////////////////////////////////////////
45//
46// Load/store microops
47//
48
49def template MicroMemDeclare {{
50    class %(class_name)s : public %(base_class)s
51    {
52      public:
53        %(class_name)s(ExtMachInst machInst,
54                       RegIndex _ura, RegIndex _urb, bool _up,
55                       uint8_t _imm);
56        %(BasicExecDeclare)s
57        %(InitiateAccDeclare)s
58        %(CompleteAccDeclare)s
59    };
60}};
61
62def template MicroMemConstructor {{
63    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
64                                          RegIndex _ura,
65                                          RegIndex _urb,
66                                          bool _up,
67                                          uint8_t _imm)
68        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
69                         _ura, _urb, _up, _imm)
70    {
71        %(constructor)s;
72    }
73}};
74
75////////////////////////////////////////////////////////////////////
76//
77// Integer = Integer op Immediate microops
78//
79
80def template MicroIntDeclare {{
81    class %(class_name)s : public %(base_class)s
82    {
83      public:
84        %(class_name)s(ExtMachInst machInst,
85                       RegIndex _ura, RegIndex _urb,
86                       uint8_t _imm);
87        %(BasicExecDeclare)s
88    };
89}};
90
91def template MicroIntConstructor {{
92    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
93                                          RegIndex _ura,
94                                          RegIndex _urb,
95                                          uint8_t _imm)
96        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
97                         _ura, _urb, _imm)
98    {
99        %(constructor)s;
100    }
101}};
102
103////////////////////////////////////////////////////////////////////
104//
105// Macro Memory-format instructions
106//
107
108def template MacroMemDeclare {{
109/**
110 * Static instructions class for a store multiple instruction
111 */
112class %(class_name)s : public %(base_class)s
113{
114    public:
115        // Constructor
116        %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
117                bool index, bool up, bool user, bool writeback, bool load,
118                uint32_t reglist);
119        %(BasicExecPanic)s
120};
121}};
122
123def template MacroMemConstructor {{
124inline %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
125        bool index, bool up, bool user, bool writeback, bool load,
126        uint32_t reglist)
127    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
128{
129    %(constructor)s;
130    uint32_t regs = reglist;
131    uint32_t ones = number_of_ones(reglist);
132    // Remember that writeback adds a uop
133    numMicroops = ones + (writeback ? 1 : 0) + 1;
134    microOps = new StaticInstPtr[numMicroops];
135    uint32_t addr = 0;
136
137    if (!up)
138        addr = (ones << 2) - 4;
139
140    if (!index)
141        addr += 4;
142
143    // Add 0 to Rn and stick it in ureg0.
144    // This is equivalent to a move.
145    microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
146
147    unsigned reg = 0;
148    bool force_user = user & !bits(reglist, 15);
149    bool exception_ret = user & bits(reglist, 15);
150
151    for (int i = 1; i < ones + 1; i++) {
152        // Find the next register.
153        while (!bits(regs, reg))
154            reg++;
155        replaceBits(regs, reg, 0);
156
157        unsigned regIdx = reg;
158        if (force_user) {
159            regIdx = intRegForceUser(regIdx);
160        }
161
162        if (load) {
163            if (reg == INTREG_PC && exception_ret) {
164                // This must be the exception return form of ldm.
165                microOps[i] =
166                    new MicroLdrRetUop(machInst, regIdx,
167                                       INTREG_UREG0, up, addr);
168            } else {
169                microOps[i] =
170                    new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr);
171            }
172        } else {
173            microOps[i] =
174                new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr);
175        }
176
177        if (up)
178            addr += 4;
179        else
180            addr -= 4;
181    }
182
183    StaticInstPtr &lastUop = microOps[numMicroops - 1];
184    if (writeback) {
185        if (up) {
186            lastUop = new MicroAddiUop(machInst, rn, rn, ones * 4);
187        } else {
188            lastUop = new MicroSubiUop(machInst, rn, rn, ones * 4);
189        }
190    }
191    lastUop->setLastMicroop();
192}
193
194}};
195