macromem.isa revision 8140
110448Snilay@cs.wisc.edu// -*- mode:c++ -*- 210448Snilay@cs.wisc.edu 310448Snilay@cs.wisc.edu// Copyright (c) 2010 ARM Limited 410448Snilay@cs.wisc.edu// All rights reserved 510448Snilay@cs.wisc.edu// 610448Snilay@cs.wisc.edu// The license below extends only to copyright in the software and shall 710448Snilay@cs.wisc.edu// not be construed as granting a license to any other intellectual 810448Snilay@cs.wisc.edu// property including but not limited to intellectual property relating 910448Snilay@cs.wisc.edu// to a hardware implementation of the functionality of the software 1010448Snilay@cs.wisc.edu// licensed hereunder. You may use the software subject to the license 1110448Snilay@cs.wisc.edu// terms below provided that you ensure that this notice is replicated 1210448Snilay@cs.wisc.edu// unmodified and in its entirety in all distributions of the software, 1310448Snilay@cs.wisc.edu// modified or unmodified, in source code or in binary form. 1410448Snilay@cs.wisc.edu// 1510448Snilay@cs.wisc.edu// Copyright (c) 2007-2008 The Florida State University 1610448Snilay@cs.wisc.edu// All rights reserved. 1710448Snilay@cs.wisc.edu// 1810448Snilay@cs.wisc.edu// Redistribution and use in source and binary forms, with or without 1910448Snilay@cs.wisc.edu// modification, are permitted provided that the following conditions are 2010448Snilay@cs.wisc.edu// met: redistributions of source code must retain the above copyright 2110448Snilay@cs.wisc.edu// notice, this list of conditions and the following disclaimer; 2210447Snilay@cs.wisc.edu// redistributions in binary form must reproduce the above copyright 2310447Snilay@cs.wisc.edu// notice, this list of conditions and the following disclaimer in the 2410447Snilay@cs.wisc.edu// documentation and/or other materials provided with the distribution; 2510447Snilay@cs.wisc.edu// neither the name of the copyright holders nor the names of its 2610447Snilay@cs.wisc.edu// contributors may be used to endorse or promote products derived from 2710447Snilay@cs.wisc.edu// this software without specific prior written permission. 2810447Snilay@cs.wisc.edu// 2910447Snilay@cs.wisc.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010447Snilay@cs.wisc.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110447Snilay@cs.wisc.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210447Snilay@cs.wisc.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310447Snilay@cs.wisc.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410447Snilay@cs.wisc.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510447Snilay@cs.wisc.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610447Snilay@cs.wisc.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710447Snilay@cs.wisc.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810447Snilay@cs.wisc.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910447Snilay@cs.wisc.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010447Snilay@cs.wisc.edu// 4110447Snilay@cs.wisc.edu// Authors: Stephen Hines 4210447Snilay@cs.wisc.edu// Gabe Black 4310447Snilay@cs.wisc.edu 4410447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 4510447Snilay@cs.wisc.edu// 4610447Snilay@cs.wisc.edu// Load/store microops 4710447Snilay@cs.wisc.edu// 4810447Snilay@cs.wisc.edu 4910447Snilay@cs.wisc.edudef template MicroMemDeclare {{ 5010447Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 5110447Snilay@cs.wisc.edu { 5210447Snilay@cs.wisc.edu public: 5310447Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 5410447Snilay@cs.wisc.edu RegIndex _ura, RegIndex _urb, bool _up, 5510447Snilay@cs.wisc.edu uint8_t _imm); 5610447Snilay@cs.wisc.edu %(BasicExecDeclare)s 5710447Snilay@cs.wisc.edu %(InitiateAccDeclare)s 5810447Snilay@cs.wisc.edu %(CompleteAccDeclare)s 5910447Snilay@cs.wisc.edu }; 6010447Snilay@cs.wisc.edu}}; 6110447Snilay@cs.wisc.edu 6210447Snilay@cs.wisc.edudef template MicroMemConstructor {{ 6310447Snilay@cs.wisc.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 6410447Snilay@cs.wisc.edu RegIndex _ura, 6510447Snilay@cs.wisc.edu RegIndex _urb, 6610447Snilay@cs.wisc.edu bool _up, 6710447Snilay@cs.wisc.edu uint8_t _imm) 6810447Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 6910447Snilay@cs.wisc.edu _ura, _urb, _up, _imm) 7010447Snilay@cs.wisc.edu { 7110447Snilay@cs.wisc.edu %(constructor)s; 7210447Snilay@cs.wisc.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 7310447Snilay@cs.wisc.edu for (int x = 0; x < _numDestRegs; x++) { 7410447Snilay@cs.wisc.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 7510447Snilay@cs.wisc.edu } 7610447Snilay@cs.wisc.edu } 7710447Snilay@cs.wisc.edu } 7810447Snilay@cs.wisc.edu}}; 7910447Snilay@cs.wisc.edu 8010447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 8110447Snilay@cs.wisc.edu// 8210447Snilay@cs.wisc.edu// Neon load/store microops 8310447Snilay@cs.wisc.edu// 8410447Snilay@cs.wisc.edu 8510447Snilay@cs.wisc.edudef template MicroNeonMemDeclare {{ 8610447Snilay@cs.wisc.edu template <class Element> 8710447Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 8810447Snilay@cs.wisc.edu { 8910447Snilay@cs.wisc.edu public: 9010447Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, RegIndex _dest, 9110447Snilay@cs.wisc.edu RegIndex _ura, uint32_t _imm, unsigned extraMemFlags) 9210447Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, 9310447Snilay@cs.wisc.edu %(op_class)s, _dest, _ura, _imm) 9410447Snilay@cs.wisc.edu { 9510447Snilay@cs.wisc.edu memAccessFlags |= extraMemFlags; 9610447Snilay@cs.wisc.edu %(constructor)s; 9710447Snilay@cs.wisc.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 9810447Snilay@cs.wisc.edu for (int x = 0; x < _numDestRegs; x++) { 9910447Snilay@cs.wisc.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10010447Snilay@cs.wisc.edu } 10110447Snilay@cs.wisc.edu } 10210447Snilay@cs.wisc.edu } 10310447Snilay@cs.wisc.edu 10410447Snilay@cs.wisc.edu %(BasicExecDeclare)s 10510447Snilay@cs.wisc.edu %(InitiateAccDeclare)s 10610447Snilay@cs.wisc.edu %(CompleteAccDeclare)s 10710447Snilay@cs.wisc.edu }; 10810447Snilay@cs.wisc.edu}}; 10910447Snilay@cs.wisc.edu 11010447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 11110447Snilay@cs.wisc.edu// 11210447Snilay@cs.wisc.edu// PC = Integer(ura) 11310447Snilay@cs.wisc.edu// CPSR = Integer(urb) 11410447Snilay@cs.wisc.edu// 11510447Snilay@cs.wisc.edu 11610447Snilay@cs.wisc.edudef template MicroSetPCCPSRDeclare {{ 11710447Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 11810447Snilay@cs.wisc.edu { 11910447Snilay@cs.wisc.edu public: 12010447Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 12110447Snilay@cs.wisc.edu IntRegIndex _ura, 12210447Snilay@cs.wisc.edu IntRegIndex _urb, 12310447Snilay@cs.wisc.edu IntRegIndex _urc); 12410447Snilay@cs.wisc.edu %(BasicExecDeclare)s 12510447Snilay@cs.wisc.edu }; 12610447Snilay@cs.wisc.edu}}; 12710447Snilay@cs.wisc.edu 12810447Snilay@cs.wisc.edudef template MicroSetPCCPSRConstructor {{ 12910447Snilay@cs.wisc.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 13010447Snilay@cs.wisc.edu IntRegIndex _ura, 13110447Snilay@cs.wisc.edu IntRegIndex _urb, 13210447Snilay@cs.wisc.edu IntRegIndex _urc) 13310447Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 13410447Snilay@cs.wisc.edu _ura, _urb, _urc) 13510447Snilay@cs.wisc.edu { 13610447Snilay@cs.wisc.edu %(constructor)s; 13710447Snilay@cs.wisc.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 13810447Snilay@cs.wisc.edu for (int x = 0; x < _numDestRegs; x++) { 13910447Snilay@cs.wisc.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 14010447Snilay@cs.wisc.edu } 14110447Snilay@cs.wisc.edu } 14210447Snilay@cs.wisc.edu } 14310447Snilay@cs.wisc.edu}}; 14410447Snilay@cs.wisc.edu 14510447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 14610447Snilay@cs.wisc.edu// 14710447Snilay@cs.wisc.edu// Integer = Integer op Integer microops 14810447Snilay@cs.wisc.edu// 14910447Snilay@cs.wisc.edu 15010447Snilay@cs.wisc.edudef template MicroIntDeclare {{ 15110447Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 15210447Snilay@cs.wisc.edu { 15310447Snilay@cs.wisc.edu public: 15410447Snilay@cs.wisc.edu %(class_name)s(ExtMachInst machInst, 15510447Snilay@cs.wisc.edu RegIndex _ura, RegIndex _urb, RegIndex _urc); 15610447Snilay@cs.wisc.edu %(BasicExecDeclare)s 15710447Snilay@cs.wisc.edu }; 15810447Snilay@cs.wisc.edu}}; 15910447Snilay@cs.wisc.edu 16010447Snilay@cs.wisc.edudef template MicroIntConstructor {{ 16110447Snilay@cs.wisc.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 16210447Snilay@cs.wisc.edu RegIndex _ura, 16310447Snilay@cs.wisc.edu RegIndex _urb, 16410447Snilay@cs.wisc.edu RegIndex _urc) 16510447Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 16610447Snilay@cs.wisc.edu _ura, _urb, _urc) 16710447Snilay@cs.wisc.edu { 16810447Snilay@cs.wisc.edu %(constructor)s; 16910447Snilay@cs.wisc.edu if (!(condCode == COND_AL || condCode == COND_UC)) { 17010447Snilay@cs.wisc.edu for (int x = 0; x < _numDestRegs; x++) { 17110447Snilay@cs.wisc.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 17210447Snilay@cs.wisc.edu } 17310447Snilay@cs.wisc.edu } 17410447Snilay@cs.wisc.edu } 17510447Snilay@cs.wisc.edu}}; 17610447Snilay@cs.wisc.edu 17710447Snilay@cs.wisc.edudef template MicroNeonMemExecDeclare {{ 17810447Snilay@cs.wisc.edu template 17910447Snilay@cs.wisc.edu Fault %(class_name)s<%(targs)s>::execute( 18010447Snilay@cs.wisc.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 18110447Snilay@cs.wisc.edu template 18210447Snilay@cs.wisc.edu Fault %(class_name)s<%(targs)s>::initiateAcc( 18310447Snilay@cs.wisc.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 18410447Snilay@cs.wisc.edu template 18510447Snilay@cs.wisc.edu Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr, 18610447Snilay@cs.wisc.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 18710447Snilay@cs.wisc.edu}}; 18810447Snilay@cs.wisc.edu 18910447Snilay@cs.wisc.edudef template MicroNeonExecDeclare {{ 19010447Snilay@cs.wisc.edu template 19110447Snilay@cs.wisc.edu Fault %(class_name)s<%(targs)s>::execute( 19210447Snilay@cs.wisc.edu %(CPU_exec_context)s *, Trace::InstRecord *) const; 19310447Snilay@cs.wisc.edu}}; 19410447Snilay@cs.wisc.edu 19510447Snilay@cs.wisc.edu//////////////////////////////////////////////////////////////////// 19610447Snilay@cs.wisc.edu// 19710447Snilay@cs.wisc.edu// Neon (de)interlacing microops 19810447Snilay@cs.wisc.edu// 19910447Snilay@cs.wisc.edu 20010447Snilay@cs.wisc.edudef template MicroNeonMixDeclare {{ 20110447Snilay@cs.wisc.edu template <class Element> 202 class %(class_name)s : public %(base_class)s 203 { 204 public: 205 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 206 uint8_t _step) : 207 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 208 _dest, _op1, _step) 209 { 210 %(constructor)s; 211 if (!(condCode == COND_AL || condCode == COND_UC)) { 212 for (int x = 0; x < _numDestRegs; x++) { 213 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 214 } 215 } 216 } 217 218 %(BasicExecDeclare)s 219 }; 220}}; 221 222def template MicroNeonMixExecute {{ 223 template <class Element> 224 Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc, 225 Trace::InstRecord *traceData) const 226 { 227 Fault fault = NoFault; 228 uint64_t resTemp = 0; 229 resTemp = resTemp; 230 %(op_decl)s; 231 %(op_rd)s; 232 233 if (%(predicate_test)s) 234 { 235 %(code)s; 236 if (fault == NoFault) 237 { 238 %(op_wb)s; 239 } 240 } else { 241 xc->setPredicate(false); 242 } 243 244 if (fault == NoFault && machInst.itstateMask != 0) { 245 xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); 246 } 247 248 return fault; 249 } 250}}; 251 252//////////////////////////////////////////////////////////////////// 253// 254// Neon (un)packing microops using a particular lane 255// 256 257def template MicroNeonMixLaneDeclare {{ 258 template <class Element> 259 class %(class_name)s : public %(base_class)s 260 { 261 public: 262 %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1, 263 uint8_t _step, unsigned _lane) : 264 %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 265 _dest, _op1, _step, _lane) 266 { 267 %(constructor)s; 268 if (!(condCode == COND_AL || condCode == COND_UC)) { 269 for (int x = 0; x < _numDestRegs; x++) { 270 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 271 } 272 } 273 } 274 275 %(BasicExecDeclare)s 276 }; 277}}; 278 279//////////////////////////////////////////////////////////////////// 280// 281// Integer = Integer 282// 283 284def template MicroIntMovDeclare {{ 285 class %(class_name)s : public %(base_class)s 286 { 287 public: 288 %(class_name)s(ExtMachInst machInst, 289 RegIndex _ura, RegIndex _urb); 290 %(BasicExecDeclare)s 291 }; 292}}; 293def template MicroIntMovConstructor {{ 294 %(class_name)s::%(class_name)s(ExtMachInst machInst, 295 RegIndex _ura, 296 RegIndex _urb) 297 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 298 _ura, _urb) 299 { 300 %(constructor)s; 301 if (!(condCode == COND_AL || condCode == COND_UC)) { 302 for (int x = 0; x < _numDestRegs; x++) { 303 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 304 } 305 } 306 } 307}}; 308 309//////////////////////////////////////////////////////////////////// 310// 311// Integer = Integer op Immediate microops 312// 313 314def template MicroIntImmDeclare {{ 315 class %(class_name)s : public %(base_class)s 316 { 317 public: 318 %(class_name)s(ExtMachInst machInst, 319 RegIndex _ura, RegIndex _urb, 320 int32_t _imm); 321 %(BasicExecDeclare)s 322 }; 323}}; 324 325def template MicroIntImmConstructor {{ 326 %(class_name)s::%(class_name)s(ExtMachInst machInst, 327 RegIndex _ura, 328 RegIndex _urb, 329 int32_t _imm) 330 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 331 _ura, _urb, _imm) 332 { 333 %(constructor)s; 334 if (!(condCode == COND_AL || condCode == COND_UC)) { 335 for (int x = 0; x < _numDestRegs; x++) { 336 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 337 } 338 } 339 } 340}}; 341 342def template MicroIntRegDeclare {{ 343 class %(class_name)s : public %(base_class)s 344 { 345 public: 346 %(class_name)s(ExtMachInst machInst, 347 RegIndex _ura, RegIndex _urb, RegIndex _urc, 348 int32_t _shiftAmt, ArmShiftType _shiftType); 349 %(BasicExecDeclare)s 350 }; 351}}; 352 353def template MicroIntRegConstructor {{ 354 %(class_name)s::%(class_name)s(ExtMachInst machInst, 355 RegIndex _ura, RegIndex _urb, RegIndex _urc, 356 int32_t _shiftAmt, ArmShiftType _shiftType) 357 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 358 _ura, _urb, _urc, _shiftAmt, _shiftType) 359 { 360 %(constructor)s; 361 if (!(condCode == COND_AL || condCode == COND_UC)) { 362 for (int x = 0; x < _numDestRegs; x++) { 363 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 364 } 365 } 366 } 367}}; 368 369//////////////////////////////////////////////////////////////////// 370// 371// Macro Memory-format instructions 372// 373 374def template MacroMemDeclare {{ 375/** 376 * Static instructions class for a store multiple instruction 377 */ 378class %(class_name)s : public %(base_class)s 379{ 380 public: 381 // Constructor 382 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 383 bool index, bool up, bool user, bool writeback, bool load, 384 uint32_t reglist); 385 %(BasicExecPanic)s 386}; 387}}; 388 389def template MacroMemConstructor {{ 390%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 391 bool index, bool up, bool user, bool writeback, bool load, 392 uint32_t reglist) 393 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 394 index, up, user, writeback, load, reglist) 395{ 396 %(constructor)s; 397 if (!(condCode == COND_AL || condCode == COND_UC)) { 398 for (int x = 0; x < _numDestRegs; x++) { 399 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 400 } 401 } 402} 403 404}}; 405 406def template VMemMultDeclare {{ 407class %(class_name)s : public %(base_class)s 408{ 409 public: 410 // Constructor 411 %(class_name)s(ExtMachInst machInst, unsigned width, 412 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 413 uint32_t size, uint32_t align, RegIndex rm); 414 %(BasicExecPanic)s 415}; 416}}; 417 418def template VMemMultConstructor {{ 419%(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width, 420 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 421 uint32_t size, uint32_t align, RegIndex rm) 422 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width, 423 rn, vd, regs, inc, size, align, rm) 424{ 425 %(constructor)s; 426 if (!(condCode == COND_AL || condCode == COND_UC)) { 427 for (int x = 0; x < _numDestRegs; x++) { 428 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 429 } 430 } 431} 432}}; 433 434def template VMemSingleDeclare {{ 435class %(class_name)s : public %(base_class)s 436{ 437 public: 438 // Constructor 439 %(class_name)s(ExtMachInst machInst, bool all, unsigned width, 440 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 441 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); 442 %(BasicExecPanic)s 443}; 444}}; 445 446def template VMemSingleConstructor {{ 447%(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width, 448 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, 449 uint32_t size, uint32_t align, RegIndex rm, unsigned lane) 450 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width, 451 rn, vd, regs, inc, size, align, rm, lane) 452{ 453 %(constructor)s; 454 if (!(condCode == COND_AL || condCode == COND_UC)) { 455 for (int x = 0; x < _numDestRegs; x++) { 456 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 457 } 458 } 459} 460}}; 461 462def template MacroVFPMemDeclare {{ 463/** 464 * Static instructions class for a store multiple instruction 465 */ 466class %(class_name)s : public %(base_class)s 467{ 468 public: 469 // Constructor 470 %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 471 RegIndex vd, bool single, bool up, bool writeback, 472 bool load, uint32_t offset); 473 %(BasicExecPanic)s 474}; 475}}; 476 477def template MacroVFPMemConstructor {{ 478%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 479 RegIndex vd, bool single, bool up, bool writeback, bool load, 480 uint32_t offset) 481 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn, 482 vd, single, up, writeback, load, offset) 483{ 484 %(constructor)s; 485 if (!(condCode == COND_AL || condCode == COND_UC)) { 486 for (int x = 0; x < _numDestRegs; x++) { 487 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 488 } 489 } 490} 491 492}}; 493