macromem.isa revision 7169
16019SN/A// -*- mode:c++ -*- 26019SN/A 37134Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 496309SN/Adef template MicroMemDeclare {{ 506309SN/A class %(class_name)s : public %(base_class)s 516309SN/A { 526309SN/A public: 536309SN/A %(class_name)s(ExtMachInst machInst, 547134Sgblack@eecs.umich.edu RegIndex _ura, RegIndex _urb, bool _up, 556309SN/A uint8_t _imm); 566309SN/A %(BasicExecDeclare)s 576309SN/A %(InitiateAccDeclare)s 586309SN/A %(CompleteAccDeclare)s 596309SN/A }; 606309SN/A}}; 616309SN/A 627134Sgblack@eecs.umich.edudef template MicroMemConstructor {{ 637134Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 647134Sgblack@eecs.umich.edu RegIndex _ura, 657134Sgblack@eecs.umich.edu RegIndex _urb, 667134Sgblack@eecs.umich.edu bool _up, 677134Sgblack@eecs.umich.edu uint8_t _imm) 687134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 697134Sgblack@eecs.umich.edu _ura, _urb, _up, _imm) 707134Sgblack@eecs.umich.edu { 717134Sgblack@eecs.umich.edu %(constructor)s; 727134Sgblack@eecs.umich.edu } 736309SN/A}}; 746308SN/A 756308SN/A//////////////////////////////////////////////////////////////////// 766308SN/A// 776308SN/A// Integer = Integer op Immediate microops 786308SN/A// 796308SN/A 806308SN/Adef template MicroIntDeclare {{ 816308SN/A class %(class_name)s : public %(base_class)s 826308SN/A { 836308SN/A public: 846308SN/A %(class_name)s(ExtMachInst machInst, 856308SN/A RegIndex _ura, RegIndex _urb, 866308SN/A uint8_t _imm); 876308SN/A %(BasicExecDeclare)s 886308SN/A }; 896308SN/A}}; 906308SN/A 917134Sgblack@eecs.umich.edudef template MicroIntConstructor {{ 927134Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 937134Sgblack@eecs.umich.edu RegIndex _ura, 947134Sgblack@eecs.umich.edu RegIndex _urb, 957134Sgblack@eecs.umich.edu uint8_t _imm) 967134Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 977134Sgblack@eecs.umich.edu _ura, _urb, _imm) 987134Sgblack@eecs.umich.edu { 997134Sgblack@eecs.umich.edu %(constructor)s; 1007134Sgblack@eecs.umich.edu } 1016308SN/A}}; 1026019SN/A 1036019SN/A//////////////////////////////////////////////////////////////////// 1046019SN/A// 1056019SN/A// Macro Memory-format instructions 1066019SN/A// 1076019SN/A 1087134Sgblack@eecs.umich.edudef template MacroMemDeclare {{ 1096253SN/A/** 1106253SN/A * Static instructions class for a store multiple instruction 1116253SN/A */ 1126253SN/Aclass %(class_name)s : public %(base_class)s 1136253SN/A{ 1146253SN/A public: 1156253SN/A // Constructor 1167134Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex rn, 1177134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 1187134Sgblack@eecs.umich.edu uint32_t reglist); 1197169Sgblack@eecs.umich.edu %(BasicExecPanic)s 1206253SN/A}; 1216019SN/A}}; 1226019SN/A 1237134Sgblack@eecs.umich.edudef template MacroMemConstructor {{ 1247134Sgblack@eecs.umich.eduinline %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn, 1257134Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, bool load, 1267134Sgblack@eecs.umich.edu uint32_t reglist) 1276253SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1286253SN/A{ 1296253SN/A %(constructor)s; 1306725SN/A uint32_t regs = reglist; 1317134Sgblack@eecs.umich.edu uint32_t ones = number_of_ones(reglist); 1327134Sgblack@eecs.umich.edu // Remember that writeback adds a uop 1337134Sgblack@eecs.umich.edu numMicroops = ones + (writeback ? 1 : 0) + 1; 1347134Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1356725SN/A uint32_t addr = 0; 1366253SN/A 1376725SN/A if (!up) 1386725SN/A addr = (ones << 2) - 4; 1396725SN/A 1407134Sgblack@eecs.umich.edu if (!index) 1416725SN/A addr += 4; 1426019SN/A 1436717SN/A // Add 0 to Rn and stick it in ureg0. 1446308SN/A // This is equivalent to a move. 1457134Sgblack@eecs.umich.edu microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0); 1466253SN/A 1476725SN/A unsigned reg = 0; 1487134Sgblack@eecs.umich.edu bool force_user = user & !bits(reglist, 15); 1497134Sgblack@eecs.umich.edu bool exception_ret = user & bits(reglist, 15); 1506758SN/A 1516725SN/A for (int i = 1; i < ones + 1; i++) { 1526725SN/A // Find the next register. 1536725SN/A while (!bits(regs, reg)) 1546725SN/A reg++; 1556725SN/A replaceBits(regs, reg, 0); 1566253SN/A 1576726SN/A unsigned regIdx = reg; 1586758SN/A if (force_user) { 1596726SN/A regIdx = intRegForceUser(regIdx); 1606726SN/A } 1616726SN/A 1627134Sgblack@eecs.umich.edu if (load) { 1636758SN/A if (reg == INTREG_PC && exception_ret) { 1646755SN/A // This must be the exception return form of ldm. 1656755SN/A microOps[i] = 1667134Sgblack@eecs.umich.edu new MicroLdrRetUop(machInst, regIdx, 1677134Sgblack@eecs.umich.edu INTREG_UREG0, up, addr); 1686755SN/A } else { 1696755SN/A microOps[i] = 1707134Sgblack@eecs.umich.edu new MicroLdrUop(machInst, regIdx, INTREG_UREG0, up, addr); 1716755SN/A } 1726726SN/A } else { 1736726SN/A microOps[i] = 1747134Sgblack@eecs.umich.edu new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr); 1756726SN/A } 1766253SN/A 1776253SN/A if (up) 1786725SN/A addr += 4; 1796253SN/A else 1806725SN/A addr -= 4; 1816253SN/A } 1826253SN/A 1836725SN/A StaticInstPtr &lastUop = microOps[numMicroops - 1]; 1847134Sgblack@eecs.umich.edu if (writeback) { 1856308SN/A if (up) { 1867134Sgblack@eecs.umich.edu lastUop = new MicroAddiUop(machInst, rn, rn, ones * 4); 1876308SN/A } else { 1887134Sgblack@eecs.umich.edu lastUop = new MicroSubiUop(machInst, rn, rn, ones * 4); 1896019SN/A } 1906019SN/A } 1916725SN/A lastUop->setLastMicroop(); 1926253SN/A} 1936019SN/A 1946019SN/A}}; 195