macromem.isa revision 6717 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30//          Gabe Black
31
32////////////////////////////////////////////////////////////////////
33//
34// Common microop templates
35//
36
37def template MicroConstructor {{
38    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
39                                          RegIndex _ura,
40                                          RegIndex _urb,
41                                          uint8_t _imm)
42        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
43                         _ura, _urb, _imm)
44    {
45        %(constructor)s;
46    }
47}};
48
49////////////////////////////////////////////////////////////////////
50//
51// Load/store microops
52//
53
54def template MicroMemDeclare {{
55    class %(class_name)s : public %(base_class)s
56    {
57      public:
58        %(class_name)s(ExtMachInst machInst,
59                       RegIndex _ura, RegIndex _urb,
60                       uint8_t _imm);
61        %(BasicExecDeclare)s
62        %(InitiateAccDeclare)s
63        %(CompleteAccDeclare)s
64    };
65}};
66
67let {{
68    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
69                                   'MicroMemOp',
70                                   {'memacc_code': 'Ra = Mem;',
71                                    'ea_code': 'EA = Rb + (UP ? imm : -imm);',
72                                    'predicate_test': predicateTest},
73                                   ['IsMicroop'])
74
75    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
76                                   'MicroMemOp',
77                                   {'memacc_code': 'Mem = Ra;',
78                                    'ea_code': 'EA = Rb + (UP ? imm : -imm);',
79                                    'predicate_test': predicateTest},
80                                   ['IsMicroop'])
81
82    header_output = MicroMemDeclare.subst(microLdrUopIop) + \
83                    MicroMemDeclare.subst(microStrUopIop)
84    decoder_output = MicroConstructor.subst(microLdrUopIop) + \
85                     MicroConstructor.subst(microStrUopIop)
86    exec_output = LoadExecute.subst(microLdrUopIop) + \
87                  StoreExecute.subst(microStrUopIop) + \
88                  LoadInitiateAcc.subst(microLdrUopIop) + \
89                  StoreInitiateAcc.subst(microStrUopIop) + \
90                  LoadCompleteAcc.subst(microLdrUopIop) + \
91                  StoreCompleteAcc.subst(microStrUopIop)
92}};
93
94////////////////////////////////////////////////////////////////////
95//
96// Integer = Integer op Immediate microops
97//
98
99def template MicroIntDeclare {{
100    class %(class_name)s : public %(base_class)s
101    {
102      public:
103        %(class_name)s(ExtMachInst machInst,
104                       RegIndex _ura, RegIndex _urb,
105                       uint8_t _imm);
106        %(BasicExecDeclare)s
107    };
108}};
109
110let {{
111    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
112                                    'MicroIntOp',
113                                    {'code': 'Ra = Rb + imm;',
114                                     'predicate_test': predicateTest},
115                                    ['IsMicroop'])
116
117    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
118                                    'MicroIntOp',
119                                    {'code': 'Ra = Rb - imm;',
120                                     'predicate_test': predicateTest},
121                                    ['IsMicroop'])
122
123    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
124                    MicroIntDeclare.subst(microSubiUopIop)
125    decoder_output = MicroConstructor.subst(microAddiUopIop) + \
126                     MicroConstructor.subst(microSubiUopIop)
127    exec_output = PredOpExecute.subst(microAddiUopIop) + \
128                  PredOpExecute.subst(microSubiUopIop)
129}};
130
131////////////////////////////////////////////////////////////////////
132//
133// Moving to/from double floating point registers
134//
135
136let {{
137    microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop',
138                                    'PredOp',
139                                    {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;',
140                                     'predicate_test': predicateTest},
141                                    ['IsMicroop'])
142
143    microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop',
144                                    'PredOp',
145                                    {'code': '''Rhi = bits(Fd.ud, 63, 32);
146                                                Rlo = bits(Fd.ud, 31, 0);''',
147                                     'predicate_test': predicateTest},
148                                    ['IsMicroop'])
149
150    header_output = BasicDeclare.subst(microMvtdUopIop) + \
151                    BasicDeclare.subst(microMvfdUopIop)
152    decoder_output = BasicConstructor.subst(microMvtdUopIop) + \
153                     BasicConstructor.subst(microMvfdUopIop)
154    exec_output = PredOpExecute.subst(microMvtdUopIop) + \
155                  PredOpExecute.subst(microMvfdUopIop)
156}};
157
158////////////////////////////////////////////////////////////////////
159//
160// Macro Memory-format instructions
161//
162
163def template MacroStoreDeclare {{
164/**
165 * Static instructions class for a store multiple instruction
166 */
167class %(class_name)s : public %(base_class)s
168{
169    public:
170        // Constructor
171        %(class_name)s(ExtMachInst machInst);
172        %(BasicExecDeclare)s
173};
174}};
175
176def template MacroStoreConstructor {{
177inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
178    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
179{
180    %(constructor)s;
181    uint32_t regs_to_handle = reglist;
182    uint32_t start_addr = 0;
183
184    switch (puswl)
185    {
186        case 0x00: //       stmda
187        case 0x01: //     L ldmda_l
188        case 0x02: //    W  stmda_w
189        case 0x03: //    WL ldmda_wl
190            start_addr = (ones << 2) - 4;
191            break;
192        case 0x08: //  U    stmia_u
193        case 0x09: //  U  L ldmia_ul
194        case 0x0a: //  U W  stmia
195        case 0x0b: //  U WL ldmia
196            start_addr = 0;
197            break;
198        case 0x10: // P     stmdb
199        case 0x11: // P   L ldmdb
200        case 0x12: // P  W  stmdb
201        case 0x13: // P  WL ldmdb
202            start_addr = (ones << 2); // U-bit is already 0 for subtract
203            break;
204        case 0x18: // PU    stmib
205        case 0x19: // PU  L ldmib
206        case 0x1a: // PU W  stmib
207        case 0x1b: // PU WL ldmib
208            start_addr = 4;
209            break;
210        default:
211            panic("Unhandled Load/Store Multiple Instruction, "
212                "puswl = 0x%x", (unsigned) puswl);
213            break;
214    }
215
216    // Add 0 to Rn and stick it in ureg0.
217    // This is equivalent to a move.
218    microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
219
220    unsigned j = 0;
221    for (int i = 1; i < ones+1; i++) {
222        // Get next available bit for transfer
223        while (! ( regs_to_handle & (1<<j)))
224            j++;
225        regs_to_handle &= ~(1<<j);
226
227        if (loadop)
228            microOps[i] = new MicroLdrUop(machInst, j,
229                    INTREG_UREG0, start_addr);
230        else
231            microOps[i] = new MicroStrUop(machInst, j,
232                    INTREG_UREG0, start_addr);
233
234        if (up)
235            start_addr += 4;
236        else
237            start_addr -= 4;
238    }
239
240    if (writeback) {
241        if (up) {
242            microOps[numMicroops-1] =
243                new MicroAddiUop(machInst, RN, RN, ones * 4);
244        } else {
245            microOps[numMicroops-1] =
246                new MicroSubiUop(machInst, RN, RN, ones * 4);
247        }
248    }
249    microOps[numMicroops-1]->setLastMicroop();
250}
251
252}};
253
254def template MacroStoreExecute {{
255Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
256{
257    Fault fault = NoFault;
258
259    %(fp_enable_check)s;
260    %(op_decl)s;
261    %(op_rd)s;
262    %(code)s;
263    if (fault == NoFault)
264    {
265        %(op_wb)s;
266    }
267
268    return fault;
269}
270}};
271
272def template MacroFPAConstructor {{
273inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
274    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
275{
276    %(constructor)s;
277
278    uint32_t start_addr = 0;
279
280    if (prepost)
281        start_addr = disp8;
282    else
283        start_addr = 0;
284
285    emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
286
287    if (writeback)
288    {
289        if (up) {
290            microOps[numMicroops-1] =
291                new MicroAddiUop(machInst, RN, RN, disp8);
292        } else {
293            microOps[numMicroops-1] =
294                new MicroSubiUop(machInst, RN, RN, disp8);
295        }
296    }
297    microOps[numMicroops-1]->setLastMicroop();
298}
299
300}};
301
302
303def template MacroFMConstructor {{
304inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
305    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
306{
307    %(constructor)s;
308
309    uint32_t start_addr = 0;
310
311    if (prepost)
312        start_addr = disp8;
313    else
314        start_addr = 0;
315
316    for (int i = 0; i < count; i++)
317        emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
318
319    if (writeback) {
320        if (up) {
321            microOps[numMicroops-1] =
322                new MicroAddiUop(machInst, RN, RN, disp8);
323        } else {
324            microOps[numMicroops-1] =
325                new MicroSubiUop(machInst, RN, RN, disp8);
326        }
327    }
328    microOps[numMicroops-1]->setLastMicroop();
329}
330}};
331
332
333def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
334    iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
335    header_output = MacroStoreDeclare.subst(iop)
336    decoder_output = MacroStoreConstructor.subst(iop)
337    decode_block = BasicDecode.subst(iop)
338    exec_output = MacroStoreExecute.subst(iop)
339}};
340
341def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
342    iop = InstObjParams(name, Name, 'ArmMacroFPAOp',
343                        {"code": code,
344                         "predicate_test": predicateTest},
345                        opt_flags)
346    header_output = BasicDeclare.subst(iop)
347    decoder_output = MacroFPAConstructor.subst(iop)
348    decode_block = BasicDecode.subst(iop)
349    exec_output = PredOpExecute.subst(iop)
350}};
351
352def format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
353    iop = InstObjParams(name, Name, 'ArmMacroFMOp',
354                        {"code": code,
355                         "predicate_test": predicateTest},
356                        opt_flags)
357    header_output = BasicDeclare.subst(iop)
358    decoder_output = MacroFMConstructor.subst(iop)
359    decode_block = BasicDecode.subst(iop)
360    exec_output = PredOpExecute.subst(iop)
361}};
362