branch.isa revision 9552:460cf901acba
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template BranchImmDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43    public:
44        // Constructor
45        %(class_name)s(ExtMachInst machInst, int32_t _imm);
46        %(BasicExecDeclare)s
47};
48}};
49
50def template BranchImmConstructor {{
51    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
52                                          int32_t _imm)
53        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
54    {
55        %(constructor)s;
56        if (!(condCode == COND_AL || condCode == COND_UC)) {
57            for (int x = 0; x < _numDestRegs; x++) {
58                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
59            }
60            flags[IsCondControl] = true;
61        } else {
62            flags[IsUncondControl] = true;
63        }
64
65    }
66}};
67
68def template BranchImmCondDeclare {{
69class %(class_name)s : public %(base_class)s
70{
71    public:
72        // Constructor
73        %(class_name)s(ExtMachInst machInst, int32_t _imm,
74                       ConditionCode _condCode);
75        %(BasicExecDeclare)s
76        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
77
78        /// Explicitly import the otherwise hidden branchTarget
79        using StaticInst::branchTarget;
80};
81}};
82
83def template BranchImmCondConstructor {{
84    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
85                                          int32_t _imm,
86                                          ConditionCode _condCode)
87        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
88                         _imm, _condCode)
89    {
90        %(constructor)s;
91        if (!(condCode == COND_AL || condCode == COND_UC)) {
92            for (int x = 0; x < _numDestRegs; x++) {
93                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
94            }
95            flags[IsCondControl] = true;
96        } else {
97            flags[IsUncondControl] = true;
98        }
99    }
100}};
101
102def template BranchRegDeclare {{
103class %(class_name)s : public %(base_class)s
104{
105    public:
106        // Constructor
107        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
108        %(BasicExecDeclare)s
109};
110}};
111
112def template BranchRegConstructor {{
113    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
114                                          IntRegIndex _op1)
115        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
116    {
117        %(constructor)s;
118        if (!(condCode == COND_AL || condCode == COND_UC)) {
119            for (int x = 0; x < _numDestRegs; x++) {
120                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
121            }
122            flags[IsCondControl] = true;
123        } else {
124            flags[IsUncondControl] = true;
125        }
126        if (%(is_ras_pop)s)
127            flags[IsReturn] = true;
128    }
129}};
130
131def template BranchRegCondDeclare {{
132class %(class_name)s : public %(base_class)s
133{
134    public:
135        // Constructor
136        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
137                       ConditionCode _condCode);
138        %(BasicExecDeclare)s
139};
140}};
141
142def template BranchRegCondConstructor {{
143    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
144                                          IntRegIndex _op1,
145                                          ConditionCode _condCode)
146        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
147                         _op1, _condCode)
148    {
149        %(constructor)s;
150        if (!(condCode == COND_AL || condCode == COND_UC)) {
151            for (int x = 0; x < _numDestRegs; x++) {
152                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
153            }
154            flags[IsCondControl] = true;
155        } else {
156            flags[IsUncondControl] = true;
157        }
158        if (%(is_ras_pop)s)
159            flags[IsReturn] = true;
160    }
161}};
162
163def template BranchRegRegDeclare {{
164class %(class_name)s : public %(base_class)s
165{
166    public:
167        // Constructor
168        %(class_name)s(ExtMachInst machInst,
169                       IntRegIndex _op1, IntRegIndex _op2);
170        %(BasicExecDeclare)s
171};
172}};
173
174def template BranchTableDeclare {{
175class %(class_name)s : public %(base_class)s
176{
177    public:
178        // Constructor
179        %(class_name)s(ExtMachInst machInst,
180                       IntRegIndex _op1, IntRegIndex _op2);
181        %(BasicExecDeclare)s
182
183        %(InitiateAccDeclare)s
184
185        %(CompleteAccDeclare)s
186};
187}};
188
189def template BranchRegRegConstructor {{
190    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
191                                          IntRegIndex _op1,
192                                          IntRegIndex _op2)
193        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
194    {
195        %(constructor)s;
196        if (!(condCode == COND_AL || condCode == COND_UC)) {
197            for (int x = 0; x < _numDestRegs; x++) {
198                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
199            }
200            flags[IsCondControl] = true;
201        } else {
202            flags[IsUncondControl] = true;
203        }
204    }
205}};
206
207def template BranchImmRegDeclare {{
208class %(class_name)s : public %(base_class)s
209{
210    public:
211        // Constructor
212        %(class_name)s(ExtMachInst machInst,
213                       int32_t imm, IntRegIndex _op1);
214        %(BasicExecDeclare)s
215};
216}};
217
218// Only used by CBNZ, CBZ which is conditional based on
219// a register value even though the instruction is always unconditional.
220def template BranchImmRegConstructor {{
221    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
222                                          int32_t _imm,
223                                          IntRegIndex _op1)
224        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
225    {
226        %(constructor)s;
227        flags[IsCondControl] = true;
228    }
229}};
230
231def template BranchTarget {{
232
233    ArmISA::PCState
234    %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
235    {
236        %(op_decl)s;
237        %(op_rd)s;
238
239        ArmISA::PCState pcs = branchPC;
240        %(brTgtCode)s
241        pcs.advance();
242        return pcs;
243    }
244}};
245
246
247