branch.isa revision 8146:18368caa8489
16899SN/A// -*- mode:c++ -*- 29542Sandreas.hansson@arm.com 38851Sandreas.hansson@arm.com// Copyright (c) 2010 ARM Limited 48851Sandreas.hansson@arm.com// All rights reserved 58851Sandreas.hansson@arm.com// 68851Sandreas.hansson@arm.com// The license below extends only to copyright in the software and shall 78851Sandreas.hansson@arm.com// not be construed as granting a license to any other intellectual 88851Sandreas.hansson@arm.com// property including but not limited to intellectual property relating 98851Sandreas.hansson@arm.com// to a hardware implementation of the functionality of the software 108851Sandreas.hansson@arm.com// licensed hereunder. You may use the software subject to the license 118851Sandreas.hansson@arm.com// terms below provided that you ensure that this notice is replicated 128851Sandreas.hansson@arm.com// unmodified and in its entirety in all distributions of the software, 138851Sandreas.hansson@arm.com// modified or unmodified, in source code or in binary form. 146899SN/A// 156899SN/A// Redistribution and use in source and binary forms, with or without 166899SN/A// modification, are permitted provided that the following conditions are 176899SN/A// met: redistributions of source code must retain the above copyright 186899SN/A// notice, this list of conditions and the following disclaimer; 196899SN/A// redistributions in binary form must reproduce the above copyright 206899SN/A// notice, this list of conditions and the following disclaimer in the 216899SN/A// documentation and/or other materials provided with the distribution; 226899SN/A// neither the name of the copyright holders nor the names of its 236899SN/A// contributors may be used to endorse or promote products derived from 246899SN/A// this software without specific prior written permission. 256899SN/A// 266899SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 276899SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 286899SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 296899SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 306899SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 316899SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 326899SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 336899SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 346899SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 356899SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 366899SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376899SN/A// 386899SN/A// Authors: Gabe Black 396899SN/A 406899SN/Adef template BranchImmDeclare {{ 416899SN/Aclass %(class_name)s : public %(base_class)s 4211793Sbrandon.potter@amd.com{ 4311793Sbrandon.potter@amd.com public: 447805Snilay@cs.wisc.edu // Constructor 4511800Sbrandon.potter@amd.com %(class_name)s(ExtMachInst machInst, int32_t _imm); 467632SBrad.Beckmann@amd.com %(BasicExecDeclare)s 478232Snate@binkert.org}; 487053SN/A}}; 496899SN/A 508832SAli.Saidi@ARM.comdef template BranchImmConstructor {{ 516899SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 526899SN/A int32_t _imm) 5312129Sspwilson2@wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 5412129Sspwilson2@wisc.edu { 5512129Sspwilson2@wisc.edu %(constructor)s; 568832SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 5710412Sandreas.hansson@arm.com for (int x = 0; x < _numDestRegs; x++) { 588932SBrad.Beckmann@amd.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 596899SN/A } 606899SN/A flags[IsCondControl] = true; 6110412Sandreas.hansson@arm.com } else { 6210412Sandreas.hansson@arm.com flags[IsUncondControl] = true; 638184Ssomayeh@cs.wisc.edu } 648932SBrad.Beckmann@amd.com 6511266SBrad.Beckmann@amd.com } 6611266SBrad.Beckmann@amd.com}}; 676899SN/A 687053SN/Adef template BranchImmCondDeclare {{ 696899SN/Aclass %(class_name)s : public %(base_class)s 708932SBrad.Beckmann@amd.com{ 718932SBrad.Beckmann@amd.com public: 728932SBrad.Beckmann@amd.com // Constructor 738932SBrad.Beckmann@amd.com %(class_name)s(ExtMachInst machInst, int32_t _imm, 748932SBrad.Beckmann@amd.com ConditionCode _condCode); 758932SBrad.Beckmann@amd.com %(BasicExecDeclare)s 768932SBrad.Beckmann@amd.com ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 778932SBrad.Beckmann@amd.com}; 788932SBrad.Beckmann@amd.com}}; 798932SBrad.Beckmann@amd.com 808932SBrad.Beckmann@amd.comdef template BranchImmCondConstructor {{ 8111266SBrad.Beckmann@amd.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 828932SBrad.Beckmann@amd.com int32_t _imm, 838932SBrad.Beckmann@amd.com ConditionCode _condCode) 8411266SBrad.Beckmann@amd.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8511266SBrad.Beckmann@amd.com _imm, _condCode) 8611266SBrad.Beckmann@amd.com { 8711266SBrad.Beckmann@amd.com %(constructor)s; 8811266SBrad.Beckmann@amd.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8911266SBrad.Beckmann@amd.com for (int x = 0; x < _numDestRegs; x++) { 9011266SBrad.Beckmann@amd.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9111266SBrad.Beckmann@amd.com } 9211266SBrad.Beckmann@amd.com flags[IsCondControl] = true; 938932SBrad.Beckmann@amd.com } else { 948932SBrad.Beckmann@amd.com flags[IsUncondControl] = true; 958950Sandreas.hansson@arm.com } 9611266SBrad.Beckmann@amd.com } 978932SBrad.Beckmann@amd.com}}; 988932SBrad.Beckmann@amd.com 9911266SBrad.Beckmann@amd.comdef template BranchRegDeclare {{ 1008851Sandreas.hansson@arm.comclass %(class_name)s : public %(base_class)s 1018851Sandreas.hansson@arm.com{ 1027053SN/A public: 1037053SN/A // Constructor 1046899SN/A %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 1056899SN/A %(BasicExecDeclare)s 1066899SN/A}; 1076899SN/A}}; 1087053SN/A 1098932SBrad.Beckmann@amd.comdef template BranchRegConstructor {{ 1108932SBrad.Beckmann@amd.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1118932SBrad.Beckmann@amd.com IntRegIndex _op1) 1126899SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 1136899SN/A { 1147053SN/A %(constructor)s; 1157053SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 1166899SN/A for (int x = 0; x < _numDestRegs; x++) { 1178932SBrad.Beckmann@amd.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1186899SN/A } 1198932SBrad.Beckmann@amd.com flags[IsCondControl] = true; 1207053SN/A } else { 12110302Snilay@cs.wisc.edu flags[IsUncondControl] = true; 1227053SN/A } 1236899SN/A } 1248932SBrad.Beckmann@amd.com}}; 1258932SBrad.Beckmann@amd.com 12611266SBrad.Beckmann@amd.comdef template BranchRegCondDeclare {{ 1276899SN/Aclass %(class_name)s : public %(base_class)s 1288932SBrad.Beckmann@amd.com{ 1296899SN/A public: 1306899SN/A // Constructor 1319294Sandreas.hansson@arm.com %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 1329294Sandreas.hansson@arm.com ConditionCode _condCode); 1336899SN/A %(BasicExecDeclare)s 13411266SBrad.Beckmann@amd.com}; 13511266SBrad.Beckmann@amd.com}}; 1368922Swilliam.wang@arm.com 1378922Swilliam.wang@arm.comdef template BranchRegCondConstructor {{ 1388922Swilliam.wang@arm.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 1398932SBrad.Beckmann@amd.com IntRegIndex _op1, 14011266SBrad.Beckmann@amd.com ConditionCode _condCode) 14111266SBrad.Beckmann@amd.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1428932SBrad.Beckmann@amd.com _op1, _condCode) 1438932SBrad.Beckmann@amd.com { 1448932SBrad.Beckmann@amd.com %(constructor)s; 14511266SBrad.Beckmann@amd.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1468932SBrad.Beckmann@amd.com for (int x = 0; x < _numDestRegs; x++) { 1478932SBrad.Beckmann@amd.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 14811266SBrad.Beckmann@amd.com } 14911266SBrad.Beckmann@amd.com flags[IsCondControl] = true; 15011266SBrad.Beckmann@amd.com } else { 15111266SBrad.Beckmann@amd.com flags[IsUncondControl] = true; 15211266SBrad.Beckmann@amd.com } 15311266SBrad.Beckmann@amd.com } 15411266SBrad.Beckmann@amd.com}}; 15511266SBrad.Beckmann@amd.com 15611266SBrad.Beckmann@amd.comdef template BranchRegRegDeclare {{ 15711266SBrad.Beckmann@amd.comclass %(class_name)s : public %(base_class)s 1588932SBrad.Beckmann@amd.com{ 1598932SBrad.Beckmann@amd.com public: 1608932SBrad.Beckmann@amd.com // Constructor 16111266SBrad.Beckmann@amd.com %(class_name)s(ExtMachInst machInst, 1628932SBrad.Beckmann@amd.com IntRegIndex _op1, IntRegIndex _op2); 16311266SBrad.Beckmann@amd.com %(BasicExecDeclare)s 16411266SBrad.Beckmann@amd.com}; 16511266SBrad.Beckmann@amd.com}}; 1668932SBrad.Beckmann@amd.com 1678932SBrad.Beckmann@amd.comdef template BranchTableDeclare {{ 16811266SBrad.Beckmann@amd.comclass %(class_name)s : public %(base_class)s 1698932SBrad.Beckmann@amd.com{ 1708922Swilliam.wang@arm.com public: 17111266SBrad.Beckmann@amd.com // Constructor 17211266SBrad.Beckmann@amd.com %(class_name)s(ExtMachInst machInst, 1736899SN/A IntRegIndex _op1, IntRegIndex _op2); 1746899SN/A %(BasicExecDeclare)s 1756899SN/A 1766899SN/A %(InitiateAccDeclare)s 1778975Sandreas.hansson@arm.com 1786899SN/A %(CompleteAccDeclare)s 1797053SN/A}; 1807053SN/A}}; 1817053SN/A 1829542Sandreas.hansson@arm.comdef template BranchRegRegConstructor {{ 1836899SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 18411266SBrad.Beckmann@amd.com IntRegIndex _op1, 1857053SN/A IntRegIndex _op2) 1867053SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 1877053SN/A { 1889542Sandreas.hansson@arm.com %(constructor)s; 1897053SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 1907053SN/A for (int x = 0; x < _numDestRegs; x++) { 1917053SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1926899SN/A } 1936899SN/A flags[IsCondControl] = true; 1948950Sandreas.hansson@arm.com } else { 19511266SBrad.Beckmann@amd.com flags[IsUncondControl] = true; 1968950Sandreas.hansson@arm.com } 19711266SBrad.Beckmann@amd.com } 19811266SBrad.Beckmann@amd.com}}; 19911266SBrad.Beckmann@amd.com 20011266SBrad.Beckmann@amd.comdef template BranchImmRegDeclare {{ 20111266SBrad.Beckmann@amd.comclass %(class_name)s : public %(base_class)s 20211266SBrad.Beckmann@amd.com{ 20311266SBrad.Beckmann@amd.com public: 20411266SBrad.Beckmann@amd.com // Constructor 2058950Sandreas.hansson@arm.com %(class_name)s(ExtMachInst machInst, 2068950Sandreas.hansson@arm.com int32_t imm, IntRegIndex _op1); 2078922Swilliam.wang@arm.com %(BasicExecDeclare)s 2088932SBrad.Beckmann@amd.com}; 2096899SN/A}}; 2108932SBrad.Beckmann@amd.com 2116899SN/Adef template BranchImmRegConstructor {{ 2128932SBrad.Beckmann@amd.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 2138932SBrad.Beckmann@amd.com int32_t _imm, 2148932SBrad.Beckmann@amd.com IntRegIndex _op1) 2158932SBrad.Beckmann@amd.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 2168932SBrad.Beckmann@amd.com { 2178932SBrad.Beckmann@amd.com %(constructor)s; 2188932SBrad.Beckmann@amd.com if (!(condCode == COND_AL || condCode == COND_UC)) { 2198932SBrad.Beckmann@amd.com for (int x = 0; x < _numDestRegs; x++) { 2208932SBrad.Beckmann@amd.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 2216899SN/A } 2226899SN/A flags[IsCondControl] = true; 2237053SN/A } else { 2247053SN/A flags[IsUncondControl] = true; 2256899SN/A } 2267053SN/A } 2279475Snilay@cs.wisc.edu}}; 2286899SN/A 22911266SBrad.Beckmann@amd.comdef template BranchTarget {{ 23011266SBrad.Beckmann@amd.com 2317053SN/A ArmISA::PCState 2327053SN/A %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 23311266SBrad.Beckmann@amd.com { 2347053SN/A %(op_decl)s; 23511266SBrad.Beckmann@amd.com %(op_rd)s; 2366899SN/A 2377053SN/A ArmISA::PCState pcs = branchPC; 2387053SN/A %(brTgtCode)s 2397053SN/A pcs.advance(); 2407053SN/A return pcs; 2419475Snilay@cs.wisc.edu } 2426899SN/A}}; 2436899SN/A 2447053SN/A 2457053SN/A