branch.isa revision 7848:cc5e64f8423f 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40def template BranchImmDeclare {{
41class %(class_name)s : public %(base_class)s
42{
43    public:
44        // Constructor
45        %(class_name)s(ExtMachInst machInst, int32_t _imm);
46        %(BasicExecDeclare)s
47};
48}};
49
50def template BranchImmConstructor {{
51    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
52                                          int32_t _imm)
53        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
54    {
55        %(constructor)s;
56        if (!(condCode == COND_AL || condCode == COND_UC)) {
57            for (int x = 0; x < _numDestRegs; x++) {
58                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
59            }
60        }
61    }
62}};
63
64def template BranchImmCondDeclare {{
65class %(class_name)s : public %(base_class)s
66{
67    public:
68        // Constructor
69        %(class_name)s(ExtMachInst machInst, int32_t _imm,
70                       ConditionCode _condCode);
71        %(BasicExecDeclare)s
72};
73}};
74
75def template BranchImmCondConstructor {{
76    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
77                                          int32_t _imm,
78                                          ConditionCode _condCode)
79        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
80                         _imm, _condCode)
81    {
82        %(constructor)s;
83        if (!(condCode == COND_AL || condCode == COND_UC)) {
84            for (int x = 0; x < _numDestRegs; x++) {
85                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
86            }
87        }
88    }
89}};
90
91def template BranchRegDeclare {{
92class %(class_name)s : public %(base_class)s
93{
94    public:
95        // Constructor
96        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
97        %(BasicExecDeclare)s
98};
99}};
100
101def template BranchRegConstructor {{
102    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
103                                          IntRegIndex _op1)
104        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
105    {
106        %(constructor)s;
107        if (!(condCode == COND_AL || condCode == COND_UC)) {
108            for (int x = 0; x < _numDestRegs; x++) {
109                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
110            }
111        }
112    }
113}};
114
115def template BranchRegCondDeclare {{
116class %(class_name)s : public %(base_class)s
117{
118    public:
119        // Constructor
120        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
121                       ConditionCode _condCode);
122        %(BasicExecDeclare)s
123};
124}};
125
126def template BranchRegCondConstructor {{
127    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
128                                          IntRegIndex _op1,
129                                          ConditionCode _condCode)
130        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
131                         _op1, _condCode)
132    {
133        %(constructor)s;
134        if (!(condCode == COND_AL || condCode == COND_UC)) {
135            for (int x = 0; x < _numDestRegs; x++) {
136                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
137            }
138        }
139    }
140}};
141
142def template BranchRegRegDeclare {{
143class %(class_name)s : public %(base_class)s
144{
145    public:
146        // Constructor
147        %(class_name)s(ExtMachInst machInst,
148                       IntRegIndex _op1, IntRegIndex _op2);
149        %(BasicExecDeclare)s
150};
151}};
152
153def template BranchTableDeclare {{
154class %(class_name)s : public %(base_class)s
155{
156    public:
157        // Constructor
158        %(class_name)s(ExtMachInst machInst,
159                       IntRegIndex _op1, IntRegIndex _op2);
160        %(BasicExecDeclare)s
161
162        %(InitiateAccDeclare)s
163
164        %(CompleteAccDeclare)s
165};
166}};
167
168def template BranchRegRegConstructor {{
169    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
170                                          IntRegIndex _op1,
171                                          IntRegIndex _op2)
172        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
173    {
174        %(constructor)s;
175        if (!(condCode == COND_AL || condCode == COND_UC)) {
176            for (int x = 0; x < _numDestRegs; x++) {
177                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
178            }
179        }
180    }
181}};
182
183def template BranchImmRegDeclare {{
184class %(class_name)s : public %(base_class)s
185{
186    public:
187        // Constructor
188        %(class_name)s(ExtMachInst machInst,
189                       int32_t imm, IntRegIndex _op1);
190        %(BasicExecDeclare)s
191};
192}};
193
194def template BranchImmRegConstructor {{
195    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
196                                          int32_t _imm,
197                                          IntRegIndex _op1)
198        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
199    {
200        %(constructor)s;
201        if (!(condCode == COND_AL || condCode == COND_UC)) {
202            for (int x = 0; x < _numDestRegs; x++) {
203                _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
204            }
205        }
206    }
207}};
208