branch.isa revision 10334
17150Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27150Sgblack@eecs.umich.edu 310334Smitch.hayenga@arm.com// Copyright (c) 2010, 2014 ARM Limited 47150Sgblack@eecs.umich.edu// All rights reserved 57150Sgblack@eecs.umich.edu// 67150Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77150Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87150Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97150Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107150Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117150Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127150Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137150Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147150Sgblack@eecs.umich.edu// 157150Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167150Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177150Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187150Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197150Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207150Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217150Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227150Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237150Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247150Sgblack@eecs.umich.edu// this software without specific prior written permission. 257150Sgblack@eecs.umich.edu// 267150Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277150Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287150Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297150Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307150Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317150Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327150Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337150Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347150Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357150Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367150Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377150Sgblack@eecs.umich.edu// 387150Sgblack@eecs.umich.edu// Authors: Gabe Black 397150Sgblack@eecs.umich.edu 407150Sgblack@eecs.umich.edudef template BranchImmDeclare {{ 417150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 427150Sgblack@eecs.umich.edu{ 437150Sgblack@eecs.umich.edu public: 447150Sgblack@eecs.umich.edu // Constructor 457150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, int32_t _imm); 467150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 477150Sgblack@eecs.umich.edu}; 487150Sgblack@eecs.umich.edu}}; 497150Sgblack@eecs.umich.edu 507150Sgblack@eecs.umich.edudef template BranchImmConstructor {{ 5110184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 527150Sgblack@eecs.umich.edu int32_t _imm) 537150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 547150Sgblack@eecs.umich.edu { 557150Sgblack@eecs.umich.edu %(constructor)s; 567848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 577848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 587848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 597848SAli.Saidi@ARM.com } 608146SAli.Saidi@ARM.com flags[IsCondControl] = true; 618146SAli.Saidi@ARM.com } else { 628146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 637848SAli.Saidi@ARM.com } 648146SAli.Saidi@ARM.com 657150Sgblack@eecs.umich.edu } 667150Sgblack@eecs.umich.edu}}; 677150Sgblack@eecs.umich.edu 687150Sgblack@eecs.umich.edudef template BranchImmCondDeclare {{ 697150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 707150Sgblack@eecs.umich.edu{ 717150Sgblack@eecs.umich.edu public: 727150Sgblack@eecs.umich.edu // Constructor 737150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, int32_t _imm, 747150Sgblack@eecs.umich.edu ConditionCode _condCode); 757150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 768146SAli.Saidi@ARM.com ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 779552Sandreas.hansson@arm.com 789552Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden branchTarget 799552Sandreas.hansson@arm.com using StaticInst::branchTarget; 807150Sgblack@eecs.umich.edu}; 817150Sgblack@eecs.umich.edu}}; 827150Sgblack@eecs.umich.edu 837150Sgblack@eecs.umich.edudef template BranchImmCondConstructor {{ 8410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 857150Sgblack@eecs.umich.edu int32_t _imm, 867150Sgblack@eecs.umich.edu ConditionCode _condCode) 877150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 887150Sgblack@eecs.umich.edu _imm, _condCode) 897150Sgblack@eecs.umich.edu { 907150Sgblack@eecs.umich.edu %(constructor)s; 917848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 927848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 937848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 947848SAli.Saidi@ARM.com } 958146SAli.Saidi@ARM.com flags[IsCondControl] = true; 968146SAli.Saidi@ARM.com } else { 978146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 987848SAli.Saidi@ARM.com } 997150Sgblack@eecs.umich.edu } 1007150Sgblack@eecs.umich.edu}}; 1017150Sgblack@eecs.umich.edu 1027150Sgblack@eecs.umich.edudef template BranchRegDeclare {{ 1037150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1047150Sgblack@eecs.umich.edu{ 1057150Sgblack@eecs.umich.edu public: 1067150Sgblack@eecs.umich.edu // Constructor 1077150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 1087150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1097150Sgblack@eecs.umich.edu}; 1107150Sgblack@eecs.umich.edu}}; 1117150Sgblack@eecs.umich.edu 1127150Sgblack@eecs.umich.edudef template BranchRegConstructor {{ 11310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1147150Sgblack@eecs.umich.edu IntRegIndex _op1) 1157150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 1167150Sgblack@eecs.umich.edu { 1177150Sgblack@eecs.umich.edu %(constructor)s; 1187848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1197848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1207848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1217848SAli.Saidi@ARM.com } 1228146SAli.Saidi@ARM.com flags[IsCondControl] = true; 1238146SAli.Saidi@ARM.com } else { 1248146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 1257848SAli.Saidi@ARM.com } 1268203SAli.Saidi@ARM.com if (%(is_ras_pop)s) 1278203SAli.Saidi@ARM.com flags[IsReturn] = true; 1287150Sgblack@eecs.umich.edu } 1297150Sgblack@eecs.umich.edu}}; 1307150Sgblack@eecs.umich.edu 1317150Sgblack@eecs.umich.edudef template BranchRegCondDeclare {{ 1327150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1337150Sgblack@eecs.umich.edu{ 1347150Sgblack@eecs.umich.edu public: 1357150Sgblack@eecs.umich.edu // Constructor 1367150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 1377150Sgblack@eecs.umich.edu ConditionCode _condCode); 1387150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1397150Sgblack@eecs.umich.edu}; 1407150Sgblack@eecs.umich.edu}}; 1417150Sgblack@eecs.umich.edu 1427150Sgblack@eecs.umich.edudef template BranchRegCondConstructor {{ 14310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1447150Sgblack@eecs.umich.edu IntRegIndex _op1, 1457150Sgblack@eecs.umich.edu ConditionCode _condCode) 1467150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1477150Sgblack@eecs.umich.edu _op1, _condCode) 1487150Sgblack@eecs.umich.edu { 1497150Sgblack@eecs.umich.edu %(constructor)s; 1507848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1517848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1527848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1537848SAli.Saidi@ARM.com } 1548146SAli.Saidi@ARM.com flags[IsCondControl] = true; 1558146SAli.Saidi@ARM.com } else { 1568146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 1577848SAli.Saidi@ARM.com } 1588203SAli.Saidi@ARM.com if (%(is_ras_pop)s) 1598203SAli.Saidi@ARM.com flags[IsReturn] = true; 1607150Sgblack@eecs.umich.edu } 1617150Sgblack@eecs.umich.edu}}; 1627150Sgblack@eecs.umich.edu 1637150Sgblack@eecs.umich.edudef template BranchRegRegDeclare {{ 1647150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1657150Sgblack@eecs.umich.edu{ 1667150Sgblack@eecs.umich.edu public: 1677150Sgblack@eecs.umich.edu // Constructor 1687150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1697150Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2); 1707150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1717150Sgblack@eecs.umich.edu}; 1727150Sgblack@eecs.umich.edu}}; 1737150Sgblack@eecs.umich.edu 1747150Sgblack@eecs.umich.edudef template BranchTableDeclare {{ 1757150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1767150Sgblack@eecs.umich.edu{ 1777150Sgblack@eecs.umich.edu public: 1787150Sgblack@eecs.umich.edu // Constructor 1797150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1807150Sgblack@eecs.umich.edu IntRegIndex _op1, IntRegIndex _op2); 1817150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1827150Sgblack@eecs.umich.edu 1837150Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 1847150Sgblack@eecs.umich.edu 1857150Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 1867150Sgblack@eecs.umich.edu}; 1877150Sgblack@eecs.umich.edu}}; 1887150Sgblack@eecs.umich.edu 1897150Sgblack@eecs.umich.edudef template BranchRegRegConstructor {{ 19010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 1917150Sgblack@eecs.umich.edu IntRegIndex _op1, 1927150Sgblack@eecs.umich.edu IntRegIndex _op2) 1937150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 1947150Sgblack@eecs.umich.edu { 1957150Sgblack@eecs.umich.edu %(constructor)s; 1967848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 1977848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 1987848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1997848SAli.Saidi@ARM.com } 2008146SAli.Saidi@ARM.com flags[IsCondControl] = true; 2018146SAli.Saidi@ARM.com } else { 2028146SAli.Saidi@ARM.com flags[IsUncondControl] = true; 2037848SAli.Saidi@ARM.com } 2047150Sgblack@eecs.umich.edu } 2057150Sgblack@eecs.umich.edu}}; 2067150Sgblack@eecs.umich.edu 2077150Sgblack@eecs.umich.edudef template BranchImmRegDeclare {{ 2087150Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 2097150Sgblack@eecs.umich.edu{ 2107150Sgblack@eecs.umich.edu public: 2117150Sgblack@eecs.umich.edu // Constructor 2127150Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 2137150Sgblack@eecs.umich.edu int32_t imm, IntRegIndex _op1); 2147150Sgblack@eecs.umich.edu %(BasicExecDeclare)s 21510334Smitch.hayenga@arm.com ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 21610334Smitch.hayenga@arm.com 21710334Smitch.hayenga@arm.com /// Explicitly import the otherwise hidden branchTarget 21810334Smitch.hayenga@arm.com using StaticInst::branchTarget; 2197150Sgblack@eecs.umich.edu}; 2207150Sgblack@eecs.umich.edu}}; 2217150Sgblack@eecs.umich.edu 2228892Sb.grayson@samsung.com// Only used by CBNZ, CBZ which is conditional based on 2238892Sb.grayson@samsung.com// a register value even though the instruction is always unconditional. 2247150Sgblack@eecs.umich.edudef template BranchImmRegConstructor {{ 22510184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 2267150Sgblack@eecs.umich.edu int32_t _imm, 2277150Sgblack@eecs.umich.edu IntRegIndex _op1) 2287150Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 2297150Sgblack@eecs.umich.edu { 2307150Sgblack@eecs.umich.edu %(constructor)s; 2318892Sb.grayson@samsung.com flags[IsCondControl] = true; 2327150Sgblack@eecs.umich.edu } 2337150Sgblack@eecs.umich.edu}}; 2348146SAli.Saidi@ARM.com 2358146SAli.Saidi@ARM.comdef template BranchTarget {{ 2368146SAli.Saidi@ARM.com 2378146SAli.Saidi@ARM.com ArmISA::PCState 2388146SAli.Saidi@ARM.com %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const 2398146SAli.Saidi@ARM.com { 2408146SAli.Saidi@ARM.com %(op_decl)s; 2418146SAli.Saidi@ARM.com %(op_rd)s; 2428146SAli.Saidi@ARM.com 2438146SAli.Saidi@ARM.com ArmISA::PCState pcs = branchPC; 2448146SAli.Saidi@ARM.com %(brTgtCode)s 2458146SAli.Saidi@ARM.com pcs.advance(); 2468146SAli.Saidi@ARM.com return pcs; 2478146SAli.Saidi@ARM.com } 2488146SAli.Saidi@ARM.com}}; 2498146SAli.Saidi@ARM.com 2508146SAli.Saidi@ARM.com 251