operands.isa revision 8204:6c051a8df26a 
1// -*- mode:c++ -*-
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14// Copyright (c) 2007-2008 The Florida State University
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'tud' : ('twin64 int', 64),
51    'sf' : ('float', 32),
52    'df' : ('float', 64)
53}};
54
55let {{
56    maybePCRead = '''
57        ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybeAlignedPCRead = '''
60        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
61         xc->%(func)s(this, %(op_idx)s))
62    '''
63    maybePCWrite = '''
64        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66    '''
67    maybeIWPCWrite = '''
68        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70    '''
71    maybeAIWPCWrite = '''
72        if (%(reg_idx)s == PCReg) {
73            bool thumb = THUMB;
74            if (thumb) {
75                setNextPC(xc, %(final_val)s);
76            } else {
77                setIWNextPC(xc, %(final_val)s);
78            }
79        } else {
80            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81        }
82    '''
83
84    #PCState operands need to have a sorting index (the number at the end)
85    #less than all the integer registers which might update the PC. That way
86    #if the flag bits of the pc state are updated and a branch happens through
87    #R15, the updates are layered properly and the R15 update isn't lost.
88    srtNormal = 5
89    srtCpsr = 4
90    srtBase = 3
91    srtPC = 2
92    srtMode = 1
93    srtEPC = 0
94
95    def floatReg(idx):
96        return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
97
98    def intReg(idx):
99        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
100                maybePCRead, maybePCWrite)
101
102    def intRegNPC(idx):
103        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
104
105    def intRegAPC(idx, id = srtNormal):
106        return ('IntReg', 'uw', idx, 'IsInteger', id,
107                maybeAlignedPCRead, maybePCWrite)
108
109    def intRegIWPC(idx):
110        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
111                maybePCRead, maybeIWPCWrite)
112
113    def intRegAIWPC(idx):
114        return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
115                maybePCRead, maybeAIWPCWrite)
116
117    def intRegCC(idx):
118        return ('IntReg', 'uw', idx, None, srtNormal)
119
120    def cntrlReg(idx, id = srtNormal, type = 'uw'):
121        return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
122
123    def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
124        return ('ControlReg', type, idx, None, id)
125
126    def pcStateReg(idx, id):
127        return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
128}};
129
130def operands {{
131    #Abstracted integer reg operands
132    'Dest': intReg('dest'),
133    'IWDest': intRegIWPC('dest'),
134    'AIWDest': intRegAIWPC('dest'),
135    'Dest2': intReg('dest2'),
136    'Result': intReg('result'),
137    'Base': intRegAPC('base', id = srtBase),
138    'Index': intReg('index'),
139    'Shift': intReg('shift'),
140    'Op1': intReg('op1'),
141    'Op2': intReg('op2'),
142    'Op3': intReg('op3'),
143    'Reg0': intReg('reg0'),
144    'Reg1': intReg('reg1'),
145    'Reg2': intReg('reg2'),
146    'Reg3': intReg('reg3'),
147
148    #Fixed index integer reg operands
149    'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
150    'LR': intRegNPC('INTREG_LR'),
151    'R7': intRegNPC('7'),
152    # First four arguments are passed in registers
153    'R0': intRegNPC('0'),
154    'R1': intRegNPC('1'),
155    'R2': intRegNPC('2'),
156    'R3': intRegNPC('3'),
157
158    #Pseudo integer condition code registers
159    'CondCodes': intRegCC('INTREG_CONDCODES'),
160    'OptCondCodes': intRegCC(
161            '''(condCode == COND_AL || condCode == COND_UC) ?
162               INTREG_ZERO : INTREG_CONDCODES'''),
163    'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
164
165    #Abstracted floating point reg operands
166    'FpDest': floatReg('(dest + 0)'),
167    'FpDestP0': floatReg('(dest + 0)'),
168    'FpDestP1': floatReg('(dest + 1)'),
169    'FpDestP2': floatReg('(dest + 2)'),
170    'FpDestP3': floatReg('(dest + 3)'),
171    'FpDestP4': floatReg('(dest + 4)'),
172    'FpDestP5': floatReg('(dest + 5)'),
173    'FpDestP6': floatReg('(dest + 6)'),
174    'FpDestP7': floatReg('(dest + 7)'),
175    'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
176    'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
177    'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
178    'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
179    'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
180    'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
181    'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
182    'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
183
184    'FpDest2': floatReg('(dest2 + 0)'),
185    'FpDest2P0': floatReg('(dest2 + 0)'),
186    'FpDest2P1': floatReg('(dest2 + 1)'),
187    'FpDest2P2': floatReg('(dest2 + 2)'),
188    'FpDest2P3': floatReg('(dest2 + 3)'),
189
190    'FpOp1': floatReg('(op1 + 0)'),
191    'FpOp1P0': floatReg('(op1 + 0)'),
192    'FpOp1P1': floatReg('(op1 + 1)'),
193    'FpOp1P2': floatReg('(op1 + 2)'),
194    'FpOp1P3': floatReg('(op1 + 3)'),
195    'FpOp1P4': floatReg('(op1 + 4)'),
196    'FpOp1P5': floatReg('(op1 + 5)'),
197    'FpOp1P6': floatReg('(op1 + 6)'),
198    'FpOp1P7': floatReg('(op1 + 7)'),
199    'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
200    'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
201    'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
202    'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
203    'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
204    'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
205    'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
206    'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
207
208    'FpOp2': floatReg('(op2 + 0)'),
209    'FpOp2P0': floatReg('(op2 + 0)'),
210    'FpOp2P1': floatReg('(op2 + 1)'),
211    'FpOp2P2': floatReg('(op2 + 2)'),
212    'FpOp2P3': floatReg('(op2 + 3)'),
213
214    #Abstracted control reg operands
215    'MiscDest': cntrlReg('dest'),
216    'MiscOp1': cntrlReg('op1'),
217
218    #Fixed index control regs
219    'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
220    'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'),
221    'Spsr': cntrlRegNC('MISCREG_SPSR'),
222    'Fpsr': cntrlRegNC('MISCREG_FPSR'),
223    'Fpsid': cntrlRegNC('MISCREG_FPSID'),
224    'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
225    'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
226    'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
227    'Cpacr': cntrlReg('MISCREG_CPACR'),
228    'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
229    'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
230    'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
231
232    #Register fields for microops
233    'URa' : intReg('ura'),
234    'IWRa' : intRegIWPC('ura'),
235    'Fa' : floatReg('ura'),
236    'URb' : intReg('urb'),
237    'URc' : intReg('urc'),
238
239    #Memory Operand
240    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
241
242    #PCState fields
243    'PC': pcStateReg('instPC', srtPC),
244    'NPC': pcStateReg('instNPC', srtPC),
245    'pNPC': pcStateReg('instNPC', srtEPC),
246    'IWNPC': pcStateReg('instIWNPC', srtPC),
247    'Thumb': pcStateReg('thumb', srtPC),
248    'NextThumb': pcStateReg('nextThumb', srtMode),
249    'NextJazelle': pcStateReg('nextJazelle', srtMode),
250    'ForcedItState': pcStateReg('forcedItState', srtMode),
251
252    #Register operands depending on a field in the instruction encoding. These
253    #should be avoided since they may not be portable across different
254    #encodings of the same instruction.
255    'Rd': intReg('RD'),
256    'Rm': intReg('RM'),
257    'Rs': intReg('RS'),
258    'Rn': intReg('RN'),
259    'Rt': intReg('RT')
260}};
261