operands.isa revision 7422:feddb9077def 
1// -*- mode:c++ -*-
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39//
40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'sf' : ('float', 32),
51    'df' : ('float', 64)
52}};
53
54let {{
55    maybePCRead = '''
56        ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57         xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybeAlignedPCRead = '''
60        ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
61         xc->%(func)s(this, %(op_idx)s))
62    '''
63    maybePCWrite = '''
64        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66    '''
67    maybeIWPCWrite = '''
68        ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70    '''
71    maybeAIWPCWrite = '''
72        if (%(reg_idx)s == PCReg) {
73            bool thumb = THUMB;
74            if (thumb) {
75                setNextPC(xc, %(final_val)s);
76            } else {
77                setIWNextPC(xc, %(final_val)s);
78            }
79        } else {
80            xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81        }
82    '''
83
84    readNPC = 'xc->readNextPC() & ~PcModeMask'
85    writeNPC = 'setNextPC(xc, %(final_val)s)'
86    writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
87    forceNPC = 'xc->setNextPC(%(final_val)s)'
88}};
89
90def operands {{
91    #Abstracted integer reg operands
92    'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
93             maybePCRead, maybePCWrite),
94    'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
95    'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
96    'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
97    'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
98    'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
99    'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
100               maybePCRead, maybePCWrite),
101    'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
102              maybePCRead, maybePCWrite),
103    'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
104    'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
105    'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
106    'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
107    'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
108    'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
109               maybePCRead, maybeIWPCWrite),
110    'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
111                maybePCRead, maybeAIWPCWrite),
112    'SpMode': ('IntReg', 'uw',
113               'intRegInMode((OperatingMode)regMode, INTREG_SP)',
114               'IsInteger', 2),
115    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
116    'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
117             maybeAlignedPCRead, maybePCWrite),
118    'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
119              maybePCRead, maybePCWrite),
120    'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
121              maybePCRead, maybePCWrite),
122    'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
123    'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
124    'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
125    'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
126    'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
127    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
128    'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
129              maybePCRead, maybePCWrite),
130    'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
131    'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
132    'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
133    'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
134    'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
135    'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
136              maybePCRead, maybePCWrite),
137    'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
138              maybePCRead, maybePCWrite),
139    'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
140              maybePCRead, maybePCWrite),
141    'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
142              maybePCRead, maybePCWrite),
143    'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
144              maybePCRead, maybePCWrite),
145    'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
146              maybePCRead, maybePCWrite),
147    #General Purpose Integer Reg Operands
148    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
149    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
150    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
151    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
152    'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
153    'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
154
155    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
156    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
157    'OptCondCodes': ('IntReg', 'uw',
158            '''(condCode == COND_AL || condCode == COND_UC) ?
159               INTREG_ZERO : INTREG_CONDCODES''', None, 2),
160
161    #Register fields for microops
162    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
163    'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
164            maybePCRead, maybeIWPCWrite),
165    'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
166    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
167
168    #General Purpose Floating Point Reg Operands
169    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
170    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
171    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
172
173    #Memory Operand
174    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
175
176    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
177    'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
178    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
179    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
180    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
181    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
182    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
183    'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
184    'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
185    'PC': ('PC', 'ud', None, None, 2),
186    'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
187            readNPC, writeNPC),
188    'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
189             readNPC, forceNPC),
190    'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
191              readNPC, writeIWNPC),
192}};
193