operands.isa revision 7147:53c74014d4ef 
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14// Copyright (c) 2007-2008 The Florida State University
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40// Authors: Stephen Hines
41
42def operand_types {{
43    'sb' : ('signed int', 8),
44    'ub' : ('unsigned int', 8),
45    'sh' : ('signed int', 16),
46    'uh' : ('unsigned int', 16),
47    'sw' : ('signed int', 32),
48    'uw' : ('unsigned int', 32),
49    'ud' : ('unsigned int', 64),
50    'sf' : ('float', 32),
51    'df' : ('float', 64)
52}};
53
54let {{
55    maybePCRead = '''
56        ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57         xc->%(func)s(this, %(op_idx)s))
58    '''
59    maybePCWrite = '''
60        ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61         xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62    '''
63
64    readNPC = 'xc->readNextPC() & ~PcModeMask'
65    writeNPC = 'setNextPC(xc, %(final_val)s)'
66}};
67
68def operands {{
69    #Abstracted integer reg operands
70    'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
71             maybePCRead, maybePCWrite),
72    'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
73             maybePCRead, maybePCWrite),
74    'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
75              maybePCRead, maybePCWrite),
76    'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
77              maybePCRead, maybePCWrite),
78    'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
79              maybePCRead, maybePCWrite),
80    'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
81              maybePCRead, maybePCWrite),
82    #General Purpose Integer Reg Operands
83    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
84    'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
85    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
86    'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
87    'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
88    'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
89
90    #Destination register for load/store double instructions
91    'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
92    'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
93
94    'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
95    'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
96    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
97    'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
98
99    #Register fields for microops
100    'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
101    'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
102
103    #General Purpose Floating Point Reg Operands
104    'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
105    'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
106    'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
107
108    #Memory Operand
109    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
110
111    'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
112    'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
113    'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
114    'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
115    'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
116    'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
117    'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
118            readNPC, writeNPC),
119}};
120