operands.isa revision 7114:5975996bcf2a
19070Satgutier@umich.edu// -*- mode:c++ -*- 29070Satgutier@umich.edu// Copyright (c) 2010 ARM Limited 39070Satgutier@umich.edu// All rights reserved 49070Satgutier@umich.edu// 59070Satgutier@umich.edu// The license below extends only to copyright in the software and shall 69070Satgutier@umich.edu// not be construed as granting a license to any other intellectual 79070Satgutier@umich.edu// property including but not limited to intellectual property relating 89070Satgutier@umich.edu// to a hardware implementation of the functionality of the software 99070Satgutier@umich.edu// licensed hereunder. You may use the software subject to the license 109070Satgutier@umich.edu// terms below provided that you ensure that this notice is replicated 119070Satgutier@umich.edu// unmodified and in its entirety in all distributions of the software, 129070Satgutier@umich.edu// modified or unmodified, in source code or in binary form. 139070Satgutier@umich.edu// 149070Satgutier@umich.edu// Copyright (c) 2007-2008 The Florida State University 159070Satgutier@umich.edu// All rights reserved. 169070Satgutier@umich.edu// 179070Satgutier@umich.edu// Redistribution and use in source and binary forms, with or without 189070Satgutier@umich.edu// modification, are permitted provided that the following conditions are 199070Satgutier@umich.edu// met: redistributions of source code must retain the above copyright 209070Satgutier@umich.edu// notice, this list of conditions and the following disclaimer; 219070Satgutier@umich.edu// redistributions in binary form must reproduce the above copyright 229070Satgutier@umich.edu// notice, this list of conditions and the following disclaimer in the 239070Satgutier@umich.edu// documentation and/or other materials provided with the distribution; 249070Satgutier@umich.edu// neither the name of the copyright holders nor the names of its 259070Satgutier@umich.edu// contributors may be used to endorse or promote products derived from 269070Satgutier@umich.edu// this software without specific prior written permission. 279070Satgutier@umich.edu// 289070Satgutier@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299070Satgutier@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309070Satgutier@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319070Satgutier@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329070Satgutier@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339070Satgutier@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349070Satgutier@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359070Satgutier@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369070Satgutier@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379070Satgutier@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389070Satgutier@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39// 40// Authors: Stephen Hines 41 42def operand_types {{ 43 'sb' : ('signed int', 8), 44 'ub' : ('unsigned int', 8), 45 'sh' : ('signed int', 16), 46 'uh' : ('unsigned int', 16), 47 'sw' : ('signed int', 32), 48 'uw' : ('unsigned int', 32), 49 'ud' : ('unsigned int', 64), 50 'sf' : ('float', 32), 51 'df' : ('float', 64) 52}}; 53 54let {{ 55 maybePCRead = ''' 56 ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) : 57 xc->%(func)s(this, %(op_idx)s)) 58 ''' 59 maybePCWrite = ''' 60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) : 61 xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 62 ''' 63 64 readPC = 'xc->readPC() & ~PcModeMask' 65 writePC = 'setPC(xc, %(final_val)s)' 66 67 readNPC = 'xc->readNextPC() & ~PcModeMask' 68 writeNPC = 'setNextPC(xc, %(final_val)s)' 69}}; 70 71def operands {{ 72 #General Purpose Integer Reg Operands 73 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 74 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 75 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 76 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 77 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 78 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 79 80 #Destination register for load/store double instructions 81 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 82 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 83 84 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), 85 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), 86 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 87 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 88 89 #Register fields for microops 90 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 91 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 92 93 #General Purpose Floating Point Reg Operands 94 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 95 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 96 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 97 98 #Memory Operand 99 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 100 101 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 102 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 103 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 104 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 105 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 106 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 107 'PC': ('PC', 'ud', None, (None, None, 'IsControl'), 50, 108 readPC, writePC), 109 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 110 readNPC, writeNPC), 111}}; 112