operands.isa revision 6312:94b1a249422e
16700Snate@binkert.org// -*- mode:c++ -*- 26700Snate@binkert.org 36700Snate@binkert.org// Copyright (c) 2007-2008 The Florida State University 46700Snate@binkert.org// All rights reserved. 56700Snate@binkert.org// 66700Snate@binkert.org// Redistribution and use in source and binary forms, with or without 76700Snate@binkert.org// modification, are permitted provided that the following conditions are 86700Snate@binkert.org// met: redistributions of source code must retain the above copyright 96700Snate@binkert.org// notice, this list of conditions and the following disclaimer; 106700Snate@binkert.org// redistributions in binary form must reproduce the above copyright 116700Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 126700Snate@binkert.org// documentation and/or other materials provided with the distribution; 136700Snate@binkert.org// neither the name of the copyright holders nor the names of its 146700Snate@binkert.org// contributors may be used to endorse or promote products derived from 156700Snate@binkert.org// this software without specific prior written permission. 166700Snate@binkert.org// 176700Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186700Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196700Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206700Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216700Snate@binkert.org// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226700Snate@binkert.org// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236700Snate@binkert.org// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246700Snate@binkert.org// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256700Snate@binkert.org// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266700Snate@binkert.org// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276700Snate@binkert.org// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286285Snate@binkert.org// 297805Snilay@cs.wisc.edu// Authors: Stephen Hines 306285Snate@binkert.org 316285Snate@binkert.orgdef operand_types {{ 326881SBrad.Beckmann@amd.com 'sb' : ('signed int', 8), 336285Snate@binkert.org 'ub' : ('unsigned int', 8), 346876Ssteve.reinhardt@amd.com 'sh' : ('signed int', 16), 356876Ssteve.reinhardt@amd.com 'uh' : ('unsigned int', 16), 366285Snate@binkert.org 'sw' : ('signed int', 32), 376876Ssteve.reinhardt@amd.com 'uw' : ('unsigned int', 32), 386876Ssteve.reinhardt@amd.com 'ud' : ('unsigned int', 64), 396876Ssteve.reinhardt@amd.com 'sf' : ('float', 32), 406876Ssteve.reinhardt@amd.com 'df' : ('float', 64) 416876Ssteve.reinhardt@amd.com}}; 426876Ssteve.reinhardt@amd.com 436876Ssteve.reinhardt@amd.comlet {{ 446876Ssteve.reinhardt@amd.com maybePCRead = ''' 456881SBrad.Beckmann@amd.com ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) : 466881SBrad.Beckmann@amd.com xc->%(func)s(this, %(op_idx)s)) 477054Snate@binkert.org ''' 486881SBrad.Beckmann@amd.com maybePCWrite = ''' 496881SBrad.Beckmann@amd.com ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) : 506876Ssteve.reinhardt@amd.com xc->%(func)s(this, %(op_idx)s, %(final_val)s)) 516876Ssteve.reinhardt@amd.com ''' 526881SBrad.Beckmann@amd.com}}; 536881SBrad.Beckmann@amd.com 546881SBrad.Beckmann@amd.comdef operands {{ 556285Snate@binkert.org #General Purpose Integer Reg Operands 566285Snate@binkert.org 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 577054Snate@binkert.org 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 587054Snate@binkert.org 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 596285Snate@binkert.org 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 607054Snate@binkert.org 616285Snate@binkert.org #Destination register for load/store double instructions 626493STushar.Krishna@amd.com 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 637054Snate@binkert.org 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 647054Snate@binkert.org 656493STushar.Krishna@amd.com 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6), 667054Snate@binkert.org 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7), 677054Snate@binkert.org 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8), 687805Snilay@cs.wisc.edu 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9), 697054Snate@binkert.org 707054Snate@binkert.org #Register fields for microops 717054Snate@binkert.org 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 727054Snate@binkert.org 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 737054Snate@binkert.org 747054Snate@binkert.org #General Purpose Floating Point Reg Operands 757548SBrad.Beckmann@amd.com 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 767904SBrad.Beckmann@amd.com 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 777054Snate@binkert.org 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 787054Snate@binkert.org 797054Snate@binkert.org #Memory Operand 807054Snate@binkert.org 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 817054Snate@binkert.org 827054Snate@binkert.org 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 837054Snate@binkert.org 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), 847054Snate@binkert.org 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42), 857054Snate@binkert.org 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43), 867054Snate@binkert.org 877054Snate@binkert.org}}; 887054Snate@binkert.org