str64.isa revision 12219
110037SARM gem5 Developers// -*- mode:c++ -*- 210037SARM gem5 Developers 312219Snikos.nikoleris@arm.com// Copyright (c) 2011-2013,2017 ARM Limited 410037SARM gem5 Developers// All rights reserved 510037SARM gem5 Developers// 610037SARM gem5 Developers// The license below extends only to copyright in the software and shall 710037SARM gem5 Developers// not be construed as granting a license to any other intellectual 810037SARM gem5 Developers// property including but not limited to intellectual property relating 910037SARM gem5 Developers// to a hardware implementation of the functionality of the software 1010037SARM gem5 Developers// licensed hereunder. You may use the software subject to the license 1110037SARM gem5 Developers// terms below provided that you ensure that this notice is replicated 1210037SARM gem5 Developers// unmodified and in its entirety in all distributions of the software, 1310037SARM gem5 Developers// modified or unmodified, in source code or in binary form. 1410037SARM gem5 Developers// 1510037SARM gem5 Developers// Redistribution and use in source and binary forms, with or without 1610037SARM gem5 Developers// modification, are permitted provided that the following conditions are 1710037SARM gem5 Developers// met: redistributions of source code must retain the above copyright 1810037SARM gem5 Developers// notice, this list of conditions and the following disclaimer; 1910037SARM gem5 Developers// redistributions in binary form must reproduce the above copyright 2010037SARM gem5 Developers// notice, this list of conditions and the following disclaimer in the 2110037SARM gem5 Developers// documentation and/or other materials provided with the distribution; 2210037SARM gem5 Developers// neither the name of the copyright holders nor the names of its 2310037SARM gem5 Developers// contributors may be used to endorse or promote products derived from 2410037SARM gem5 Developers// this software without specific prior written permission. 2510037SARM gem5 Developers// 2610037SARM gem5 Developers// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2710037SARM gem5 Developers// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2810037SARM gem5 Developers// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2910037SARM gem5 Developers// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3010037SARM gem5 Developers// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3110037SARM gem5 Developers// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3210037SARM gem5 Developers// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3310037SARM gem5 Developers// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3410037SARM gem5 Developers// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3510037SARM gem5 Developers// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3610037SARM gem5 Developers// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3710037SARM gem5 Developers// 3810037SARM gem5 Developers// Authors: Gabe Black 3910037SARM gem5 Developers 4010037SARM gem5 Developerslet {{ 4110037SARM gem5 Developers 4210037SARM gem5 Developers header_output = "" 4310037SARM gem5 Developers decoder_output = "" 4410037SARM gem5 Developers exec_output = "" 4510037SARM gem5 Developers 4610037SARM gem5 Developers class StoreInst64(LoadStoreInst): 4710037SARM gem5 Developers execBase = 'Store64' 4810037SARM gem5 Developers micro = False 4910037SARM gem5 Developers 5010037SARM gem5 Developers def __init__(self, mnem, Name, size=4, user=False, flavor="normal", 5110037SARM gem5 Developers top = False): 5210037SARM gem5 Developers super(StoreInst64, self).__init__() 5310037SARM gem5 Developers 5410037SARM gem5 Developers self.name = mnem 5510037SARM gem5 Developers self.Name = Name 5610037SARM gem5 Developers self.size = size 5710037SARM gem5 Developers self.user = user 5810037SARM gem5 Developers self.flavor = flavor 5910037SARM gem5 Developers self.top = top 6010037SARM gem5 Developers 6110037SARM gem5 Developers self.memFlags = ["ArmISA::TLB::MustBeOne"] 6210037SARM gem5 Developers self.instFlags = [] 6310037SARM gem5 Developers self.codeBlobs = { "postacc_code" : "" } 6410037SARM gem5 Developers 6510037SARM gem5 Developers # Add memory request flags where necessary 6610037SARM gem5 Developers if self.user: 6710037SARM gem5 Developers self.memFlags.append("ArmISA::TLB::UserMode") 6810037SARM gem5 Developers 6910037SARM gem5 Developers if self.flavor in ("relexp", "exp"): 7010037SARM gem5 Developers # For exclusive pair ops alignment check is based on total size 7110037SARM gem5 Developers self.memFlags.append("%d" % int(math.log(self.size, 2) + 1)) 7210037SARM gem5 Developers elif not (self.size == 16 and self.top): 7310037SARM gem5 Developers # Only the first microop should perform alignment checking. 7410037SARM gem5 Developers self.memFlags.append("%d" % int(math.log(self.size, 2))) 7510037SARM gem5 Developers 7610037SARM gem5 Developers if self.flavor not in ("release", "relex", "exclusive", 7710037SARM gem5 Developers "relexp", "exp"): 7810037SARM gem5 Developers self.memFlags.append("ArmISA::TLB::AllowUnaligned") 7910037SARM gem5 Developers 8010037SARM gem5 Developers if self.micro: 8110037SARM gem5 Developers self.instFlags.append("IsMicroop") 8210037SARM gem5 Developers 8310037SARM gem5 Developers if self.flavor in ("release", "relex", "relexp"): 8410037SARM gem5 Developers self.instFlags.extend(["IsMemBarrier", 8510037SARM gem5 Developers "IsWriteBarrier", 8610037SARM gem5 Developers "IsReadBarrier"]) 8710037SARM gem5 Developers if self.flavor in ("relex", "exclusive", "exp", "relexp"): 8810037SARM gem5 Developers self.instFlags.append("IsStoreConditional") 8910037SARM gem5 Developers self.memFlags.append("Request::LLSC") 9010037SARM gem5 Developers 9110037SARM gem5 Developers def emitHelper(self, base = 'Memory64', wbDecl = None): 9210037SARM gem5 Developers global header_output, decoder_output, exec_output 9310037SARM gem5 Developers 9410037SARM gem5 Developers # If this is a microop itself, don't allow anything that would 9510037SARM gem5 Developers # require further microcoding. 9610037SARM gem5 Developers if self.micro: 9710037SARM gem5 Developers assert not wbDecl 9810037SARM gem5 Developers 9910037SARM gem5 Developers fa_code = None 10010037SARM gem5 Developers if not self.micro and self.flavor in ("normal", "release"): 10110037SARM gem5 Developers fa_code = ''' 10210037SARM gem5 Developers fault->annotate(ArmFault::SAS, %s); 10310037SARM gem5 Developers fault->annotate(ArmFault::SSE, false); 10410037SARM gem5 Developers fault->annotate(ArmFault::SRT, dest); 10510037SARM gem5 Developers fault->annotate(ArmFault::SF, %s); 10610037SARM gem5 Developers fault->annotate(ArmFault::AR, %s); 10710037SARM gem5 Developers ''' % ("0" if self.size == 1 else 10810037SARM gem5 Developers "1" if self.size == 2 else 10910037SARM gem5 Developers "2" if self.size == 4 else "3", 11010037SARM gem5 Developers "true" if self.size == 8 else "false", 11110037SARM gem5 Developers "true" if self.flavor == "release" else "false") 11210037SARM gem5 Developers 11310037SARM gem5 Developers (newHeader, newDecoder, newExec) = \ 11410037SARM gem5 Developers self.fillTemplates(self.name, self.Name, self.codeBlobs, 11510037SARM gem5 Developers self.memFlags, self.instFlags, 11610037SARM gem5 Developers base, wbDecl, faCode=fa_code) 11710037SARM gem5 Developers 11810037SARM gem5 Developers header_output += newHeader 11910037SARM gem5 Developers decoder_output += newDecoder 12010037SARM gem5 Developers exec_output += newExec 12110037SARM gem5 Developers 12210037SARM gem5 Developers def buildEACode(self): 12310037SARM gem5 Developers # Address computation 12410037SARM gem5 Developers eaCode = "" 12510037SARM gem5 Developers if self.flavor == "fp": 12610037SARM gem5 Developers eaCode += vfp64EnabledCheckCode 12710037SARM gem5 Developers 12810037SARM gem5 Developers eaCode += SPAlignmentCheckCode + "EA = XBase" 12910037SARM gem5 Developers if self.size == 16: 13010037SARM gem5 Developers if self.top: 13110037SARM gem5 Developers eaCode += " + (isBigEndian64(xc->tcBase()) ? 0 : 8)" 13210037SARM gem5 Developers else: 13310037SARM gem5 Developers eaCode += " + (isBigEndian64(xc->tcBase()) ? 8 : 0)" 13410037SARM gem5 Developers if not self.post: 13510037SARM gem5 Developers eaCode += self.offset 13610037SARM gem5 Developers eaCode += ";" 13710037SARM gem5 Developers 13810037SARM gem5 Developers self.codeBlobs["ea_code"] = eaCode 13910037SARM gem5 Developers 14010037SARM gem5 Developers 14110037SARM gem5 Developers class StoreImmInst64(StoreInst64): 14210037SARM gem5 Developers def __init__(self, *args, **kargs): 14310037SARM gem5 Developers super(StoreImmInst64, self).__init__(*args, **kargs) 14410037SARM gem5 Developers self.offset = "+ imm" 14510037SARM gem5 Developers 14610037SARM gem5 Developers self.wbDecl = "MicroAddXiUop(machInst, base, base, imm);" 14710037SARM gem5 Developers 14810037SARM gem5 Developers class StoreRegInst64(StoreInst64): 14910037SARM gem5 Developers def __init__(self, *args, **kargs): 15010037SARM gem5 Developers super(StoreRegInst64, self).__init__(*args, **kargs) 15110037SARM gem5 Developers self.offset = "+ extendReg64(XOffset, type, shiftAmt, 64)" 15210037SARM gem5 Developers 15310037SARM gem5 Developers self.wbDecl = \ 15410037SARM gem5 Developers "MicroAddXERegUop(machInst, base, base, " + \ 15510037SARM gem5 Developers " offset, type, shiftAmt);" 15610037SARM gem5 Developers 15710037SARM gem5 Developers class StoreRawRegInst64(StoreInst64): 15810037SARM gem5 Developers def __init__(self, *args, **kargs): 15910037SARM gem5 Developers super(StoreRawRegInst64, self).__init__(*args, **kargs) 16010037SARM gem5 Developers self.offset = "" 16110037SARM gem5 Developers 16210037SARM gem5 Developers class StoreSingle64(StoreInst64): 16310037SARM gem5 Developers def emit(self): 16410037SARM gem5 Developers self.buildEACode() 16510037SARM gem5 Developers 16610037SARM gem5 Developers # Code that actually handles the access 16710037SARM gem5 Developers if self.flavor == "fp": 16810037SARM gem5 Developers if self.size in (1, 2, 4): 16910037SARM gem5 Developers accCode = ''' 17010037SARM gem5 Developers Mem%(suffix)s = 17110037SARM gem5 Developers cSwap(AA64FpDestP0%(suffix)s, isBigEndian64(xc->tcBase())); 17210037SARM gem5 Developers ''' 17310037SARM gem5 Developers elif self.size == 8 or (self.size == 16 and not self.top): 17410037SARM gem5 Developers accCode = ''' 17510037SARM gem5 Developers uint64_t data = AA64FpDestP1_uw; 17610037SARM gem5 Developers data = (data << 32) | AA64FpDestP0_uw; 17710037SARM gem5 Developers Mem%(suffix)s = cSwap(data, isBigEndian64(xc->tcBase())); 17810037SARM gem5 Developers ''' 17910037SARM gem5 Developers elif self.size == 16 and self.top: 18010037SARM gem5 Developers accCode = ''' 18110037SARM gem5 Developers uint64_t data = AA64FpDestP3_uw; 18210037SARM gem5 Developers data = (data << 32) | AA64FpDestP2_uw; 18310037SARM gem5 Developers Mem%(suffix)s = cSwap(data, isBigEndian64(xc->tcBase())); 18410037SARM gem5 Developers ''' 18510037SARM gem5 Developers else: 18610037SARM gem5 Developers accCode = \ 18710037SARM gem5 Developers 'Mem%(suffix)s = cSwap(XDest%(suffix)s, isBigEndian64(xc->tcBase()));' 18810037SARM gem5 Developers if self.size == 16: 18910037SARM gem5 Developers accCode = accCode % \ 19010037SARM gem5 Developers { "suffix" : buildMemSuffix(False, 8) } 19110037SARM gem5 Developers else: 19210037SARM gem5 Developers accCode = accCode % \ 19310037SARM gem5 Developers { "suffix" : buildMemSuffix(False, self.size) } 19410037SARM gem5 Developers 19510037SARM gem5 Developers self.codeBlobs["memacc_code"] = accCode 19610037SARM gem5 Developers 19710037SARM gem5 Developers if self.flavor in ("relex", "exclusive"): 19810037SARM gem5 Developers self.instFlags.append("IsStoreConditional") 19910037SARM gem5 Developers self.memFlags.append("Request::LLSC") 20010037SARM gem5 Developers 20110037SARM gem5 Developers # Push it out to the output files 20210037SARM gem5 Developers wbDecl = None 20310037SARM gem5 Developers if self.writeback and not self.micro: 20410037SARM gem5 Developers wbDecl = self.wbDecl 20510037SARM gem5 Developers self.emitHelper(self.base, wbDecl) 20610037SARM gem5 Developers 20710037SARM gem5 Developers class StoreDouble64(StoreInst64): 20810037SARM gem5 Developers def emit(self): 20910037SARM gem5 Developers self.buildEACode() 21010037SARM gem5 Developers 21110037SARM gem5 Developers # Code that actually handles the access 21210037SARM gem5 Developers if self.flavor == "fp": 21310037SARM gem5 Developers accCode = ''' 21410037SARM gem5 Developers uint64_t data = AA64FpDest2P0_uw; 21510037SARM gem5 Developers data = (data << 32) | AA64FpDestP0_uw; 21610037SARM gem5 Developers Mem_ud = cSwap(data, isBigEndian64(xc->tcBase())); 21710037SARM gem5 Developers ''' 21810037SARM gem5 Developers else: 21910037SARM gem5 Developers if self.size == 4: 22010037SARM gem5 Developers accCode = ''' 22110037SARM gem5 Developers uint64_t data = XDest2_uw; 22210037SARM gem5 Developers data = (data << 32) | XDest_uw; 22310037SARM gem5 Developers Mem_ud = cSwap(data, isBigEndian64(xc->tcBase())); 22410037SARM gem5 Developers ''' 22510037SARM gem5 Developers elif self.size == 8: 22610037SARM gem5 Developers accCode = ''' 22710037SARM gem5 Developers // This temporary needs to be here so that the parser 22810037SARM gem5 Developers // will correctly identify this instruction as a store. 22910037SARM gem5 Developers Twin64_t temp; 23010037SARM gem5 Developers temp.a = XDest_ud; 23110037SARM gem5 Developers temp.b = XDest2_ud; 23210037SARM gem5 Developers Mem_tud = temp; 23310037SARM gem5 Developers ''' 23410037SARM gem5 Developers self.codeBlobs["memacc_code"] = accCode 23510037SARM gem5 Developers 23610037SARM gem5 Developers # Push it out to the output files 23710037SARM gem5 Developers wbDecl = None 23810037SARM gem5 Developers if self.writeback and not self.micro: 23910037SARM gem5 Developers wbDecl = self.wbDecl 24010037SARM gem5 Developers self.emitHelper(self.base, wbDecl) 24110037SARM gem5 Developers 24210037SARM gem5 Developers class StoreImm64(StoreImmInst64, StoreSingle64): 24310037SARM gem5 Developers decConstBase = 'LoadStoreImm64' 24410037SARM gem5 Developers base = 'ArmISA::MemoryImm64' 24510037SARM gem5 Developers writeback = False 24610037SARM gem5 Developers post = False 24710037SARM gem5 Developers 24810037SARM gem5 Developers class StorePre64(StoreImmInst64, StoreSingle64): 24910037SARM gem5 Developers decConstBase = 'LoadStoreImm64' 25010037SARM gem5 Developers base = 'ArmISA::MemoryPreIndex64' 25110037SARM gem5 Developers writeback = True 25210037SARM gem5 Developers post = False 25310037SARM gem5 Developers 25410037SARM gem5 Developers class StorePost64(StoreImmInst64, StoreSingle64): 25510037SARM gem5 Developers decConstBase = 'LoadStoreImm64' 25610037SARM gem5 Developers base = 'ArmISA::MemoryPostIndex64' 25710037SARM gem5 Developers writeback = True 25810037SARM gem5 Developers post = True 25910037SARM gem5 Developers 26010037SARM gem5 Developers class StoreReg64(StoreRegInst64, StoreSingle64): 26110037SARM gem5 Developers decConstBase = 'LoadStoreReg64' 26210037SARM gem5 Developers base = 'ArmISA::MemoryReg64' 26310037SARM gem5 Developers writeback = False 26410037SARM gem5 Developers post = False 26510037SARM gem5 Developers 26610037SARM gem5 Developers class StoreRaw64(StoreRawRegInst64, StoreSingle64): 26710037SARM gem5 Developers decConstBase = 'LoadStoreRaw64' 26810037SARM gem5 Developers base = 'ArmISA::MemoryRaw64' 26910037SARM gem5 Developers writeback = False 27010037SARM gem5 Developers post = False 27110037SARM gem5 Developers 27210037SARM gem5 Developers class StoreEx64(StoreRawRegInst64, StoreSingle64): 27310037SARM gem5 Developers decConstBase = 'LoadStoreEx64' 27410037SARM gem5 Developers base = 'ArmISA::MemoryEx64' 27510037SARM gem5 Developers writeback = False 27610037SARM gem5 Developers post = False 27710037SARM gem5 Developers execBase = 'StoreEx64' 27810037SARM gem5 Developers def __init__(self, *args, **kargs): 27910037SARM gem5 Developers super(StoreEx64, self).__init__(*args, **kargs) 28012219Snikos.nikoleris@arm.com self.codeBlobs["postacc_code"] = \ 28112219Snikos.nikoleris@arm.com "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" 28210037SARM gem5 Developers 28310037SARM gem5 Developers def buildStores64(mnem, NameBase, size, flavor="normal"): 28410037SARM gem5 Developers StoreImm64(mnem, NameBase + "_IMM", size, flavor=flavor).emit() 28510037SARM gem5 Developers StorePre64(mnem, NameBase + "_PRE", size, flavor=flavor).emit() 28610037SARM gem5 Developers StorePost64(mnem, NameBase + "_POST", size, flavor=flavor).emit() 28710037SARM gem5 Developers StoreReg64(mnem, NameBase + "_REG", size, flavor=flavor).emit() 28810037SARM gem5 Developers 28910037SARM gem5 Developers buildStores64("strb", "STRB64", 1) 29010037SARM gem5 Developers buildStores64("strh", "STRH64", 2) 29110037SARM gem5 Developers buildStores64("str", "STRW64", 4) 29210037SARM gem5 Developers buildStores64("str", "STRX64", 8) 29310037SARM gem5 Developers buildStores64("str", "STRBFP64", 1, flavor="fp") 29410037SARM gem5 Developers buildStores64("str", "STRHFP64", 2, flavor="fp") 29510037SARM gem5 Developers buildStores64("str", "STRSFP64", 4, flavor="fp") 29610037SARM gem5 Developers buildStores64("str", "STRDFP64", 8, flavor="fp") 29710037SARM gem5 Developers 29810037SARM gem5 Developers StoreImm64("sturb", "STURB64_IMM", 1).emit() 29910037SARM gem5 Developers StoreImm64("sturh", "STURH64_IMM", 2).emit() 30010037SARM gem5 Developers StoreImm64("stur", "STURW64_IMM", 4).emit() 30110037SARM gem5 Developers StoreImm64("stur", "STURX64_IMM", 8).emit() 30210037SARM gem5 Developers StoreImm64("stur", "STURBFP64_IMM", 1, flavor="fp").emit() 30310037SARM gem5 Developers StoreImm64("stur", "STURHFP64_IMM", 2, flavor="fp").emit() 30410037SARM gem5 Developers StoreImm64("stur", "STURSFP64_IMM", 4, flavor="fp").emit() 30510037SARM gem5 Developers StoreImm64("stur", "STURDFP64_IMM", 8, flavor="fp").emit() 30610037SARM gem5 Developers 30710037SARM gem5 Developers StoreImm64("sttrb", "STTRB64_IMM", 1, user=True).emit() 30810037SARM gem5 Developers StoreImm64("sttrh", "STTRH64_IMM", 2, user=True).emit() 30910037SARM gem5 Developers StoreImm64("sttr", "STTRW64_IMM", 4, user=True).emit() 31010037SARM gem5 Developers StoreImm64("sttr", "STTRX64_IMM", 8, user=True).emit() 31110037SARM gem5 Developers 31210037SARM gem5 Developers StoreRaw64("stlr", "STLRX64", 8, flavor="release").emit() 31310037SARM gem5 Developers StoreRaw64("stlr", "STLRW64", 4, flavor="release").emit() 31410037SARM gem5 Developers StoreRaw64("stlrh", "STLRH64", 2, flavor="release").emit() 31510037SARM gem5 Developers StoreRaw64("stlrb", "STLRB64", 1, flavor="release").emit() 31610037SARM gem5 Developers 31710037SARM gem5 Developers StoreEx64("stlxr", "STLXRX64", 8, flavor="relex").emit() 31810037SARM gem5 Developers StoreEx64("stlxr", "STLXRW64", 4, flavor="relex").emit() 31910037SARM gem5 Developers StoreEx64("stlxrh", "STLXRH64", 2, flavor="relex").emit() 32010037SARM gem5 Developers StoreEx64("stlxrb", "STLXRB64", 1, flavor="relex").emit() 32110037SARM gem5 Developers 32210037SARM gem5 Developers StoreEx64("stxr", "STXRX64", 8, flavor="exclusive").emit() 32310037SARM gem5 Developers StoreEx64("stxr", "STXRW64", 4, flavor="exclusive").emit() 32410037SARM gem5 Developers StoreEx64("stxrh", "STXRH64", 2, flavor="exclusive").emit() 32510037SARM gem5 Developers StoreEx64("stxrb", "STXRB64", 1, flavor="exclusive").emit() 32610037SARM gem5 Developers 32710037SARM gem5 Developers class StoreImmU64(StoreImm64): 32810037SARM gem5 Developers decConstBase = 'LoadStoreImmU64' 32910037SARM gem5 Developers micro = True 33010037SARM gem5 Developers 33110037SARM gem5 Developers class StoreImmDU64(StoreImmInst64, StoreDouble64): 33210037SARM gem5 Developers decConstBase = 'LoadStoreImmDU64' 33310037SARM gem5 Developers base = 'ArmISA::MemoryDImm64' 33410037SARM gem5 Developers micro = True 33510037SARM gem5 Developers post = False 33610037SARM gem5 Developers writeback = False 33710037SARM gem5 Developers 33810037SARM gem5 Developers class StoreImmDEx64(StoreImmInst64, StoreDouble64): 33910037SARM gem5 Developers execBase = 'StoreEx64' 34010037SARM gem5 Developers decConstBase = 'StoreImmDEx64' 34110037SARM gem5 Developers base = 'ArmISA::MemoryDImmEx64' 34210037SARM gem5 Developers micro = False 34310037SARM gem5 Developers post = False 34410037SARM gem5 Developers writeback = False 34510037SARM gem5 Developers def __init__(self, *args, **kargs): 34610037SARM gem5 Developers super(StoreImmDEx64, self).__init__(*args, **kargs) 34712219Snikos.nikoleris@arm.com self.codeBlobs["postacc_code"] = \ 34812219Snikos.nikoleris@arm.com "XResult = !writeResult; SevMailbox = 1; LLSCLock = 0;" 34910037SARM gem5 Developers 35010037SARM gem5 Developers class StoreRegU64(StoreReg64): 35110037SARM gem5 Developers decConstBase = 'LoadStoreRegU64' 35210037SARM gem5 Developers micro = True 35310037SARM gem5 Developers 35410037SARM gem5 Developers StoreImmDEx64("stlxp", "STLXPW64", 4, flavor="relexp").emit() 35510037SARM gem5 Developers StoreImmDEx64("stlxp", "STLXPX64", 8, flavor="relexp").emit() 35610037SARM gem5 Developers StoreImmDEx64("stxp", "STXPW64", 4, flavor="exp").emit() 35710037SARM gem5 Developers StoreImmDEx64("stxp", "STXPX64", 8, flavor="exp").emit() 35810037SARM gem5 Developers 35910037SARM gem5 Developers StoreImmU64("strxi_uop", "MicroStrXImmUop", 8).emit() 36010037SARM gem5 Developers StoreRegU64("strxr_uop", "MicroStrXRegUop", 8).emit() 36110037SARM gem5 Developers StoreImmU64("strfpxi_uop", "MicroStrFpXImmUop", 8, flavor="fp").emit() 36210037SARM gem5 Developers StoreRegU64("strfpxr_uop", "MicroStrFpXRegUop", 8, flavor="fp").emit() 36310037SARM gem5 Developers StoreImmU64("strqbfpxi_uop", "MicroStrQBFpXImmUop", 36410037SARM gem5 Developers 16, flavor="fp", top=False).emit() 36510037SARM gem5 Developers StoreRegU64("strqbfpxr_uop", "MicroStrQBFpXRegUop", 36610037SARM gem5 Developers 16, flavor="fp", top=False).emit() 36710037SARM gem5 Developers StoreImmU64("strqtfpxi_uop", "MicroStrQTFpXImmUop", 36810037SARM gem5 Developers 16, flavor="fp", top=True).emit() 36910037SARM gem5 Developers StoreRegU64("strqtfpxr_uop", "MicroStrQTFpXRegUop", 37010037SARM gem5 Developers 16, flavor="fp", top=True).emit() 37110037SARM gem5 Developers StoreImmDU64("strdxi_uop", "MicroStrDXImmUop", 4).emit() 37210037SARM gem5 Developers StoreImmDU64("strdfpxi_uop", "MicroStrDFpXImmUop", 4, flavor="fp").emit() 37310037SARM gem5 Developers 37410037SARM gem5 Developers}}; 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