str.isa revision 7294 
12381SN/A// -*- mode:c++ -*-
22381SN/A
32381SN/A// Copyright (c) 2010 ARM Limited
42381SN/A// All rights reserved
52381SN/A//
62381SN/A// The license below extends only to copyright in the software and shall
72381SN/A// not be construed as granting a license to any other intellectual
82381SN/A// property including but not limited to intellectual property relating
92381SN/A// to a hardware implementation of the functionality of the software
102381SN/A// licensed hereunder.  You may use the software subject to the license
112381SN/A// terms below provided that you ensure that this notice is replicated
122381SN/A// unmodified and in its entirety in all distributions of the software,
132381SN/A// modified or unmodified, in source code or in binary form.
142381SN/A//
152381SN/A// Redistribution and use in source and binary forms, with or without
162381SN/A// modification, are permitted provided that the following conditions are
172381SN/A// met: redistributions of source code must retain the above copyright
182381SN/A// notice, this list of conditions and the following disclaimer;
192381SN/A// redistributions in binary form must reproduce the above copyright
202381SN/A// notice, this list of conditions and the following disclaimer in the
212381SN/A// documentation and/or other materials provided with the distribution;
222381SN/A// neither the name of the copyright holders nor the names of its
232381SN/A// contributors may be used to endorse or promote products derived from
242381SN/A// this software without specific prior written permission.
252381SN/A//
262381SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
272665Ssaidi@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
282665Ssaidi@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
292381SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
302381SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
312381SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
322381SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
332381SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
342381SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
352381SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
362381SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
372381SN/A//
382381SN/A// Authors: Gabe Black
392381SN/A
402383SN/Alet {{
412381SN/A
422381SN/A    header_output = ""
432381SN/A    decoder_output = ""
442381SN/A    exec_output = ""
452381SN/A
462394SN/A    def storeImmClassName(post, add, writeback, \
472381SN/A                          size=4, sign=False, user=False):
482381SN/A        return memClassName("STORE_IMM", post, add, writeback,
492463SN/A                            size, sign, user)
502394SN/A
512394SN/A    def storeRegClassName(post, add, writeback, \
522381SN/A                          size=4, sign=False, user=False):
532499SN/A        return memClassName("STORE_REG", post, add, writeback,
542381SN/A                            size, sign, user)
552381SN/A
562381SN/A    def storeDoubleImmClassName(post, add, writeback):
57        return memClassName("STORE_IMMD", post, add, writeback,
58                            4, False, False)
59
60    def storeDoubleRegClassName(post, add, writeback):
61        return memClassName("STORE_REGD", post, add, writeback,
62                            4, False, False)
63
64    def emitStore(name, Name, imm, eaCode, accCode, \
65                  memFlags, instFlags, base, double=False):
66        global header_output, decoder_output, exec_output
67
68        (newHeader,
69         newDecoder,
70         newExec) = loadStoreBase(name, Name, imm,
71                                  eaCode, accCode,
72                                  memFlags, instFlags, double,
73                                  base, execTemplateBase = 'Store')
74
75        header_output += newHeader
76        decoder_output += newDecoder
77        exec_output += newExec
78
79    def buildImmStore(mnem, post, add, writeback, \
80                      size=4, sign=False, user=False):
81        name = mnem
82        Name = storeImmClassName(post, add, writeback, \
83                                 size, sign, user)
84
85        if add:
86            op = " +"
87        else:
88            op = " -"
89
90        offset = op + " imm"
91        eaCode = "EA = Base"
92        if not post:
93            eaCode += offset
94        eaCode += ";"
95
96        accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
97        if writeback:
98            accCode += "Base = Base %s;\n" % offset
99        base = buildMemBase("MemoryImm", post, writeback)
100
101        emitStore(name, Name, True, eaCode, accCode, \
102                ["ArmISA::TLB::MustBeOne", \
103                 "ArmISA::TLB::AllowUnaligned", \
104                 "%d" % (size - 1)], [], base)
105
106    def buildRegStore(mnem, post, add, writeback, \
107                      size=4, sign=False, user=False):
108        name = mnem
109        Name = storeRegClassName(post, add, writeback,
110                                 size, sign, user)
111
112        if add:
113            op = " +"
114        else:
115            op = " -"
116
117        offset = op + " shift_rm_imm(Index, shiftAmt," + \
118                      " shiftType, CondCodes<29:>)"
119        eaCode = "EA = Base"
120        if not post:
121            eaCode += offset
122        eaCode += ";"
123
124        accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
125        if writeback:
126            accCode += "Base = Base %s;\n" % offset
127        base = buildMemBase("MemoryReg", post, writeback)
128
129        emitStore(name, Name, False, eaCode, accCode, \
130                ["ArmISA::TLB::MustBeOne", \
131                 "ArmISA::TLB::AllowUnaligned", \
132                 "%d" % (size - 1)], [], base)
133
134    def buildDoubleImmStore(mnem, post, add, writeback):
135        name = mnem
136        Name = storeDoubleImmClassName(post, add, writeback)
137
138        if add:
139            op = " +"
140        else:
141            op = " -"
142
143        offset = op + " imm"
144        eaCode = "EA = Base"
145        if not post:
146            eaCode += offset
147        eaCode += ";"
148
149        accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
150        if writeback:
151            accCode += "Base = Base %s;\n" % offset
152        base = buildMemBase("MemoryDImm", post, writeback)
153
154        emitStore(name, Name, True, eaCode, accCode, \
155                ["ArmISA::TLB::MustBeOne",
156                 "ArmISA::TLB::AlignWord"], [], base, double=True)
157
158    def buildDoubleRegStore(mnem, post, add, writeback):
159        name = mnem
160        Name = storeDoubleRegClassName(post, add, writeback)
161
162        if add:
163            op = " +"
164        else:
165            op = " -"
166
167        offset = op + " shift_rm_imm(Index, shiftAmt," + \
168                      " shiftType, CondCodes<29:>)"
169        eaCode = "EA = Base"
170        if not post:
171            eaCode += offset
172        eaCode += ";"
173
174        accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
175        if writeback:
176            accCode += "Base = Base %s;\n" % offset
177        base = buildMemBase("MemoryDReg", post, writeback)
178
179        emitStore(name, Name, False, eaCode, accCode, \
180                ["ArmISA::TLB::MustBeOne", \
181                 "ArmISA::TLB::AlignWord"], [], base, double=True)
182
183    def buildStores(mnem, size=4, sign=False, user=False):
184        buildImmStore(mnem, True, True, True, size, sign, user)
185        buildRegStore(mnem, True, True, True, size, sign, user)
186        buildImmStore(mnem, True, False, True, size, sign, user)
187        buildRegStore(mnem, True, False, True, size, sign, user)
188        buildImmStore(mnem, False, True, True, size, sign, user)
189        buildRegStore(mnem, False, True, True, size, sign, user)
190        buildImmStore(mnem, False, False, True, size, sign, user)
191        buildRegStore(mnem, False, False, True, size, sign, user)
192        buildImmStore(mnem, False, True, False, size, sign, user)
193        buildRegStore(mnem, False, True, False, size, sign, user)
194        buildImmStore(mnem, False, False, False, size, sign, user)
195        buildRegStore(mnem, False, False, False, size, sign, user)
196
197    def buildDoubleStores(mnem):
198        buildDoubleImmStore(mnem, True, True, True)
199        buildDoubleRegStore(mnem, True, True, True)
200        buildDoubleImmStore(mnem, True, False, True)
201        buildDoubleRegStore(mnem, True, False, True)
202        buildDoubleImmStore(mnem, False, True, True)
203        buildDoubleRegStore(mnem, False, True, True)
204        buildDoubleImmStore(mnem, False, False, True)
205        buildDoubleRegStore(mnem, False, False, True)
206        buildDoubleImmStore(mnem, False, True, False)
207        buildDoubleRegStore(mnem, False, True, False)
208        buildDoubleImmStore(mnem, False, False, False)
209        buildDoubleRegStore(mnem, False, False, False)
210
211    buildStores("str")
212    buildStores("strt", user=True)
213    buildStores("strb", size=1)
214    buildStores("strbt", size=1, user=True)
215    buildStores("strh", size=2)
216    buildStores("strht", size=2, user=True)
217
218    buildDoubleStores("strd")
219}};
220