str.isa revision 7279:157b02cc0ba1
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 def storeImmClassName(post, add, writeback, \ 47 size=4, sign=False, user=False): 48 return memClassName("STORE_IMM", post, add, writeback, 49 size, sign, user) 50 51 def storeRegClassName(post, add, writeback, \ 52 size=4, sign=False, user=False): 53 return memClassName("STORE_REG", post, add, writeback, 54 size, sign, user) 55 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 64 def emitStore(name, Name, imm, eaCode, accCode, \ 65 memFlags, instFlags, base, double=False): 66 global header_output, decoder_output, exec_output 67 68 (newHeader, 69 newDecoder, 70 newExec) = loadStoreBase(name, Name, imm, 71 eaCode, accCode, 72 memFlags, instFlags, double, 73 base, execTemplateBase = 'Store') 74 75 header_output += newHeader 76 decoder_output += newDecoder 77 exec_output += newExec 78 79 def buildImmStore(mnem, post, add, writeback, \ 80 size=4, sign=False, user=False): 81 name = mnem 82 Name = storeImmClassName(post, add, writeback, \ 83 size, sign, user) 84 85 if add: 86 op = " +" 87 else: 88 op = " -" 89 90 offset = op + " imm" 91 eaCode = "EA = Base" 92 if not post: 93 eaCode += offset 94 eaCode += ";" 95 96 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 97 if writeback: 98 accCode += "Base = Base %s;\n" % offset 99 base = buildMemBase("MemoryImm", post, writeback) 100 101 emitStore(name, Name, True, eaCode, accCode, [], [], base) 102 103 def buildRegStore(mnem, post, add, writeback, \ 104 size=4, sign=False, user=False): 105 name = mnem 106 Name = storeRegClassName(post, add, writeback, 107 size, sign, user) 108 109 if add: 110 op = " +" 111 else: 112 op = " -" 113 114 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 115 " shiftType, CondCodes<29:>)" 116 eaCode = "EA = Base" 117 if not post: 118 eaCode += offset 119 eaCode += ";" 120 121 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 122 if writeback: 123 accCode += "Base = Base %s;\n" % offset 124 base = buildMemBase("MemoryReg", post, writeback) 125 126 emitStore(name, Name, False, eaCode, accCode, [], [], base) 127 128 def buildDoubleImmStore(mnem, post, add, writeback): 129 name = mnem 130 Name = storeDoubleImmClassName(post, add, writeback) 131 132 if add: 133 op = " +" 134 else: 135 op = " -" 136 137 offset = op + " imm" 138 eaCode = "EA = Base" 139 if not post: 140 eaCode += offset 141 eaCode += ";" 142 143 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' 144 if writeback: 145 accCode += "Base = Base %s;\n" % offset 146 base = buildMemBase("MemoryDImm", post, writeback) 147 148 emitStore(name, Name, True, eaCode, accCode, \ 149 [], [], base, double=True) 150 151 def buildDoubleRegStore(mnem, post, add, writeback): 152 name = mnem 153 Name = storeDoubleRegClassName(post, add, writeback) 154 155 if add: 156 op = " +" 157 else: 158 op = " -" 159 160 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 161 " shiftType, CondCodes<29:>)" 162 eaCode = "EA = Base" 163 if not post: 164 eaCode += offset 165 eaCode += ";" 166 167 accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' 168 if writeback: 169 accCode += "Base = Base %s;\n" % offset 170 base = buildMemBase("MemoryDReg", post, writeback) 171 172 emitStore(name, Name, False, eaCode, accCode, \ 173 [], [], base, double=True) 174 175 def buildStores(mnem, size=4, sign=False, user=False): 176 buildImmStore(mnem, True, True, True, size, sign, user) 177 buildRegStore(mnem, True, True, True, size, sign, user) 178 buildImmStore(mnem, True, False, True, size, sign, user) 179 buildRegStore(mnem, True, False, True, size, sign, user) 180 buildImmStore(mnem, False, True, True, size, sign, user) 181 buildRegStore(mnem, False, True, True, size, sign, user) 182 buildImmStore(mnem, False, False, True, size, sign, user) 183 buildRegStore(mnem, False, False, True, size, sign, user) 184 buildImmStore(mnem, False, True, False, size, sign, user) 185 buildRegStore(mnem, False, True, False, size, sign, user) 186 buildImmStore(mnem, False, False, False, size, sign, user) 187 buildRegStore(mnem, False, False, False, size, sign, user) 188 189 def buildDoubleStores(mnem): 190 buildDoubleImmStore(mnem, True, True, True) 191 buildDoubleRegStore(mnem, True, True, True) 192 buildDoubleImmStore(mnem, True, False, True) 193 buildDoubleRegStore(mnem, True, False, True) 194 buildDoubleImmStore(mnem, False, True, True) 195 buildDoubleRegStore(mnem, False, True, True) 196 buildDoubleImmStore(mnem, False, False, True) 197 buildDoubleRegStore(mnem, False, False, True) 198 buildDoubleImmStore(mnem, False, True, False) 199 buildDoubleRegStore(mnem, False, True, False) 200 buildDoubleImmStore(mnem, False, False, False) 201 buildDoubleRegStore(mnem, False, False, False) 202 203 buildStores("str") 204 buildStores("strt", user=True) 205 buildStores("strb", size=1) 206 buildStores("strbt", size=1, user=True) 207 buildStores("strh", size=2) 208 buildStores("strht", size=2, user=True) 209 210 buildDoubleStores("strd") 211}}; 212