str.isa revision 7132:83b433d6e600
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 def storeImmClassName(post, add, writeback, \ 47 size=4, sign=False, user=False): 48 return memClassName("STORE_IMM", post, add, writeback, 49 size, sign, user) 50 51 def storeRegClassName(post, add, writeback, \ 52 size=4, sign=False, user=False): 53 return memClassName("STORE_REG", post, add, writeback, 54 size, sign, user) 55 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 64 def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base): 65 global header_output, decoder_output, exec_output 66 67 (newHeader, 68 newDecoder, 69 newExec) = loadStoreBase(name, Name, imm, 70 eaCode, accCode, 71 memFlags, instFlags, 72 base, execTemplateBase = 'Store') 73 74 header_output += newHeader 75 decoder_output += newDecoder 76 exec_output += newExec 77 78 def buildImmStore(mnem, post, add, writeback, \ 79 size=4, sign=False, user=False): 80 name = mnem 81 Name = storeImmClassName(post, add, writeback, \ 82 size, sign, user) 83 84 if add: 85 op = " +" 86 else: 87 op = " -" 88 89 offset = op + " imm" 90 eaCode = "EA = Base" 91 if not post: 92 eaCode += offset 93 eaCode += ";" 94 95 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 96 if writeback: 97 accCode += "Base = Base %s;\n" % offset 98 base = buildMemBase("MemoryImm", post, writeback) 99 100 emitStore(name, Name, True, eaCode, accCode, [], [], base) 101 102 def buildRegStore(mnem, post, add, writeback, \ 103 size=4, sign=False, user=False): 104 name = mnem 105 Name = storeRegClassName(post, add, writeback, 106 size, sign, user) 107 108 if add: 109 op = " +" 110 else: 111 op = " -" 112 113 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 114 " shiftType, CondCodes<29:>)" 115 eaCode = "EA = Base" 116 if not post: 117 eaCode += offset 118 eaCode += ";" 119 120 accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size) 121 if writeback: 122 accCode += "Base = Base %s;\n" % offset 123 base = buildMemBase("MemoryReg", post, writeback) 124 125 emitStore(name, Name, False, eaCode, accCode, [], [], base) 126 127 def buildDoubleImmStore(mnem, post, add, writeback): 128 name = mnem 129 Name = storeDoubleImmClassName(post, add, writeback) 130 131 if add: 132 op = " +" 133 else: 134 op = " -" 135 136 offset = op + " imm" 137 eaCode = "EA = Base" 138 if not post: 139 eaCode += offset 140 eaCode += ";" 141 142 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' 143 if writeback: 144 accCode += "Base = Base %s;\n" % offset 145 base = buildMemBase("MemoryImm", post, writeback) 146 147 emitStore(name, Name, True, eaCode, accCode, [], [], base) 148 149 def buildDoubleRegStore(mnem, post, add, writeback): 150 name = mnem 151 Name = storeDoubleRegClassName(post, add, writeback) 152 153 if add: 154 op = " +" 155 else: 156 op = " -" 157 158 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 159 " shiftType, CondCodes<29:>)" 160 eaCode = "EA = Base" 161 if not post: 162 eaCode += offset 163 eaCode += ";" 164 165 accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' 166 if writeback: 167 accCode += "Base = Base %s;\n" % offset 168 base = buildMemBase("MemoryReg", post, writeback) 169 170 emitStore(name, Name, False, eaCode, accCode, [], [], base) 171 172 def buildStores(mnem, size=4, sign=False, user=False): 173 buildImmStore(mnem, True, True, True, size, sign, user) 174 buildRegStore(mnem, True, True, True, size, sign, user) 175 buildImmStore(mnem, True, False, True, size, sign, user) 176 buildRegStore(mnem, True, False, True, size, sign, user) 177 buildImmStore(mnem, False, True, True, size, sign, user) 178 buildRegStore(mnem, False, True, True, size, sign, user) 179 buildImmStore(mnem, False, False, True, size, sign, user) 180 buildRegStore(mnem, False, False, True, size, sign, user) 181 buildImmStore(mnem, False, True, False, size, sign, user) 182 buildRegStore(mnem, False, True, False, size, sign, user) 183 buildImmStore(mnem, False, False, False, size, sign, user) 184 buildRegStore(mnem, False, False, False, size, sign, user) 185 186 def buildDoubleStores(mnem): 187 buildDoubleImmStore(mnem, True, True, True) 188 buildDoubleRegStore(mnem, True, True, True) 189 buildDoubleImmStore(mnem, True, False, True) 190 buildDoubleRegStore(mnem, True, False, True) 191 buildDoubleImmStore(mnem, False, True, True) 192 buildDoubleRegStore(mnem, False, True, True) 193 buildDoubleImmStore(mnem, False, False, True) 194 buildDoubleRegStore(mnem, False, False, True) 195 buildDoubleImmStore(mnem, False, True, False) 196 buildDoubleRegStore(mnem, False, True, False) 197 buildDoubleImmStore(mnem, False, False, False) 198 buildDoubleRegStore(mnem, False, False, False) 199 200 buildStores("str") 201 buildStores("strt", user=True) 202 buildStores("strb", size=1) 203 buildStores("strbt", size=1, user=True) 204 buildStores("strh", size=2) 205 buildStores("strht", size=2, user=True) 206 207 buildDoubleStores("strd") 208}}; 209