str.isa revision 7120:d630089169f3 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    def storeImmClassName(post, add, writeback, \
47                          size=4, sign=False, user=False):
48        return memClassName("STORE_IMM", post, add, writeback,
49                            size, sign, user)
50
51    def storeRegClassName(post, add, writeback, \
52                          size=4, sign=False, user=False):
53        return memClassName("STORE_REG", post, add, writeback,
54                            size, sign, user)
55
56    def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
57        global header_output, decoder_output, exec_output
58
59        (newHeader,
60         newDecoder,
61         newExec) = newLoadStoreBase(name, Name, imm,
62                                     eaCode, accCode,
63                                     memFlags, instFlags,
64                                     base, execTemplateBase = 'Store')
65
66        header_output += newHeader
67        decoder_output += newDecoder
68        exec_output += newExec
69
70    def buildImmStore(mnem, post, add, writeback, \
71                      size=4, sign=False, user=False):
72        name = mnem
73        Name = storeImmClassName(post, add, writeback, \
74                                 size, sign, user)
75
76        if add:
77            op = " +"
78        else:
79            op = " -"
80
81        offset = op + " imm"
82        eaCode = "EA = Base"
83        if not post:
84            eaCode += offset
85        eaCode += ";"
86
87        accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
88        if writeback:
89            accCode += "Base = Base %s;\n" % offset
90        base = buildMemBase("MemoryNewImm", post, writeback)
91
92        emitStore(name, Name, True, eaCode, accCode, [], [], base)
93
94    def buildRegStore(mnem, post, add, writeback, \
95                      size=4, sign=False, user=False):
96        name = mnem
97        Name = storeRegClassName(post, add, writeback,
98                                 size, sign, user)
99
100        if add:
101            op = " +"
102        else:
103            op = " -"
104
105        offset = op + " shift_rm_imm(Index, shiftAmt," + \
106                      " shiftType, CondCodes<29:>)"
107        eaCode = "EA = Base"
108        if not post:
109            eaCode += offset
110        eaCode += ";"
111
112        accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
113        if writeback:
114            accCode += "Base = Base %s;\n" % offset
115        base = buildMemBase("MemoryNewReg", post, writeback)
116
117        emitStore(name, Name, False, eaCode, accCode, [], [], base)
118
119    def buildStores(mnem, size=4, sign=False, user=False):
120        buildImmStore(mnem, True, True, True, size, sign, user)
121        buildRegStore(mnem, True, True, True, size, sign, user)
122        buildImmStore(mnem, True, False, True, size, sign, user)
123        buildRegStore(mnem, True, False, True, size, sign, user)
124        buildImmStore(mnem, False, True, True, size, sign, user)
125        buildRegStore(mnem, False, True, True, size, sign, user)
126        buildImmStore(mnem, False, False, True, size, sign, user)
127        buildRegStore(mnem, False, False, True, size, sign, user)
128        buildImmStore(mnem, False, True, False, size, sign, user)
129        buildRegStore(mnem, False, True, False, size, sign, user)
130        buildImmStore(mnem, False, False, False, size, sign, user)
131        buildRegStore(mnem, False, False, False, size, sign, user)
132
133    buildStores("str")
134    buildStores("strt", user=True)
135    buildStores("strb", size=1)
136    buildStores("strbt", size=1, user=True)
137    buildStores("strh", size=2)
138    buildStores("strht", size=2, user=True)
139}};
140