misc.isa revision 8303 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    svcCode = '''
43#if FULL_SYSTEM
44    fault = new SupervisorCall;
45#else
46    fault = new SupervisorCall(machInst);
47#endif
48    '''
49
50    svcIop = InstObjParams("svc", "Svc", "PredOp",
51                           { "code": svcCode,
52                             "predicate_test": predicateTest }, ["IsSyscall"])
53    header_output = BasicDeclare.subst(svcIop)
54    decoder_output = BasicConstructor.subst(svcIop)
55    exec_output = PredOpExecute.subst(svcIop)
56
57}};
58
59let {{
60
61    header_output = decoder_output = exec_output = ""
62
63    mrsCpsrCode = '''
64        CPSR cpsr = Cpsr;
65        cpsr.nz = CondCodesNZ;
66        cpsr.c = CondCodesC;
67        cpsr.v = CondCodesV;
68        cpsr.ge = CondCodesGE;
69        Dest = cpsr & 0xF8FF03DF
70    '''
71
72    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
73                               { "code": mrsCpsrCode,
74                                 "predicate_test": condPredicateTest },
75                               ["IsSerializeBefore"])
76    header_output += MrsDeclare.subst(mrsCpsrIop)
77    decoder_output += MrsConstructor.subst(mrsCpsrIop)
78    exec_output += PredOpExecute.subst(mrsCpsrIop)
79
80    mrsSpsrCode = "Dest = Spsr"
81    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
82                               { "code": mrsSpsrCode,
83                                 "predicate_test": predicateTest },
84                               ["IsSerializeBefore"])
85    header_output += MrsDeclare.subst(mrsSpsrIop)
86    decoder_output += MrsConstructor.subst(mrsSpsrIop)
87    exec_output += PredOpExecute.subst(mrsSpsrIop)
88
89    msrCpsrRegCode = '''
90        SCTLR sctlr = Sctlr;
91        CPSR old_cpsr = Cpsr;
92        old_cpsr.nz = CondCodesNZ;
93        old_cpsr.c = CondCodesC;
94        old_cpsr.v = CondCodesV;
95        old_cpsr.ge = CondCodesGE;
96
97        CPSR new_cpsr =
98            cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
99        Cpsr = ~CondCodesMask & new_cpsr;
100        CondCodesNZ = new_cpsr.nz;
101        CondCodesC = new_cpsr.c;
102        CondCodesV = new_cpsr.v;
103        CondCodesGE = new_cpsr.ge;
104    '''
105    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
106                                  { "code": msrCpsrRegCode,
107                                    "predicate_test": condPredicateTest },
108                                  ["IsSerializeAfter","IsNonSpeculative"])
109    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
110    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
111    exec_output += PredOpExecute.subst(msrCpsrRegIop)
112
113    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
114    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
115                                  { "code": msrSpsrRegCode,
116                                    "predicate_test": predicateTest },
117                                  ["IsSerializeAfter","IsNonSpeculative"])
118    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
119    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
120    exec_output += PredOpExecute.subst(msrSpsrRegIop)
121
122    msrCpsrImmCode = '''
123        SCTLR sctlr = Sctlr;
124        CPSR old_cpsr = Cpsr;
125        old_cpsr.nz = CondCodesNZ;
126        old_cpsr.c = CondCodesC;
127        old_cpsr.v = CondCodesV;
128        old_cpsr.ge = CondCodesGE;
129        CPSR new_cpsr =
130            cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
131        Cpsr = ~CondCodesMask & new_cpsr;
132        CondCodesNZ = new_cpsr.nz;
133        CondCodesC = new_cpsr.c;
134        CondCodesV = new_cpsr.v;
135        CondCodesGE = new_cpsr.ge;
136    '''
137    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
138                                  { "code": msrCpsrImmCode,
139                                    "predicate_test": condPredicateTest },
140                                  ["IsSerializeAfter","IsNonSpeculative"])
141    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
142    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
143    exec_output += PredOpExecute.subst(msrCpsrImmIop)
144
145    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
146    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
147                                  { "code": msrSpsrImmCode,
148                                    "predicate_test": predicateTest },
149                                  ["IsSerializeAfter","IsNonSpeculative"])
150    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
151    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
152    exec_output += PredOpExecute.subst(msrSpsrImmIop)
153
154    revCode = '''
155    uint32_t val = Op1;
156    Dest = swap_byte(val);
157    '''
158    revIop = InstObjParams("rev", "Rev", "RegRegOp",
159                           { "code": revCode,
160                             "predicate_test": predicateTest }, [])
161    header_output += RegRegOpDeclare.subst(revIop)
162    decoder_output += RegRegOpConstructor.subst(revIop)
163    exec_output += PredOpExecute.subst(revIop)
164
165    rev16Code = '''
166    uint32_t val = Op1;
167    Dest = (bits(val, 15, 8) << 0) |
168           (bits(val, 7, 0) << 8) |
169           (bits(val, 31, 24) << 16) |
170           (bits(val, 23, 16) << 24);
171    '''
172    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
173                             { "code": rev16Code,
174                               "predicate_test": predicateTest }, [])
175    header_output += RegRegOpDeclare.subst(rev16Iop)
176    decoder_output += RegRegOpConstructor.subst(rev16Iop)
177    exec_output += PredOpExecute.subst(rev16Iop)
178
179    revshCode = '''
180    uint16_t val = Op1;
181    Dest = sext<16>(swap_byte(val));
182    '''
183    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
184                             { "code": revshCode,
185                               "predicate_test": predicateTest }, [])
186    header_output += RegRegOpDeclare.subst(revshIop)
187    decoder_output += RegRegOpConstructor.subst(revshIop)
188    exec_output += PredOpExecute.subst(revshIop)
189
190    rbitCode = '''
191    uint8_t *opBytes = (uint8_t *)&Op1;
192    uint32_t resTemp;
193    uint8_t *destBytes = (uint8_t *)&resTemp;
194    // This reverses the bytes and bits of the input, or so says the
195    // internet.
196    for (int i = 0; i < 4; i++) {
197        uint32_t temp = opBytes[i];
198        temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
199        destBytes[3 - i] = (temp * 0x10101) >> 16;
200    }
201    Dest = resTemp;
202    '''
203    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
204                            { "code": rbitCode,
205                              "predicate_test": predicateTest }, [])
206    header_output += RegRegOpDeclare.subst(rbitIop)
207    decoder_output += RegRegOpConstructor.subst(rbitIop)
208    exec_output += PredOpExecute.subst(rbitIop)
209
210    clzCode = '''
211        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
212    '''
213    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
214                           { "code": clzCode,
215                             "predicate_test": predicateTest }, [])
216    header_output += RegRegOpDeclare.subst(clzIop)
217    decoder_output += RegRegOpConstructor.subst(clzIop)
218    exec_output += PredOpExecute.subst(clzIop)
219
220    ssatCode = '''
221        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
222        int32_t res;
223        if (satInt(res, operand, imm))
224            CpsrQ = 1 << 27;
225        Dest = res;
226    '''
227    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
228                            { "code": ssatCode,
229                              "predicate_test": condPredicateTest }, [])
230    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
231    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
232    exec_output += PredOpExecute.subst(ssatIop)
233
234    usatCode = '''
235        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
236        int32_t res;
237        if (uSatInt(res, operand, imm))
238            CpsrQ = 1 << 27;
239        Dest = res;
240    '''
241    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
242                            { "code": usatCode,
243                              "predicate_test": condPredicateTest }, [])
244    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
245    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
246    exec_output += PredOpExecute.subst(usatIop)
247
248    ssat16Code = '''
249        int32_t res;
250        uint32_t resTemp = 0;
251        int32_t argLow = sext<16>(bits(Op1, 15, 0));
252        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
253        if (satInt(res, argLow, imm))
254            CpsrQ = 1 << 27;
255        replaceBits(resTemp, 15, 0, res);
256        if (satInt(res, argHigh, imm))
257            CpsrQ = 1 << 27;
258        replaceBits(resTemp, 31, 16, res);
259        Dest = resTemp;
260    '''
261    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
262                              { "code": ssat16Code,
263                                "predicate_test": condPredicateTest }, [])
264    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
265    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
266    exec_output += PredOpExecute.subst(ssat16Iop)
267
268    usat16Code = '''
269        int32_t res;
270        uint32_t resTemp = 0;
271        int32_t argLow = sext<16>(bits(Op1, 15, 0));
272        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
273        if (uSatInt(res, argLow, imm))
274            CpsrQ = 1 << 27;
275        replaceBits(resTemp, 15, 0, res);
276        if (uSatInt(res, argHigh, imm))
277            CpsrQ = 1 << 27;
278        replaceBits(resTemp, 31, 16, res);
279        Dest = resTemp;
280    '''
281    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
282                              { "code": usat16Code,
283                                "predicate_test": condPredicateTest }, [])
284    header_output += RegImmRegOpDeclare.subst(usat16Iop)
285    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
286    exec_output += PredOpExecute.subst(usat16Iop)
287
288    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
289                            { "code":
290                              "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
291                              "predicate_test": predicateTest }, [])
292    header_output += RegImmRegOpDeclare.subst(sxtbIop)
293    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
294    exec_output += PredOpExecute.subst(sxtbIop)
295
296    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
297                             { "code":
298                               '''
299                                   Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
300                                          Op1;
301                               ''',
302                               "predicate_test": predicateTest }, [])
303    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
304    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
305    exec_output += PredOpExecute.subst(sxtabIop)
306
307    sxtb16Code = '''
308    uint32_t resTemp = 0;
309    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
310    replaceBits(resTemp, 31, 16,
311                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
312    Dest = resTemp;
313    '''
314    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
315                              { "code": sxtb16Code,
316                                "predicate_test": predicateTest }, [])
317    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
318    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
319    exec_output += PredOpExecute.subst(sxtb16Iop)
320
321    sxtab16Code = '''
322    uint32_t resTemp = 0;
323    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
324                                        bits(Op1, 15, 0));
325    replaceBits(resTemp, 31, 16,
326                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
327                bits(Op1, 31, 16));
328    Dest = resTemp;
329    '''
330    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
331                               { "code": sxtab16Code,
332                                 "predicate_test": predicateTest }, [])
333    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
334    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
335    exec_output += PredOpExecute.subst(sxtab16Iop)
336
337    sxthCode = '''
338    uint64_t rotated = (uint32_t)Op1;
339    rotated = (rotated | (rotated << 32)) >> imm;
340    Dest = sext<16>((uint16_t)rotated);
341    '''
342    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
343                              { "code": sxthCode,
344                                "predicate_test": predicateTest }, [])
345    header_output += RegImmRegOpDeclare.subst(sxthIop)
346    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
347    exec_output += PredOpExecute.subst(sxthIop)
348
349    sxtahCode = '''
350    uint64_t rotated = (uint32_t)Op2;
351    rotated = (rotated | (rotated << 32)) >> imm;
352    Dest = sext<16>((uint16_t)rotated) + Op1;
353    '''
354    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
355                             { "code": sxtahCode,
356                               "predicate_test": predicateTest }, [])
357    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
358    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
359    exec_output += PredOpExecute.subst(sxtahIop)
360
361    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
362                            { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
363                              "predicate_test": predicateTest }, [])
364    header_output += RegImmRegOpDeclare.subst(uxtbIop)
365    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
366    exec_output += PredOpExecute.subst(uxtbIop)
367
368    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
369                             { "code":
370                               "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
371                               "predicate_test": predicateTest }, [])
372    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
373    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
374    exec_output += PredOpExecute.subst(uxtabIop)
375
376    uxtb16Code = '''
377    uint32_t resTemp = 0;
378    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
379    replaceBits(resTemp, 31, 16,
380                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
381    Dest = resTemp;
382    '''
383    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
384                              { "code": uxtb16Code,
385                                "predicate_test": predicateTest }, [])
386    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
387    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
388    exec_output += PredOpExecute.subst(uxtb16Iop)
389
390    uxtab16Code = '''
391    uint32_t resTemp = 0;
392    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
393                                        bits(Op1, 15, 0));
394    replaceBits(resTemp, 31, 16,
395                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
396                bits(Op1, 31, 16));
397    Dest = resTemp;
398    '''
399    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
400                               { "code": uxtab16Code,
401                                 "predicate_test": predicateTest }, [])
402    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
403    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
404    exec_output += PredOpExecute.subst(uxtab16Iop)
405
406    uxthCode = '''
407    uint64_t rotated = (uint32_t)Op1;
408    rotated = (rotated | (rotated << 32)) >> imm;
409    Dest = (uint16_t)rotated;
410    '''
411    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
412                              { "code": uxthCode,
413                                "predicate_test": predicateTest }, [])
414    header_output += RegImmRegOpDeclare.subst(uxthIop)
415    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
416    exec_output += PredOpExecute.subst(uxthIop)
417
418    uxtahCode = '''
419    uint64_t rotated = (uint32_t)Op2;
420    rotated = (rotated | (rotated << 32)) >> imm;
421    Dest = (uint16_t)rotated + Op1;
422    '''
423    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
424                             { "code": uxtahCode,
425                               "predicate_test": predicateTest }, [])
426    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
427    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
428    exec_output += PredOpExecute.subst(uxtahIop)
429
430    selCode = '''
431        uint32_t resTemp = 0;
432        for (unsigned i = 0; i < 4; i++) {
433            int low = i * 8;
434            int high = low + 7;
435            replaceBits(resTemp, high, low,
436                        bits(CondCodesGE, i) ?
437                            bits(Op1, high, low) : bits(Op2, high, low));
438        }
439        Dest = resTemp;
440    '''
441    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
442                           { "code": selCode,
443                             "predicate_test": predicateTest }, [])
444    header_output += RegRegRegOpDeclare.subst(selIop)
445    decoder_output += RegRegRegOpConstructor.subst(selIop)
446    exec_output += PredOpExecute.subst(selIop)
447
448    usad8Code = '''
449        uint32_t resTemp = 0;
450        for (unsigned i = 0; i < 4; i++) {
451            int low = i * 8;
452            int high = low + 7;
453            int32_t diff = bits(Op1, high, low) -
454                           bits(Op2, high, low);
455            resTemp += ((diff < 0) ? -diff : diff);
456        }
457        Dest = resTemp;
458    '''
459    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
460                             { "code": usad8Code,
461                               "predicate_test": predicateTest }, [])
462    header_output += RegRegRegOpDeclare.subst(usad8Iop)
463    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
464    exec_output += PredOpExecute.subst(usad8Iop)
465
466    usada8Code = '''
467        uint32_t resTemp = 0;
468        for (unsigned i = 0; i < 4; i++) {
469            int low = i * 8;
470            int high = low + 7;
471            int32_t diff = bits(Op1, high, low) -
472                           bits(Op2, high, low);
473            resTemp += ((diff < 0) ? -diff : diff);
474        }
475        Dest = Op3 + resTemp;
476    '''
477    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
478                              { "code": usada8Code,
479                                "predicate_test": predicateTest }, [])
480    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
481    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
482    exec_output += PredOpExecute.subst(usada8Iop)
483
484    bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
485    bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
486    header_output += BasicDeclare.subst(bkptIop)
487    decoder_output += BasicConstructor.subst(bkptIop)
488    exec_output += BasicExecute.subst(bkptIop)
489
490    nopIop = InstObjParams("nop", "NopInst", "PredOp", \
491            { "code" : "", "predicate_test" : predicateTest },
492            ['IsNop'])
493    header_output += BasicDeclare.subst(nopIop)
494    decoder_output += BasicConstructor.subst(nopIop)
495    exec_output += PredOpExecute.subst(nopIop)
496
497    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
498            { "code" : "", "predicate_test" : predicateTest })
499    header_output += BasicDeclare.subst(yieldIop)
500    decoder_output += BasicConstructor.subst(yieldIop)
501    exec_output += PredOpExecute.subst(yieldIop)
502
503    wfeCode = '''
504#if FULL_SYSTEM
505    if (SevMailbox == 1) {
506        SevMailbox = 0;
507        PseudoInst::quiesceSkip(xc->tcBase());
508    } else {
509        PseudoInst::quiesce(xc->tcBase());
510    }
511#endif
512    '''
513    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
514            { "code" : wfeCode, "predicate_test" : predicateTest },
515            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
516    header_output += BasicDeclare.subst(wfeIop)
517    decoder_output += BasicConstructor.subst(wfeIop)
518    exec_output += QuiescePredOpExecute.subst(wfeIop)
519
520    wfiCode = '''
521#if FULL_SYSTEM
522    // WFI doesn't sleep if interrupts are pending (masked or not)
523    if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
524        PseudoInst::quiesceSkip(xc->tcBase());
525    } else {
526        PseudoInst::quiesce(xc->tcBase());
527    }
528#endif
529    '''
530    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
531            { "code" : wfiCode, "predicate_test" : predicateTest },
532            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
533    header_output += BasicDeclare.subst(wfiIop)
534    decoder_output += BasicConstructor.subst(wfiIop)
535    exec_output += QuiescePredOpExecute.subst(wfiIop)
536
537    sevCode = '''
538    // Need a way for O3 to not scoreboard these accesses as pipe flushes.
539    SevMailbox = 1;
540    System *sys = xc->tcBase()->getSystemPtr();
541    for (int x = 0; x < sys->numContexts(); x++) {
542        ThreadContext *oc = sys->getThreadContext(x);
543        if (oc == xc->tcBase())
544            continue;
545        // Only wake if they were sleeping
546        if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
547            oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
548            PseudoInst::wakeCPU(xc->tcBase(), x);
549        }
550    }
551    '''
552    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
553            { "code" : sevCode, "predicate_test" : predicateTest },
554            ["IsNonSpeculative", "IsSquashAfter"])
555    header_output += BasicDeclare.subst(sevIop)
556    decoder_output += BasicConstructor.subst(sevIop)
557    exec_output += PredOpExecute.subst(sevIop)
558
559    itIop = InstObjParams("it", "ItInst", "PredOp", \
560            { "code" : ";",
561              "predicate_test" : predicateTest },
562            ["IsNonSpeculative", "IsSerializeAfter"])
563    header_output += BasicDeclare.subst(itIop)
564    decoder_output += BasicConstructor.subst(itIop)
565    exec_output += PredOpExecute.subst(itIop)
566    unknownCode = '''
567#if FULL_SYSTEM
568            return new UndefinedInstruction;
569#else
570            return new UndefinedInstruction(machInst, true);
571#endif
572    '''
573    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
574                               { "code": unknownCode,
575                                 "predicate_test": predicateTest })
576    header_output += BasicDeclare.subst(unknownIop)
577    decoder_output += BasicConstructor.subst(unknownIop)
578    exec_output += PredOpExecute.subst(unknownIop)
579
580    ubfxCode = '''
581        Dest = bits(Op1, imm2, imm1);
582    '''
583    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
584                            { "code": ubfxCode,
585                              "predicate_test": predicateTest }, [])
586    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
587    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
588    exec_output += PredOpExecute.subst(ubfxIop)
589
590    sbfxCode = '''
591        int32_t resTemp = bits(Op1, imm2, imm1);
592        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
593    '''
594    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
595                            { "code": sbfxCode,
596                              "predicate_test": predicateTest }, [])
597    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
598    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
599    exec_output += PredOpExecute.subst(sbfxIop)
600
601    bfcCode = '''
602        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
603    '''
604    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
605                           { "code": bfcCode,
606                             "predicate_test": predicateTest }, [])
607    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
608    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
609    exec_output += PredOpExecute.subst(bfcIop)
610
611    bfiCode = '''
612        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
613        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
614    '''
615    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
616                           { "code": bfiCode,
617                             "predicate_test": predicateTest }, [])
618    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
619    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
620    exec_output += PredOpExecute.subst(bfiIop)
621
622    mrc15code = '''
623    CPSR cpsr = Cpsr;
624    if (cpsr.mode == MODE_USER)
625#if FULL_SYSTEM
626        return new UndefinedInstruction;
627#else
628        return new UndefinedInstruction(false, mnemonic);
629#endif
630    Dest = MiscOp1;
631    '''
632
633    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
634                             { "code": mrc15code,
635                               "predicate_test": predicateTest }, [])
636    header_output += RegRegOpDeclare.subst(mrc15Iop)
637    decoder_output += RegRegOpConstructor.subst(mrc15Iop)
638    exec_output += PredOpExecute.subst(mrc15Iop)
639
640
641    mcr15code = '''
642    CPSR cpsr = Cpsr;
643    if (cpsr.mode == MODE_USER)
644#if FULL_SYSTEM
645        return new UndefinedInstruction;
646#else
647        return new UndefinedInstruction(false, mnemonic);
648#endif
649    MiscDest = Op1;
650    '''
651    mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
652                             { "code": mcr15code,
653                               "predicate_test": predicateTest },
654                               ["IsSerializeAfter","IsNonSpeculative"])
655    header_output += RegRegOpDeclare.subst(mcr15Iop)
656    decoder_output += RegRegOpConstructor.subst(mcr15Iop)
657    exec_output += PredOpExecute.subst(mcr15Iop)
658
659    mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
660                                 { "code": "Dest = MiscOp1;",
661                                   "predicate_test": predicateTest }, [])
662    header_output += RegRegOpDeclare.subst(mrc15UserIop)
663    decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
664    exec_output += PredOpExecute.subst(mrc15UserIop)
665
666    mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
667                                 { "code": "MiscDest = Op1",
668                                   "predicate_test": predicateTest },
669                                   ["IsSerializeAfter","IsNonSpeculative"])
670    header_output += RegRegOpDeclare.subst(mcr15UserIop)
671    decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
672    exec_output += PredOpExecute.subst(mcr15UserIop)
673
674    enterxCode = '''
675        NextThumb = true;
676        NextJazelle = true;
677    '''
678    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
679                              { "code": enterxCode,
680                                "predicate_test": predicateTest }, [])
681    header_output += BasicDeclare.subst(enterxIop)
682    decoder_output += BasicConstructor.subst(enterxIop)
683    exec_output += PredOpExecute.subst(enterxIop)
684
685    leavexCode = '''
686        NextThumb = true;
687        NextJazelle = false;
688    '''
689    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
690                              { "code": leavexCode,
691                                "predicate_test": predicateTest }, [])
692    header_output += BasicDeclare.subst(leavexIop)
693    decoder_output += BasicConstructor.subst(leavexIop)
694    exec_output += PredOpExecute.subst(leavexIop)
695
696    setendCode = '''
697        CPSR cpsr = Cpsr;
698        cpsr.e = imm;
699        Cpsr = cpsr;
700    '''
701    setendIop = InstObjParams("setend", "Setend", "ImmOp",
702                              { "code": setendCode,
703                                "predicate_test": predicateTest },
704                              ["IsSerializeAfter","IsNonSpeculative"])
705    header_output += ImmOpDeclare.subst(setendIop)
706    decoder_output += ImmOpConstructor.subst(setendIop)
707    exec_output += PredOpExecute.subst(setendIop)
708
709    clrexCode = '''
710        LLSCLock = 0;
711    '''
712    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
713                             { "code": clrexCode,
714                               "predicate_test": predicateTest },[])
715    header_output += BasicDeclare.subst(clrexIop)
716    decoder_output += BasicConstructor.subst(clrexIop)
717    exec_output += PredOpExecute.subst(clrexIop)
718
719    isbCode = '''
720        fault = new FlushPipe;
721    '''
722    isbIop = InstObjParams("isb", "Isb", "PredOp",
723                             {"code": isbCode,
724                               "predicate_test": predicateTest},
725                                ['IsSerializeAfter'])
726    header_output += BasicDeclare.subst(isbIop)
727    decoder_output += BasicConstructor.subst(isbIop)
728    exec_output += PredOpExecute.subst(isbIop)
729
730    dsbCode = '''
731        fault = new FlushPipe;
732    '''
733    dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
734                             {"code": dsbCode,
735                               "predicate_test": predicateTest},
736                              ['IsMemBarrier', 'IsSerializeAfter'])
737    header_output += BasicDeclare.subst(dsbIop)
738    decoder_output += BasicConstructor.subst(dsbIop)
739    exec_output += PredOpExecute.subst(dsbIop)
740
741    dmbCode = '''
742    '''
743    dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
744                             {"code": dmbCode,
745                               "predicate_test": predicateTest},
746                               ['IsMemBarrier'])
747    header_output += BasicDeclare.subst(dmbIop)
748    decoder_output += BasicConstructor.subst(dmbIop)
749    exec_output += PredOpExecute.subst(dmbIop)
750
751    dbgCode = '''
752    '''
753    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
754                             {"code": dbgCode,
755                               "predicate_test": predicateTest})
756    header_output += BasicDeclare.subst(dbgIop)
757    decoder_output += BasicConstructor.subst(dbgIop)
758    exec_output += PredOpExecute.subst(dbgIop)
759
760    cpsCode = '''
761    uint32_t mode = bits(imm, 4, 0);
762    uint32_t f = bits(imm, 5);
763    uint32_t i = bits(imm, 6);
764    uint32_t a = bits(imm, 7);
765    bool setMode = bits(imm, 8);
766    bool enable = bits(imm, 9);
767    CPSR cpsr = Cpsr;
768    SCTLR sctlr = Sctlr;
769    if (cpsr.mode != MODE_USER) {
770        if (enable) {
771            if (f) cpsr.f = 0;
772            if (i) cpsr.i = 0;
773            if (a) cpsr.a = 0;
774        } else {
775            if (f && !sctlr.nmfi) cpsr.f = 1;
776            if (i) cpsr.i = 1;
777            if (a) cpsr.a = 1;
778        }
779        if (setMode) {
780            cpsr.mode = mode;
781        }
782    }
783    Cpsr = cpsr;
784    '''
785    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
786                           { "code": cpsCode,
787                             "predicate_test": predicateTest },
788                           ["IsSerializeAfter","IsNonSpeculative"])
789    header_output += ImmOpDeclare.subst(cpsIop)
790    decoder_output += ImmOpConstructor.subst(cpsIop)
791    exec_output += PredOpExecute.subst(cpsIop)
792}};
793