misc.isa revision 7720:65d338a8dba4 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    svcCode = '''
43#if FULL_SYSTEM
44    fault = new SupervisorCall;
45#else
46    fault = new SupervisorCall(machInst);
47#endif
48    '''
49
50    svcIop = InstObjParams("svc", "Svc", "PredOp",
51                           { "code": svcCode,
52                             "predicate_test": predicateTest }, ["IsSyscall"])
53    header_output = BasicDeclare.subst(svcIop)
54    decoder_output = BasicConstructor.subst(svcIop)
55    exec_output = PredOpExecute.subst(svcIop)
56
57}};
58
59let {{
60
61    header_output = decoder_output = exec_output = ""
62
63    mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65                               { "code": mrsCpsrCode,
66                                 "predicate_test": condPredicateTest },
67                               ["IsSerializeAfter"])
68    header_output += MrsDeclare.subst(mrsCpsrIop)
69    decoder_output += MrsConstructor.subst(mrsCpsrIop)
70    exec_output += PredOpExecute.subst(mrsCpsrIop)
71
72    mrsSpsrCode = "Dest = Spsr"
73    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
74                               { "code": mrsSpsrCode,
75                                 "predicate_test": predicateTest },
76                               ["IsSerializeAfter"])
77    header_output += MrsDeclare.subst(mrsSpsrIop)
78    decoder_output += MrsConstructor.subst(mrsSpsrIop)
79    exec_output += PredOpExecute.subst(mrsSpsrIop)
80
81    msrCpsrRegCode = '''
82        SCTLR sctlr = Sctlr;
83        uint32_t newCpsr =
84            cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
85        Cpsr = ~CondCodesMask & newCpsr;
86        ArmISA::PCState pc = PCS;
87        pc.nextThumb(((CPSR)newCpsr).t);
88        pc.nextJazelle(((CPSR)newCpsr).j);
89        PCS = pc;
90        CondCodes = CondCodesMask & newCpsr;
91    '''
92    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
93                                  { "code": msrCpsrRegCode,
94                                    "predicate_test": condPredicateTest },
95                                  ["IsSerializeAfter","IsNonSpeculative"])
96    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
97    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
98    exec_output += PredOpExecute.subst(msrCpsrRegIop)
99
100    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
101    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
102                                  { "code": msrSpsrRegCode,
103                                    "predicate_test": predicateTest },
104                                  ["IsSerializeAfter","IsNonSpeculative"])
105    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
106    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
107    exec_output += PredOpExecute.subst(msrSpsrRegIop)
108
109    msrCpsrImmCode = '''
110        SCTLR sctlr = Sctlr;
111        uint32_t newCpsr =
112            cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
113        Cpsr = ~CondCodesMask & newCpsr;
114        ArmISA::PCState pc = PCS;
115        pc.nextThumb(((CPSR)newCpsr).t);
116        pc.nextJazelle(((CPSR)newCpsr).j);
117        PCS = pc;
118        CondCodes = CondCodesMask & newCpsr;
119    '''
120    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
121                                  { "code": msrCpsrImmCode,
122                                    "predicate_test": condPredicateTest },
123                                  ["IsSerializeAfter","IsNonSpeculative"])
124    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
125    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
126    exec_output += PredOpExecute.subst(msrCpsrImmIop)
127
128    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
129    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
130                                  { "code": msrSpsrImmCode,
131                                    "predicate_test": predicateTest },
132                                  ["IsSerializeAfter","IsNonSpeculative"])
133    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
134    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
135    exec_output += PredOpExecute.subst(msrSpsrImmIop)
136
137    revCode = '''
138    uint32_t val = Op1;
139    Dest = swap_byte(val);
140    '''
141    revIop = InstObjParams("rev", "Rev", "RegRegOp",
142                           { "code": revCode,
143                             "predicate_test": predicateTest }, [])
144    header_output += RegRegOpDeclare.subst(revIop)
145    decoder_output += RegRegOpConstructor.subst(revIop)
146    exec_output += PredOpExecute.subst(revIop)
147
148    rev16Code = '''
149    uint32_t val = Op1;
150    Dest = (bits(val, 15, 8) << 0) |
151           (bits(val, 7, 0) << 8) |
152           (bits(val, 31, 24) << 16) |
153           (bits(val, 23, 16) << 24);
154    '''
155    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
156                             { "code": rev16Code,
157                               "predicate_test": predicateTest }, [])
158    header_output += RegRegOpDeclare.subst(rev16Iop)
159    decoder_output += RegRegOpConstructor.subst(rev16Iop)
160    exec_output += PredOpExecute.subst(rev16Iop)
161
162    revshCode = '''
163    uint16_t val = Op1;
164    Dest = sext<16>(swap_byte(val));
165    '''
166    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
167                             { "code": revshCode,
168                               "predicate_test": predicateTest }, [])
169    header_output += RegRegOpDeclare.subst(revshIop)
170    decoder_output += RegRegOpConstructor.subst(revshIop)
171    exec_output += PredOpExecute.subst(revshIop)
172
173    rbitCode = '''
174    uint8_t *opBytes = (uint8_t *)&Op1;
175    uint32_t resTemp;
176    uint8_t *destBytes = (uint8_t *)&resTemp;
177    // This reverses the bytes and bits of the input, or so says the
178    // internet.
179    for (int i = 0; i < 4; i++) {
180        uint32_t temp = opBytes[i];
181        temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
182        destBytes[3 - i] = (temp * 0x10101) >> 16;
183    }
184    Dest = resTemp;
185    '''
186    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
187                            { "code": rbitCode,
188                              "predicate_test": predicateTest }, [])
189    header_output += RegRegOpDeclare.subst(rbitIop)
190    decoder_output += RegRegOpConstructor.subst(rbitIop)
191    exec_output += PredOpExecute.subst(rbitIop)
192
193    clzCode = '''
194        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
195    '''
196    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
197                           { "code": clzCode,
198                             "predicate_test": predicateTest }, [])
199    header_output += RegRegOpDeclare.subst(clzIop)
200    decoder_output += RegRegOpConstructor.subst(clzIop)
201    exec_output += PredOpExecute.subst(clzIop)
202
203    ssatCode = '''
204        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
205        int32_t res;
206        if (satInt(res, operand, imm))
207            CondCodes = CondCodes | (1 << 27);
208        else
209            CondCodes = CondCodes;
210        Dest = res;
211    '''
212    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
213                            { "code": ssatCode,
214                              "predicate_test": condPredicateTest }, [])
215    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
216    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
217    exec_output += PredOpExecute.subst(ssatIop)
218
219    usatCode = '''
220        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
221        int32_t res;
222        if (uSatInt(res, operand, imm))
223            CondCodes = CondCodes | (1 << 27);
224        else
225            CondCodes = CondCodes;
226        Dest = res;
227    '''
228    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
229                            { "code": usatCode,
230                              "predicate_test": condPredicateTest }, [])
231    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
232    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
233    exec_output += PredOpExecute.subst(usatIop)
234
235    ssat16Code = '''
236        int32_t res;
237        uint32_t resTemp = 0;
238        CondCodes = CondCodes;
239        int32_t argLow = sext<16>(bits(Op1, 15, 0));
240        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
241        if (satInt(res, argLow, imm))
242            CondCodes = CondCodes | (1 << 27);
243        replaceBits(resTemp, 15, 0, res);
244        if (satInt(res, argHigh, imm))
245            CondCodes = CondCodes | (1 << 27);
246        replaceBits(resTemp, 31, 16, res);
247        Dest = resTemp;
248    '''
249    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
250                              { "code": ssat16Code,
251                                "predicate_test": condPredicateTest }, [])
252    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
253    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
254    exec_output += PredOpExecute.subst(ssat16Iop)
255
256    usat16Code = '''
257        int32_t res;
258        uint32_t resTemp = 0;
259        CondCodes = CondCodes;
260        int32_t argLow = sext<16>(bits(Op1, 15, 0));
261        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
262        if (uSatInt(res, argLow, imm))
263            CondCodes = CondCodes | (1 << 27);
264        replaceBits(resTemp, 15, 0, res);
265        if (uSatInt(res, argHigh, imm))
266            CondCodes = CondCodes | (1 << 27);
267        replaceBits(resTemp, 31, 16, res);
268        Dest = resTemp;
269    '''
270    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
271                              { "code": usat16Code,
272                                "predicate_test": condPredicateTest }, [])
273    header_output += RegImmRegOpDeclare.subst(usat16Iop)
274    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
275    exec_output += PredOpExecute.subst(usat16Iop)
276
277    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
278                            { "code":
279                              "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
280                              "predicate_test": predicateTest }, [])
281    header_output += RegImmRegOpDeclare.subst(sxtbIop)
282    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
283    exec_output += PredOpExecute.subst(sxtbIop)
284
285    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
286                             { "code":
287                               '''
288                                   Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
289                                          Op1;
290                               ''',
291                               "predicate_test": predicateTest }, [])
292    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
293    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
294    exec_output += PredOpExecute.subst(sxtabIop)
295
296    sxtb16Code = '''
297    uint32_t resTemp = 0;
298    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
299    replaceBits(resTemp, 31, 16,
300                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
301    Dest = resTemp;
302    '''
303    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
304                              { "code": sxtb16Code,
305                                "predicate_test": predicateTest }, [])
306    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
307    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
308    exec_output += PredOpExecute.subst(sxtb16Iop)
309
310    sxtab16Code = '''
311    uint32_t resTemp = 0;
312    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
313                                        bits(Op1, 15, 0));
314    replaceBits(resTemp, 31, 16,
315                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
316                bits(Op1, 31, 16));
317    Dest = resTemp;
318    '''
319    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
320                               { "code": sxtab16Code,
321                                 "predicate_test": predicateTest }, [])
322    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
323    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
324    exec_output += PredOpExecute.subst(sxtab16Iop)
325
326    sxthCode = '''
327    uint64_t rotated = (uint32_t)Op1;
328    rotated = (rotated | (rotated << 32)) >> imm;
329    Dest = sext<16>((uint16_t)rotated);
330    '''
331    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
332                              { "code": sxthCode,
333                                "predicate_test": predicateTest }, [])
334    header_output += RegImmRegOpDeclare.subst(sxthIop)
335    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
336    exec_output += PredOpExecute.subst(sxthIop)
337
338    sxtahCode = '''
339    uint64_t rotated = (uint32_t)Op2;
340    rotated = (rotated | (rotated << 32)) >> imm;
341    Dest = sext<16>((uint16_t)rotated) + Op1;
342    '''
343    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
344                             { "code": sxtahCode,
345                               "predicate_test": predicateTest }, [])
346    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
347    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
348    exec_output += PredOpExecute.subst(sxtahIop)
349
350    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
351                            { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
352                              "predicate_test": predicateTest }, [])
353    header_output += RegImmRegOpDeclare.subst(uxtbIop)
354    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
355    exec_output += PredOpExecute.subst(uxtbIop)
356
357    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
358                             { "code":
359                               "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
360                               "predicate_test": predicateTest }, [])
361    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
362    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
363    exec_output += PredOpExecute.subst(uxtabIop)
364
365    uxtb16Code = '''
366    uint32_t resTemp = 0;
367    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
368    replaceBits(resTemp, 31, 16,
369                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
370    Dest = resTemp;
371    '''
372    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
373                              { "code": uxtb16Code,
374                                "predicate_test": predicateTest }, [])
375    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
376    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
377    exec_output += PredOpExecute.subst(uxtb16Iop)
378
379    uxtab16Code = '''
380    uint32_t resTemp = 0;
381    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
382                                        bits(Op1, 15, 0));
383    replaceBits(resTemp, 31, 16,
384                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
385                bits(Op1, 31, 16));
386    Dest = resTemp;
387    '''
388    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
389                               { "code": uxtab16Code,
390                                 "predicate_test": predicateTest }, [])
391    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
392    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
393    exec_output += PredOpExecute.subst(uxtab16Iop)
394
395    uxthCode = '''
396    uint64_t rotated = (uint32_t)Op1;
397    rotated = (rotated | (rotated << 32)) >> imm;
398    Dest = (uint16_t)rotated;
399    '''
400    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
401                              { "code": uxthCode,
402                                "predicate_test": predicateTest }, [])
403    header_output += RegImmRegOpDeclare.subst(uxthIop)
404    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
405    exec_output += PredOpExecute.subst(uxthIop)
406
407    uxtahCode = '''
408    uint64_t rotated = (uint32_t)Op2;
409    rotated = (rotated | (rotated << 32)) >> imm;
410    Dest = (uint16_t)rotated + Op1;
411    '''
412    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
413                             { "code": uxtahCode,
414                               "predicate_test": predicateTest }, [])
415    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
416    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
417    exec_output += PredOpExecute.subst(uxtahIop)
418
419    selCode = '''
420        uint32_t resTemp = 0;
421        for (unsigned i = 0; i < 4; i++) {
422            int low = i * 8;
423            int high = low + 7;
424            replaceBits(resTemp, high, low,
425                        bits(CondCodes, 16 + i) ?
426                            bits(Op1, high, low) : bits(Op2, high, low));
427        }
428        Dest = resTemp;
429    '''
430    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
431                           { "code": selCode,
432                             "predicate_test": condPredicateTest }, [])
433    header_output += RegRegRegOpDeclare.subst(selIop)
434    decoder_output += RegRegRegOpConstructor.subst(selIop)
435    exec_output += PredOpExecute.subst(selIop)
436
437    usad8Code = '''
438        uint32_t resTemp = 0;
439        for (unsigned i = 0; i < 4; i++) {
440            int low = i * 8;
441            int high = low + 7;
442            int32_t diff = bits(Op1, high, low) -
443                           bits(Op2, high, low);
444            resTemp += ((diff < 0) ? -diff : diff);
445        }
446        Dest = resTemp;
447    '''
448    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
449                             { "code": usad8Code,
450                               "predicate_test": predicateTest }, [])
451    header_output += RegRegRegOpDeclare.subst(usad8Iop)
452    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
453    exec_output += PredOpExecute.subst(usad8Iop)
454
455    usada8Code = '''
456        uint32_t resTemp = 0;
457        for (unsigned i = 0; i < 4; i++) {
458            int low = i * 8;
459            int high = low + 7;
460            int32_t diff = bits(Op1, high, low) -
461                           bits(Op2, high, low);
462            resTemp += ((diff < 0) ? -diff : diff);
463        }
464        Dest = Op3 + resTemp;
465    '''
466    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
467                              { "code": usada8Code,
468                                "predicate_test": predicateTest }, [])
469    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
470    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
471    exec_output += PredOpExecute.subst(usada8Iop)
472
473    bkptCode = '''
474    ArmISA::PCState pc = PCS;
475    return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
476    '''
477    bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
478            bkptCode)
479    header_output += BasicDeclare.subst(bkptIop)
480    decoder_output += BasicConstructor.subst(bkptIop)
481    exec_output += BasicExecute.subst(bkptIop)
482
483    nopIop = InstObjParams("nop", "NopInst", "PredOp", \
484            { "code" : "", "predicate_test" : predicateTest })
485    header_output += BasicDeclare.subst(nopIop)
486    decoder_output += BasicConstructor.subst(nopIop)
487    exec_output += PredOpExecute.subst(nopIop)
488
489    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
490            { "code" : "", "predicate_test" : predicateTest })
491    header_output += BasicDeclare.subst(yieldIop)
492    decoder_output += BasicConstructor.subst(yieldIop)
493    exec_output += PredOpExecute.subst(yieldIop)
494
495    wfeCode = '''
496#if FULL_SYSTEM
497    if (SevMailbox)
498        SevMailbox = 0;
499    else
500        PseudoInst::quiesce(xc->tcBase());
501#endif
502    '''
503    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
504            { "code" : wfeCode, "predicate_test" : predicateTest },
505            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
506    header_output += BasicDeclare.subst(wfeIop)
507    decoder_output += BasicConstructor.subst(wfeIop)
508    exec_output += PredOpExecute.subst(wfeIop)
509
510    wfiCode = '''
511#if FULL_SYSTEM
512    PseudoInst::quiesce(xc->tcBase());
513#endif
514    '''
515    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
516            { "code" : wfiCode, "predicate_test" : predicateTest },
517            ["IsNonSpeculative", "IsQuiesce"])
518    header_output += BasicDeclare.subst(wfiIop)
519    decoder_output += BasicConstructor.subst(wfiIop)
520    exec_output += PredOpExecute.subst(wfiIop)
521
522    sevCode = '''
523    // Need a way for O3 to not scoreboard these accesses as pipe flushes.
524    System *sys = xc->tcBase()->getSystemPtr();
525    for (int x = 0; x < sys->numContexts(); x++) {
526        ThreadContext *oc = sys->getThreadContext(x);
527        oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
528    }
529    '''
530    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
531            { "code" : sevCode, "predicate_test" : predicateTest },
532            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
533    header_output += BasicDeclare.subst(sevIop)
534    decoder_output += BasicConstructor.subst(sevIop)
535    exec_output += PredOpExecute.subst(sevIop)
536
537    itIop = InstObjParams("it", "ItInst", "PredOp", \
538            { "code" : "Itstate = machInst.newItstate;",
539              "predicate_test" : predicateTest },
540            ["IsNonSpeculative", "IsSerializeAfter"])
541    header_output += BasicDeclare.subst(itIop)
542    decoder_output += BasicConstructor.subst(itIop)
543    exec_output += PredOpExecute.subst(itIop)
544    unknownCode = '''
545#if FULL_SYSTEM
546            return new UndefinedInstruction;
547#else
548            return new UndefinedInstruction(machInst, true);
549#endif
550    '''
551    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
552                               { "code": unknownCode,
553                                 "predicate_test": predicateTest })
554    header_output += BasicDeclare.subst(unknownIop)
555    decoder_output += BasicConstructor.subst(unknownIop)
556    exec_output += PredOpExecute.subst(unknownIop)
557
558    ubfxCode = '''
559        Dest = bits(Op1, imm2, imm1);
560    '''
561    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
562                            { "code": ubfxCode,
563                              "predicate_test": predicateTest }, [])
564    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
565    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
566    exec_output += PredOpExecute.subst(ubfxIop)
567
568    sbfxCode = '''
569        int32_t resTemp = bits(Op1, imm2, imm1);
570        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
571    '''
572    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
573                            { "code": sbfxCode,
574                              "predicate_test": predicateTest }, [])
575    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
576    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
577    exec_output += PredOpExecute.subst(sbfxIop)
578
579    bfcCode = '''
580        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
581    '''
582    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
583                           { "code": bfcCode,
584                             "predicate_test": predicateTest }, [])
585    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
586    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
587    exec_output += PredOpExecute.subst(bfcIop)
588
589    bfiCode = '''
590        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
591        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
592    '''
593    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
594                           { "code": bfiCode,
595                             "predicate_test": predicateTest }, [])
596    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
597    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
598    exec_output += PredOpExecute.subst(bfiIop)
599
600    mrc15code = '''
601    CPSR cpsr = Cpsr;
602    if (cpsr.mode == MODE_USER)
603#if FULL_SYSTEM
604        return new UndefinedInstruction;
605#else
606        return new UndefinedInstruction(false, mnemonic);
607#endif
608    Dest = MiscOp1;
609    '''
610
611    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
612                             { "code": mrc15code,
613                               "predicate_test": predicateTest }, [])
614    header_output += RegRegOpDeclare.subst(mrc15Iop)
615    decoder_output += RegRegOpConstructor.subst(mrc15Iop)
616    exec_output += PredOpExecute.subst(mrc15Iop)
617
618
619    mcr15code = '''
620    CPSR cpsr = Cpsr;
621    if (cpsr.mode == MODE_USER)
622#if FULL_SYSTEM
623        return new UndefinedInstruction;
624#else
625        return new UndefinedInstruction(false, mnemonic);
626#endif
627    MiscDest = Op1;
628    '''
629    mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
630                             { "code": mcr15code,
631                               "predicate_test": predicateTest },
632                               ["IsSerializeAfter","IsNonSpeculative"])
633    header_output += RegRegOpDeclare.subst(mcr15Iop)
634    decoder_output += RegRegOpConstructor.subst(mcr15Iop)
635    exec_output += PredOpExecute.subst(mcr15Iop)
636
637    mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
638                                 { "code": "Dest = MiscOp1;",
639                                   "predicate_test": predicateTest }, [])
640    header_output += RegRegOpDeclare.subst(mrc15UserIop)
641    decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
642    exec_output += PredOpExecute.subst(mrc15UserIop)
643
644    mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
645                                 { "code": "MiscDest = Op1",
646                                   "predicate_test": predicateTest },
647                                   ["IsSerializeAfter","IsNonSpeculative"])
648    header_output += RegRegOpDeclare.subst(mcr15UserIop)
649    decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
650    exec_output += PredOpExecute.subst(mcr15UserIop)
651
652    enterxCode = '''
653        ArmISA::PCState pc = PCS;
654        pc.nextThumb(true);
655        pc.nextJazelle(true);
656        PCS = pc;
657    '''
658    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
659                              { "code": enterxCode,
660                                "predicate_test": predicateTest }, [])
661    header_output += BasicDeclare.subst(enterxIop)
662    decoder_output += BasicConstructor.subst(enterxIop)
663    exec_output += PredOpExecute.subst(enterxIop)
664
665    leavexCode = '''
666        ArmISA::PCState pc = PCS;
667        pc.nextThumb(true);
668        pc.nextJazelle(false);
669        PCS = pc;
670    '''
671    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
672                              { "code": leavexCode,
673                                "predicate_test": predicateTest }, [])
674    header_output += BasicDeclare.subst(leavexIop)
675    decoder_output += BasicConstructor.subst(leavexIop)
676    exec_output += PredOpExecute.subst(leavexIop)
677
678    setendCode = '''
679        CPSR cpsr = Cpsr;
680        cpsr.e = imm;
681        Cpsr = cpsr;
682    '''
683    setendIop = InstObjParams("setend", "Setend", "ImmOp",
684                              { "code": setendCode,
685                                "predicate_test": predicateTest },
686                              ["IsSerializeAfter","IsNonSpeculative"])
687    header_output += ImmOpDeclare.subst(setendIop)
688    decoder_output += ImmOpConstructor.subst(setendIop)
689    exec_output += PredOpExecute.subst(setendIop)
690
691    clrexCode = '''
692        unsigned memAccessFlags = Request::CLEAR_LL |
693            ArmISA::TLB::AlignWord | Request::LLSC;
694        fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
695    '''
696    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
697                             { "code": clrexCode,
698                               "predicate_test": predicateTest },[])
699    header_output += ClrexDeclare.subst(clrexIop)
700    decoder_output += BasicConstructor.subst(clrexIop)
701    exec_output += PredOpExecute.subst(clrexIop)
702    exec_output += ClrexInitiateAcc.subst(clrexIop)
703    exec_output += ClrexCompleteAcc.subst(clrexIop)
704
705    isbCode = '''
706    '''
707    isbIop = InstObjParams("isb", "Isb", "PredOp",
708                             {"code": isbCode,
709                               "predicate_test": predicateTest}, ['IsSerializing'])
710    header_output += BasicDeclare.subst(isbIop)
711    decoder_output += BasicConstructor.subst(isbIop)
712    exec_output += PredOpExecute.subst(isbIop)
713
714    dsbCode = '''
715    '''
716    dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
717                             {"code": dsbCode,
718                               "predicate_test": predicateTest},['IsMemBarrier'])
719    header_output += BasicDeclare.subst(dsbIop)
720    decoder_output += BasicConstructor.subst(dsbIop)
721    exec_output += PredOpExecute.subst(dsbIop)
722
723    dmbCode = '''
724    '''
725    dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
726                             {"code": dmbCode,
727                               "predicate_test": predicateTest},['IsMemBarrier'])
728    header_output += BasicDeclare.subst(dmbIop)
729    decoder_output += BasicConstructor.subst(dmbIop)
730    exec_output += PredOpExecute.subst(dmbIop)
731
732    dbgCode = '''
733    '''
734    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
735                             {"code": dbgCode,
736                               "predicate_test": predicateTest})
737    header_output += BasicDeclare.subst(dbgIop)
738    decoder_output += BasicConstructor.subst(dbgIop)
739    exec_output += PredOpExecute.subst(dbgIop)
740
741    cpsCode = '''
742    uint32_t mode = bits(imm, 4, 0);
743    uint32_t f = bits(imm, 5);
744    uint32_t i = bits(imm, 6);
745    uint32_t a = bits(imm, 7);
746    bool setMode = bits(imm, 8);
747    bool enable = bits(imm, 9);
748    CPSR cpsr = Cpsr;
749    SCTLR sctlr = Sctlr;
750    if (cpsr.mode != MODE_USER) {
751        if (enable) {
752            if (f) cpsr.f = 0;
753            if (i) cpsr.i = 0;
754            if (a) cpsr.a = 0;
755        } else {
756            if (f && !sctlr.nmfi) cpsr.f = 1;
757            if (i) cpsr.i = 1;
758            if (a) cpsr.a = 1;
759        }
760        if (setMode) {
761            cpsr.mode = mode;
762        }
763    }
764    Cpsr = cpsr;
765    '''
766    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
767                           { "code": cpsCode,
768                             "predicate_test": predicateTest },
769                           ["IsSerializeAfter","IsNonSpeculative"])
770    header_output += ImmOpDeclare.subst(cpsIop)
771    decoder_output += ImmOpConstructor.subst(cpsIop)
772    exec_output += PredOpExecute.subst(cpsIop)
773}};
774