misc.isa revision 7705
14120SN/A// -*- mode:c++ -*- 24120SN/A 39917Ssteve.reinhardt@amd.com// Copyright (c) 2010 ARM Limited 44120SN/A// All rights reserved 54120SN/A// 67087Snate@binkert.org// The license below extends only to copyright in the software and shall 77087Snate@binkert.org// not be construed as granting a license to any other intellectual 87087Snate@binkert.org// property including but not limited to intellectual property relating 97087Snate@binkert.org// to a hardware implementation of the functionality of the software 107087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org// modified or unmodified, in source code or in binary form. 144120SN/A// 157087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 167087Snate@binkert.org// modification, are permitted provided that the following conditions are 177087Snate@binkert.org// met: redistributions of source code must retain the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 197087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 207087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 217087Snate@binkert.org// documentation and/or other materials provided with the distribution; 227087Snate@binkert.org// neither the name of the copyright holders nor the names of its 234120SN/A// contributors may be used to endorse or promote products derived from 247087Snate@binkert.org// this software without specific prior written permission. 254120SN/A// 264120SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 274120SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 284120SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 294120SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 304120SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 314120SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 324120SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 334120SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 344120SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 354120SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 364120SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 374120SN/A// 384120SN/A// Authors: Gabe Black 394120SN/A 404120SN/Alet {{ 416329Sgblack@eecs.umich.edu 426329Sgblack@eecs.umich.edu svcCode = ''' 436216SN/A#if FULL_SYSTEM 4412109SRekai.GonzalezAlberquilla@arm.com fault = new SupervisorCall; 458961Sgblack@eecs.umich.edu#else 467629Sgblack@eecs.umich.edu fault = new SupervisorCall(machInst); 479921Syasuko.eckert@amd.com#endif 487629Sgblack@eecs.umich.edu ''' 496315SN/A 504137SN/A svcIop = InstObjParams("svc", "Svc", "PredOp", 514120SN/A { "code": svcCode, 524120SN/A "predicate_test": predicateTest }, ["IsSyscall"]) 536329Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(svcIop) 546329Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(svcIop) 559046SAli.Saidi@ARM.com exec_output = PredOpExecute.subst(svcIop) 566329Sgblack@eecs.umich.edu 576313SN/A}}; 586329Sgblack@eecs.umich.edu 599921Syasuko.eckert@amd.comlet {{ 609921Syasuko.eckert@amd.com 619921Syasuko.eckert@amd.com header_output = decoder_output = exec_output = "" 629921Syasuko.eckert@amd.com 636319SN/A mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF" 649917Ssteve.reinhardt@amd.com mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 659917Ssteve.reinhardt@amd.com { "code": mrsCpsrCode, 666329Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 679917Ssteve.reinhardt@amd.com ["IsSerializeAfter"]) 686315SN/A header_output += MrsDeclare.subst(mrsCpsrIop) 696329Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 706329Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 719918Ssteve.reinhardt@amd.com 729917Ssteve.reinhardt@amd.com mrsSpsrCode = "Dest = Spsr" 739917Ssteve.reinhardt@amd.com mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 749918Ssteve.reinhardt@amd.com { "code": mrsSpsrCode, 759920Syasuko.eckert@amd.com "predicate_test": predicateTest }, 7610935Snilay@cs.wisc.edu ["IsSerializeAfter"]) 779918Ssteve.reinhardt@amd.com header_output += MrsDeclare.subst(mrsSpsrIop) 786329Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 794137SN/A exec_output += PredOpExecute.subst(mrsSpsrIop) 806329Sgblack@eecs.umich.edu 816329Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 826329Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 836329Sgblack@eecs.umich.edu uint32_t newCpsr = 846329Sgblack@eecs.umich.edu cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); 856329Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 866329Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 876329Sgblack@eecs.umich.edu ''' 884137SN/A msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 896329Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 906329Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 916329Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 926329Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 9313556Sgabeblack@google.com decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 949920Syasuko.eckert@amd.com exec_output += PredOpExecute.subst(msrCpsrRegIop) 9513556Sgabeblack@google.com 966329Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 9712109SRekai.GonzalezAlberquilla@arm.com msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 9812109SRekai.GonzalezAlberquilla@arm.com { "code": msrSpsrRegCode, 9912109SRekai.GonzalezAlberquilla@arm.com "predicate_test": predicateTest }, 10012109SRekai.GonzalezAlberquilla@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 10112109SRekai.GonzalezAlberquilla@arm.com header_output += MsrRegDeclare.subst(msrSpsrRegIop) 10212109SRekai.GonzalezAlberquilla@arm.com decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 10312109SRekai.GonzalezAlberquilla@arm.com exec_output += PredOpExecute.subst(msrSpsrRegIop) 10412109SRekai.GonzalezAlberquilla@arm.com 10512109SRekai.GonzalezAlberquilla@arm.com msrCpsrImmCode = ''' 1066329Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 1076329Sgblack@eecs.umich.edu uint32_t newCpsr = 10813556Sgabeblack@google.com cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); 10913556Sgabeblack@google.com Cpsr = ~CondCodesMask & newCpsr; 1106329Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 1117811Ssteve.reinhardt@amd.com ''' 1124120SN/A msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 1134120SN/A { "code": msrCpsrImmCode, 114 "predicate_test": condPredicateTest }, 115 ["IsSerializeAfter","IsNonSpeculative"]) 116 header_output += MsrImmDeclare.subst(msrCpsrImmIop) 117 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 118 exec_output += PredOpExecute.subst(msrCpsrImmIop) 119 120 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 121 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 122 { "code": msrSpsrImmCode, 123 "predicate_test": predicateTest }, 124 ["IsSerializeAfter","IsNonSpeculative"]) 125 header_output += MsrImmDeclare.subst(msrSpsrImmIop) 126 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 127 exec_output += PredOpExecute.subst(msrSpsrImmIop) 128 129 revCode = ''' 130 uint32_t val = Op1; 131 Dest = swap_byte(val); 132 ''' 133 revIop = InstObjParams("rev", "Rev", "RegRegOp", 134 { "code": revCode, 135 "predicate_test": predicateTest }, []) 136 header_output += RegRegOpDeclare.subst(revIop) 137 decoder_output += RegRegOpConstructor.subst(revIop) 138 exec_output += PredOpExecute.subst(revIop) 139 140 rev16Code = ''' 141 uint32_t val = Op1; 142 Dest = (bits(val, 15, 8) << 0) | 143 (bits(val, 7, 0) << 8) | 144 (bits(val, 31, 24) << 16) | 145 (bits(val, 23, 16) << 24); 146 ''' 147 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 148 { "code": rev16Code, 149 "predicate_test": predicateTest }, []) 150 header_output += RegRegOpDeclare.subst(rev16Iop) 151 decoder_output += RegRegOpConstructor.subst(rev16Iop) 152 exec_output += PredOpExecute.subst(rev16Iop) 153 154 revshCode = ''' 155 uint16_t val = Op1; 156 Dest = sext<16>(swap_byte(val)); 157 ''' 158 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 159 { "code": revshCode, 160 "predicate_test": predicateTest }, []) 161 header_output += RegRegOpDeclare.subst(revshIop) 162 decoder_output += RegRegOpConstructor.subst(revshIop) 163 exec_output += PredOpExecute.subst(revshIop) 164 165 rbitCode = ''' 166 uint8_t *opBytes = (uint8_t *)&Op1; 167 uint32_t resTemp; 168 uint8_t *destBytes = (uint8_t *)&resTemp; 169 // This reverses the bytes and bits of the input, or so says the 170 // internet. 171 for (int i = 0; i < 4; i++) { 172 uint32_t temp = opBytes[i]; 173 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 174 destBytes[3 - i] = (temp * 0x10101) >> 16; 175 } 176 Dest = resTemp; 177 ''' 178 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 179 { "code": rbitCode, 180 "predicate_test": predicateTest }, []) 181 header_output += RegRegOpDeclare.subst(rbitIop) 182 decoder_output += RegRegOpConstructor.subst(rbitIop) 183 exec_output += PredOpExecute.subst(rbitIop) 184 185 clzCode = ''' 186 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 187 ''' 188 clzIop = InstObjParams("clz", "Clz", "RegRegOp", 189 { "code": clzCode, 190 "predicate_test": predicateTest }, []) 191 header_output += RegRegOpDeclare.subst(clzIop) 192 decoder_output += RegRegOpConstructor.subst(clzIop) 193 exec_output += PredOpExecute.subst(clzIop) 194 195 ssatCode = ''' 196 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 197 int32_t res; 198 if (satInt(res, operand, imm)) 199 CondCodes = CondCodes | (1 << 27); 200 else 201 CondCodes = CondCodes; 202 Dest = res; 203 ''' 204 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 205 { "code": ssatCode, 206 "predicate_test": condPredicateTest }, []) 207 header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 208 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 209 exec_output += PredOpExecute.subst(ssatIop) 210 211 usatCode = ''' 212 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 213 int32_t res; 214 if (uSatInt(res, operand, imm)) 215 CondCodes = CondCodes | (1 << 27); 216 else 217 CondCodes = CondCodes; 218 Dest = res; 219 ''' 220 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 221 { "code": usatCode, 222 "predicate_test": condPredicateTest }, []) 223 header_output += RegImmRegShiftOpDeclare.subst(usatIop) 224 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 225 exec_output += PredOpExecute.subst(usatIop) 226 227 ssat16Code = ''' 228 int32_t res; 229 uint32_t resTemp = 0; 230 CondCodes = CondCodes; 231 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 232 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 233 if (satInt(res, argLow, imm)) 234 CondCodes = CondCodes | (1 << 27); 235 replaceBits(resTemp, 15, 0, res); 236 if (satInt(res, argHigh, imm)) 237 CondCodes = CondCodes | (1 << 27); 238 replaceBits(resTemp, 31, 16, res); 239 Dest = resTemp; 240 ''' 241 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 242 { "code": ssat16Code, 243 "predicate_test": condPredicateTest }, []) 244 header_output += RegImmRegOpDeclare.subst(ssat16Iop) 245 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 246 exec_output += PredOpExecute.subst(ssat16Iop) 247 248 usat16Code = ''' 249 int32_t res; 250 uint32_t resTemp = 0; 251 CondCodes = CondCodes; 252 int32_t argLow = sext<16>(bits(Op1, 15, 0)); 253 int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 254 if (uSatInt(res, argLow, imm)) 255 CondCodes = CondCodes | (1 << 27); 256 replaceBits(resTemp, 15, 0, res); 257 if (uSatInt(res, argHigh, imm)) 258 CondCodes = CondCodes | (1 << 27); 259 replaceBits(resTemp, 31, 16, res); 260 Dest = resTemp; 261 ''' 262 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 263 { "code": usat16Code, 264 "predicate_test": condPredicateTest }, []) 265 header_output += RegImmRegOpDeclare.subst(usat16Iop) 266 decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 267 exec_output += PredOpExecute.subst(usat16Iop) 268 269 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 270 { "code": 271 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));", 272 "predicate_test": predicateTest }, []) 273 header_output += RegImmRegOpDeclare.subst(sxtbIop) 274 decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 275 exec_output += PredOpExecute.subst(sxtbIop) 276 277 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 278 { "code": 279 ''' 280 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) + 281 Op1; 282 ''', 283 "predicate_test": predicateTest }, []) 284 header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 285 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 286 exec_output += PredOpExecute.subst(sxtabIop) 287 288 sxtb16Code = ''' 289 uint32_t resTemp = 0; 290 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 291 replaceBits(resTemp, 31, 16, 292 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 293 Dest = resTemp; 294 ''' 295 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 296 { "code": sxtb16Code, 297 "predicate_test": predicateTest }, []) 298 header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 299 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 300 exec_output += PredOpExecute.subst(sxtb16Iop) 301 302 sxtab16Code = ''' 303 uint32_t resTemp = 0; 304 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 305 bits(Op1, 15, 0)); 306 replaceBits(resTemp, 31, 16, 307 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 308 bits(Op1, 31, 16)); 309 Dest = resTemp; 310 ''' 311 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 312 { "code": sxtab16Code, 313 "predicate_test": predicateTest }, []) 314 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 315 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 316 exec_output += PredOpExecute.subst(sxtab16Iop) 317 318 sxthCode = ''' 319 uint64_t rotated = (uint32_t)Op1; 320 rotated = (rotated | (rotated << 32)) >> imm; 321 Dest = sext<16>((uint16_t)rotated); 322 ''' 323 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 324 { "code": sxthCode, 325 "predicate_test": predicateTest }, []) 326 header_output += RegImmRegOpDeclare.subst(sxthIop) 327 decoder_output += RegImmRegOpConstructor.subst(sxthIop) 328 exec_output += PredOpExecute.subst(sxthIop) 329 330 sxtahCode = ''' 331 uint64_t rotated = (uint32_t)Op2; 332 rotated = (rotated | (rotated << 32)) >> imm; 333 Dest = sext<16>((uint16_t)rotated) + Op1; 334 ''' 335 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 336 { "code": sxtahCode, 337 "predicate_test": predicateTest }, []) 338 header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 339 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 340 exec_output += PredOpExecute.subst(sxtahIop) 341 342 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 343 { "code": "Dest = (uint8_t)(Op1.ud >> imm);", 344 "predicate_test": predicateTest }, []) 345 header_output += RegImmRegOpDeclare.subst(uxtbIop) 346 decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 347 exec_output += PredOpExecute.subst(uxtbIop) 348 349 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 350 { "code": 351 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;", 352 "predicate_test": predicateTest }, []) 353 header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 354 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 355 exec_output += PredOpExecute.subst(uxtabIop) 356 357 uxtb16Code = ''' 358 uint32_t resTemp = 0; 359 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 360 replaceBits(resTemp, 31, 16, 361 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 362 Dest = resTemp; 363 ''' 364 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 365 { "code": uxtb16Code, 366 "predicate_test": predicateTest }, []) 367 header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 368 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 369 exec_output += PredOpExecute.subst(uxtb16Iop) 370 371 uxtab16Code = ''' 372 uint32_t resTemp = 0; 373 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 374 bits(Op1, 15, 0)); 375 replaceBits(resTemp, 31, 16, 376 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 377 bits(Op1, 31, 16)); 378 Dest = resTemp; 379 ''' 380 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 381 { "code": uxtab16Code, 382 "predicate_test": predicateTest }, []) 383 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 384 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 385 exec_output += PredOpExecute.subst(uxtab16Iop) 386 387 uxthCode = ''' 388 uint64_t rotated = (uint32_t)Op1; 389 rotated = (rotated | (rotated << 32)) >> imm; 390 Dest = (uint16_t)rotated; 391 ''' 392 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 393 { "code": uxthCode, 394 "predicate_test": predicateTest }, []) 395 header_output += RegImmRegOpDeclare.subst(uxthIop) 396 decoder_output += RegImmRegOpConstructor.subst(uxthIop) 397 exec_output += PredOpExecute.subst(uxthIop) 398 399 uxtahCode = ''' 400 uint64_t rotated = (uint32_t)Op2; 401 rotated = (rotated | (rotated << 32)) >> imm; 402 Dest = (uint16_t)rotated + Op1; 403 ''' 404 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 405 { "code": uxtahCode, 406 "predicate_test": predicateTest }, []) 407 header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 408 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 409 exec_output += PredOpExecute.subst(uxtahIop) 410 411 selCode = ''' 412 uint32_t resTemp = 0; 413 for (unsigned i = 0; i < 4; i++) { 414 int low = i * 8; 415 int high = low + 7; 416 replaceBits(resTemp, high, low, 417 bits(CondCodes, 16 + i) ? 418 bits(Op1, high, low) : bits(Op2, high, low)); 419 } 420 Dest = resTemp; 421 ''' 422 selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 423 { "code": selCode, 424 "predicate_test": condPredicateTest }, []) 425 header_output += RegRegRegOpDeclare.subst(selIop) 426 decoder_output += RegRegRegOpConstructor.subst(selIop) 427 exec_output += PredOpExecute.subst(selIop) 428 429 usad8Code = ''' 430 uint32_t resTemp = 0; 431 for (unsigned i = 0; i < 4; i++) { 432 int low = i * 8; 433 int high = low + 7; 434 int32_t diff = bits(Op1, high, low) - 435 bits(Op2, high, low); 436 resTemp += ((diff < 0) ? -diff : diff); 437 } 438 Dest = resTemp; 439 ''' 440 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 441 { "code": usad8Code, 442 "predicate_test": predicateTest }, []) 443 header_output += RegRegRegOpDeclare.subst(usad8Iop) 444 decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 445 exec_output += PredOpExecute.subst(usad8Iop) 446 447 usada8Code = ''' 448 uint32_t resTemp = 0; 449 for (unsigned i = 0; i < 4; i++) { 450 int low = i * 8; 451 int high = low + 7; 452 int32_t diff = bits(Op1, high, low) - 453 bits(Op2, high, low); 454 resTemp += ((diff < 0) ? -diff : diff); 455 } 456 Dest = Op3 + resTemp; 457 ''' 458 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 459 { "code": usada8Code, 460 "predicate_test": predicateTest }, []) 461 header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 462 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 463 exec_output += PredOpExecute.subst(usada8Iop) 464 465 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst", 466 "return new PrefetchAbort(PC, ArmFault::DebugEvent);") 467 header_output += BasicDeclare.subst(bkptIop) 468 decoder_output += BasicConstructor.subst(bkptIop) 469 exec_output += BasicExecute.subst(bkptIop) 470 471 nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 472 { "code" : "", "predicate_test" : predicateTest }) 473 header_output += BasicDeclare.subst(nopIop) 474 decoder_output += BasicConstructor.subst(nopIop) 475 exec_output += PredOpExecute.subst(nopIop) 476 477 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 478 { "code" : "", "predicate_test" : predicateTest }) 479 header_output += BasicDeclare.subst(yieldIop) 480 decoder_output += BasicConstructor.subst(yieldIop) 481 exec_output += PredOpExecute.subst(yieldIop) 482 483 wfeCode = ''' 484#if FULL_SYSTEM 485 if (SevMailbox) 486 SevMailbox = 0; 487 else 488 PseudoInst::quiesce(xc->tcBase()); 489#endif 490 ''' 491 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 492 { "code" : wfeCode, "predicate_test" : predicateTest }, 493 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 494 header_output += BasicDeclare.subst(wfeIop) 495 decoder_output += BasicConstructor.subst(wfeIop) 496 exec_output += PredOpExecute.subst(wfeIop) 497 498 wfiCode = ''' 499#if FULL_SYSTEM 500 PseudoInst::quiesce(xc->tcBase()); 501#endif 502 ''' 503 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 504 { "code" : wfiCode, "predicate_test" : predicateTest }, 505 ["IsNonSpeculative", "IsQuiesce"]) 506 header_output += BasicDeclare.subst(wfiIop) 507 decoder_output += BasicConstructor.subst(wfiIop) 508 exec_output += PredOpExecute.subst(wfiIop) 509 510 sevCode = ''' 511 // Need a way for O3 to not scoreboard these accesses as pipe flushes. 512 System *sys = xc->tcBase()->getSystemPtr(); 513 for (int x = 0; x < sys->numContexts(); x++) { 514 ThreadContext *oc = sys->getThreadContext(x); 515 oc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 516 } 517 ''' 518 sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 519 { "code" : sevCode, "predicate_test" : predicateTest }, 520 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 521 header_output += BasicDeclare.subst(sevIop) 522 decoder_output += BasicConstructor.subst(sevIop) 523 exec_output += PredOpExecute.subst(sevIop) 524 525 itIop = InstObjParams("it", "ItInst", "PredOp", \ 526 { "code" : "Itstate = machInst.newItstate;", 527 "predicate_test" : predicateTest }, 528 ["IsNonSpeculative", "IsSerializeAfter"]) 529 header_output += BasicDeclare.subst(itIop) 530 decoder_output += BasicConstructor.subst(itIop) 531 exec_output += PredOpExecute.subst(itIop) 532 unknownCode = ''' 533#if FULL_SYSTEM 534 return new UndefinedInstruction; 535#else 536 return new UndefinedInstruction(machInst, true); 537#endif 538 ''' 539 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 540 { "code": unknownCode, 541 "predicate_test": predicateTest }) 542 header_output += BasicDeclare.subst(unknownIop) 543 decoder_output += BasicConstructor.subst(unknownIop) 544 exec_output += PredOpExecute.subst(unknownIop) 545 546 ubfxCode = ''' 547 Dest = bits(Op1, imm2, imm1); 548 ''' 549 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 550 { "code": ubfxCode, 551 "predicate_test": predicateTest }, []) 552 header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 553 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 554 exec_output += PredOpExecute.subst(ubfxIop) 555 556 sbfxCode = ''' 557 int32_t resTemp = bits(Op1, imm2, imm1); 558 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 559 ''' 560 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 561 { "code": sbfxCode, 562 "predicate_test": predicateTest }, []) 563 header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 564 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 565 exec_output += PredOpExecute.subst(sbfxIop) 566 567 bfcCode = ''' 568 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 569 ''' 570 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 571 { "code": bfcCode, 572 "predicate_test": predicateTest }, []) 573 header_output += RegRegImmImmOpDeclare.subst(bfcIop) 574 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 575 exec_output += PredOpExecute.subst(bfcIop) 576 577 bfiCode = ''' 578 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 579 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 580 ''' 581 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 582 { "code": bfiCode, 583 "predicate_test": predicateTest }, []) 584 header_output += RegRegImmImmOpDeclare.subst(bfiIop) 585 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 586 exec_output += PredOpExecute.subst(bfiIop) 587 588 mrc15code = ''' 589 CPSR cpsr = Cpsr; 590 if (cpsr.mode == MODE_USER) 591#if FULL_SYSTEM 592 return new UndefinedInstruction; 593#else 594 return new UndefinedInstruction(false, mnemonic); 595#endif 596 Dest = MiscOp1; 597 ''' 598 599 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 600 { "code": mrc15code, 601 "predicate_test": predicateTest }, []) 602 header_output += RegRegOpDeclare.subst(mrc15Iop) 603 decoder_output += RegRegOpConstructor.subst(mrc15Iop) 604 exec_output += PredOpExecute.subst(mrc15Iop) 605 606 607 mcr15code = ''' 608 CPSR cpsr = Cpsr; 609 if (cpsr.mode == MODE_USER) 610#if FULL_SYSTEM 611 return new UndefinedInstruction; 612#else 613 return new UndefinedInstruction(false, mnemonic); 614#endif 615 MiscDest = Op1; 616 ''' 617 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 618 { "code": mcr15code, 619 "predicate_test": predicateTest }, 620 ["IsSerializeAfter","IsNonSpeculative"]) 621 header_output += RegRegOpDeclare.subst(mcr15Iop) 622 decoder_output += RegRegOpConstructor.subst(mcr15Iop) 623 exec_output += PredOpExecute.subst(mcr15Iop) 624 625 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 626 { "code": "Dest = MiscOp1;", 627 "predicate_test": predicateTest }, []) 628 header_output += RegRegOpDeclare.subst(mrc15UserIop) 629 decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 630 exec_output += PredOpExecute.subst(mrc15UserIop) 631 632 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 633 { "code": "MiscDest = Op1", 634 "predicate_test": predicateTest }, 635 ["IsSerializeAfter","IsNonSpeculative"]) 636 header_output += RegRegOpDeclare.subst(mcr15UserIop) 637 decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 638 exec_output += PredOpExecute.subst(mcr15UserIop) 639 640 enterxCode = ''' 641 FNPC = NPC | PcJBit | PcTBit; 642 ''' 643 enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 644 { "code": enterxCode, 645 "predicate_test": predicateTest }, []) 646 header_output += BasicDeclare.subst(enterxIop) 647 decoder_output += BasicConstructor.subst(enterxIop) 648 exec_output += PredOpExecute.subst(enterxIop) 649 650 leavexCode = ''' 651 FNPC = (NPC & ~PcJBit) | PcTBit; 652 ''' 653 leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 654 { "code": leavexCode, 655 "predicate_test": predicateTest }, []) 656 header_output += BasicDeclare.subst(leavexIop) 657 decoder_output += BasicConstructor.subst(leavexIop) 658 exec_output += PredOpExecute.subst(leavexIop) 659 660 setendCode = ''' 661 CPSR cpsr = Cpsr; 662 cpsr.e = imm; 663 Cpsr = cpsr; 664 ''' 665 setendIop = InstObjParams("setend", "Setend", "ImmOp", 666 { "code": setendCode, 667 "predicate_test": predicateTest }, 668 ["IsSerializeAfter","IsNonSpeculative"]) 669 header_output += ImmOpDeclare.subst(setendIop) 670 decoder_output += ImmOpConstructor.subst(setendIop) 671 exec_output += PredOpExecute.subst(setendIop) 672 673 clrexCode = ''' 674 unsigned memAccessFlags = Request::CLEAR_LL | 675 ArmISA::TLB::AlignWord | Request::LLSC; 676 fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); 677 ''' 678 clrexIop = InstObjParams("clrex", "Clrex","PredOp", 679 { "code": clrexCode, 680 "predicate_test": predicateTest },[]) 681 header_output += ClrexDeclare.subst(clrexIop) 682 decoder_output += BasicConstructor.subst(clrexIop) 683 exec_output += PredOpExecute.subst(clrexIop) 684 exec_output += ClrexInitiateAcc.subst(clrexIop) 685 exec_output += ClrexCompleteAcc.subst(clrexIop) 686 687 isbCode = ''' 688 ''' 689 isbIop = InstObjParams("isb", "Isb", "PredOp", 690 {"code": isbCode, 691 "predicate_test": predicateTest}, ['IsSerializing']) 692 header_output += BasicDeclare.subst(isbIop) 693 decoder_output += BasicConstructor.subst(isbIop) 694 exec_output += PredOpExecute.subst(isbIop) 695 696 dsbCode = ''' 697 ''' 698 dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 699 {"code": dsbCode, 700 "predicate_test": predicateTest},['IsMemBarrier']) 701 header_output += BasicDeclare.subst(dsbIop) 702 decoder_output += BasicConstructor.subst(dsbIop) 703 exec_output += PredOpExecute.subst(dsbIop) 704 705 dmbCode = ''' 706 ''' 707 dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 708 {"code": dmbCode, 709 "predicate_test": predicateTest},['IsMemBarrier']) 710 header_output += BasicDeclare.subst(dmbIop) 711 decoder_output += BasicConstructor.subst(dmbIop) 712 exec_output += PredOpExecute.subst(dmbIop) 713 714 dbgCode = ''' 715 ''' 716 dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 717 {"code": dbgCode, 718 "predicate_test": predicateTest}) 719 header_output += BasicDeclare.subst(dbgIop) 720 decoder_output += BasicConstructor.subst(dbgIop) 721 exec_output += PredOpExecute.subst(dbgIop) 722 723 cpsCode = ''' 724 uint32_t mode = bits(imm, 4, 0); 725 uint32_t f = bits(imm, 5); 726 uint32_t i = bits(imm, 6); 727 uint32_t a = bits(imm, 7); 728 bool setMode = bits(imm, 8); 729 bool enable = bits(imm, 9); 730 CPSR cpsr = Cpsr; 731 SCTLR sctlr = Sctlr; 732 if (cpsr.mode != MODE_USER) { 733 if (enable) { 734 if (f) cpsr.f = 0; 735 if (i) cpsr.i = 0; 736 if (a) cpsr.a = 0; 737 } else { 738 if (f && !sctlr.nmfi) cpsr.f = 1; 739 if (i) cpsr.i = 1; 740 if (a) cpsr.a = 1; 741 } 742 if (setMode) { 743 cpsr.mode = mode; 744 } 745 } 746 Cpsr = cpsr; 747 ''' 748 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 749 { "code": cpsCode, 750 "predicate_test": predicateTest }, 751 ["IsSerializeAfter","IsNonSpeculative"]) 752 header_output += ImmOpDeclare.subst(cpsIop) 753 decoder_output += ImmOpConstructor.subst(cpsIop) 754 exec_output += PredOpExecute.subst(cpsIop) 755}}; 756