misc.isa revision 8733
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 37199Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 437199Sgblack@eecs.umich.edu#if FULL_SYSTEM 447199Sgblack@eecs.umich.edu fault = new SupervisorCall; 457199Sgblack@eecs.umich.edu#else 467199Sgblack@eecs.umich.edu fault = new SupervisorCall(machInst); 477199Sgblack@eecs.umich.edu#endif 487199Sgblack@eecs.umich.edu ''' 497199Sgblack@eecs.umich.edu 507199Sgblack@eecs.umich.edu svcIop = InstObjParams("svc", "Svc", "PredOp", 517199Sgblack@eecs.umich.edu { "code": svcCode, 527199Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 537199Sgblack@eecs.umich.edu ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"]) 547199Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(svcIop) 557199Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(svcIop) 567199Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(svcIop) 577199Sgblack@eecs.umich.edu 587202Sgblack@eecs.umich.edu}}; 597202Sgblack@eecs.umich.edu 607202Sgblack@eecs.umich.edulet {{ 617202Sgblack@eecs.umich.edu 627202Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 637202Sgblack@eecs.umich.edu 647202Sgblack@eecs.umich.edu mrsCpsrCode = ''' 657202Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 667599Sminkyu.jeong@arm.com cpsr.nz = CondCodesNZ; 677783SGiacomo.Gabrielli@arm.com cpsr.c = CondCodesC; 687202Sgblack@eecs.umich.edu cpsr.v = CondCodesV; 697202Sgblack@eecs.umich.edu cpsr.ge = CondCodesGE; 707202Sgblack@eecs.umich.edu Dest = cpsr & 0xF8FF03DF 717202Sgblack@eecs.umich.edu ''' 727202Sgblack@eecs.umich.edu 737202Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 747202Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 757599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 767783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 777202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 787202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 797202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 807202Sgblack@eecs.umich.edu 817202Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 827400SAli.Saidi@ARM.com mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 837202Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 847400SAli.Saidi@ARM.com "predicate_test": predicateTest }, 857202Sgblack@eecs.umich.edu ["IsSerializeBefore"]) 867797Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 877797Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 887858SMatt.Horsnell@arm.com exec_output += PredOpExecute.subst(mrsSpsrIop) 897858SMatt.Horsnell@arm.com 907202Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 917202Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 927202Sgblack@eecs.umich.edu CPSR old_cpsr = Cpsr; 937202Sgblack@eecs.umich.edu old_cpsr.nz = CondCodesNZ; 947599Sminkyu.jeong@arm.com old_cpsr.c = CondCodesC; 957599Sminkyu.jeong@arm.com old_cpsr.v = CondCodesV; 967202Sgblack@eecs.umich.edu old_cpsr.ge = CondCodesGE; 977202Sgblack@eecs.umich.edu 987202Sgblack@eecs.umich.edu CPSR new_cpsr = 997202Sgblack@eecs.umich.edu cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi); 1007202Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & new_cpsr; 1017202Sgblack@eecs.umich.edu CondCodesNZ = new_cpsr.nz; 1027202Sgblack@eecs.umich.edu CondCodesC = new_cpsr.c; 1037599Sminkyu.jeong@arm.com CondCodesV = new_cpsr.v; 1047599Sminkyu.jeong@arm.com CondCodesGE = new_cpsr.ge; 1057202Sgblack@eecs.umich.edu ''' 1067202Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 1077202Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 1087202Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 1097202Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 1107400SAli.Saidi@ARM.com header_output += MsrRegDeclare.subst(msrCpsrRegIop) 1117202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 1127400SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(msrCpsrRegIop) 1137202Sgblack@eecs.umich.edu 1147797Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 1157797Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 1167858SMatt.Horsnell@arm.com { "code": msrSpsrRegCode, 1177858SMatt.Horsnell@arm.com "predicate_test": predicateTest }, 1187202Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 1197202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 1207202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 1217202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 1227599Sminkyu.jeong@arm.com 1237599Sminkyu.jeong@arm.com msrCpsrImmCode = ''' 1247202Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 1257202Sgblack@eecs.umich.edu CPSR old_cpsr = Cpsr; 1267202Sgblack@eecs.umich.edu old_cpsr.nz = CondCodesNZ; 1277202Sgblack@eecs.umich.edu old_cpsr.c = CondCodesC; 1287202Sgblack@eecs.umich.edu old_cpsr.v = CondCodesV; 1297202Sgblack@eecs.umich.edu old_cpsr.ge = CondCodesGE; 1307202Sgblack@eecs.umich.edu CPSR new_cpsr = 1317599Sminkyu.jeong@arm.com cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi); 1327599Sminkyu.jeong@arm.com Cpsr = ~CondCodesMask & new_cpsr; 1337202Sgblack@eecs.umich.edu CondCodesNZ = new_cpsr.nz; 1347202Sgblack@eecs.umich.edu CondCodesC = new_cpsr.c; 1357202Sgblack@eecs.umich.edu CondCodesV = new_cpsr.v; 1367209Sgblack@eecs.umich.edu CondCodesGE = new_cpsr.ge; 1377209Sgblack@eecs.umich.edu ''' 1387209Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 1397209Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 1407209Sgblack@eecs.umich.edu "predicate_test": condPredicateTest }, 1417261Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 1427209Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 1437209Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 1447261Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 1457261Sgblack@eecs.umich.edu 1467209Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 1477209Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 1487209Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 1497209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 1507209Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 1517209Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 1527209Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 1537209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 1547209Sgblack@eecs.umich.edu 1557261Sgblack@eecs.umich.edu revCode = ''' 1567209Sgblack@eecs.umich.edu uint32_t val = Op1; 1577209Sgblack@eecs.umich.edu Dest = swap_byte(val); 1587261Sgblack@eecs.umich.edu ''' 1597261Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 1607209Sgblack@eecs.umich.edu { "code": revCode, 1617209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1627209Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 1637209Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 1647209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 1657209Sgblack@eecs.umich.edu 1667261Sgblack@eecs.umich.edu rev16Code = ''' 1677209Sgblack@eecs.umich.edu uint32_t val = Op1; 1687209Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 1697261Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 1707261Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 1717209Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 1727226Sgblack@eecs.umich.edu ''' 1737249Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 1747249Sgblack@eecs.umich.edu { "code": rev16Code, 1757249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1767249Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 1777249Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 1787249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 1797249Sgblack@eecs.umich.edu 1807249Sgblack@eecs.umich.edu revshCode = ''' 1817249Sgblack@eecs.umich.edu uint16_t val = Op1; 1827249Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 1837249Sgblack@eecs.umich.edu ''' 1847249Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 1857249Sgblack@eecs.umich.edu { "code": revshCode, 1867261Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1877249Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 1887249Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 1897261Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 1907261Sgblack@eecs.umich.edu 1917249Sgblack@eecs.umich.edu rbitCode = ''' 1927249Sgblack@eecs.umich.edu uint8_t *opBytes = (uint8_t *)&Op1; 1937251Sgblack@eecs.umich.edu uint32_t resTemp; 1947251Sgblack@eecs.umich.edu uint8_t *destBytes = (uint8_t *)&resTemp; 1957251Sgblack@eecs.umich.edu // This reverses the bytes and bits of the input, or so says the 1967261Sgblack@eecs.umich.edu // internet. 1977251Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1987251Sgblack@eecs.umich.edu uint32_t temp = opBytes[i]; 1997261Sgblack@eecs.umich.edu temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 2007261Sgblack@eecs.umich.edu destBytes[3 - i] = (temp * 0x10101) >> 16; 2017251Sgblack@eecs.umich.edu } 2027251Sgblack@eecs.umich.edu Dest = resTemp; 2037226Sgblack@eecs.umich.edu ''' 2047226Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 2057226Sgblack@eecs.umich.edu { "code": rbitCode, 2067232Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2077226Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 2087226Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 2097226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 2107226Sgblack@eecs.umich.edu 2117226Sgblack@eecs.umich.edu clzCode = ''' 2127232Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 2137226Sgblack@eecs.umich.edu ''' 2147422Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 2157232Sgblack@eecs.umich.edu { "code": clzCode, 2167232Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2177226Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 2187226Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 2197226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 2207226Sgblack@eecs.umich.edu 2217226Sgblack@eecs.umich.edu ssatCode = ''' 2227232Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2237226Sgblack@eecs.umich.edu int32_t res; 2247226Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 2257226Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 2267226Sgblack@eecs.umich.edu Dest = res; 2277226Sgblack@eecs.umich.edu ''' 2287232Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 2297226Sgblack@eecs.umich.edu { "code": ssatCode, 2307422Sgblack@eecs.umich.edu "predicate_test": pickPredicate(ssatCode) }, []) 2317232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 2327232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 2337226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 2347226Sgblack@eecs.umich.edu 2357226Sgblack@eecs.umich.edu usatCode = ''' 2367226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2377226Sgblack@eecs.umich.edu int32_t res; 2387226Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 2397226Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 2407226Sgblack@eecs.umich.edu Dest = res; 2417232Sgblack@eecs.umich.edu ''' 2427226Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 2437226Sgblack@eecs.umich.edu { "code": usatCode, 2447232Sgblack@eecs.umich.edu "predicate_test": pickPredicate(usatCode) }, []) 2457226Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 2467226Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 2477226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 2487226Sgblack@eecs.umich.edu 2497232Sgblack@eecs.umich.edu ssat16Code = ''' 2507226Sgblack@eecs.umich.edu int32_t res; 2517422Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2527232Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2537232Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2547226Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 2557226Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 2567226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2577226Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 2587226Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 2597226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2607226Sgblack@eecs.umich.edu Dest = resTemp; 2617226Sgblack@eecs.umich.edu ''' 2627232Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 2637226Sgblack@eecs.umich.edu { "code": ssat16Code, 2647226Sgblack@eecs.umich.edu "predicate_test": pickPredicate(ssat16Code) }, []) 2657232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 2667226Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 2677226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 2687226Sgblack@eecs.umich.edu 2697226Sgblack@eecs.umich.edu usat16Code = ''' 2707232Sgblack@eecs.umich.edu int32_t res; 2717226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2727422Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2737232Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2747232Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 2757226Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 2767234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2777234Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 2787234Sgblack@eecs.umich.edu CpsrQ = 1 << 27; 2797234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2807234Sgblack@eecs.umich.edu Dest = resTemp; 2817234Sgblack@eecs.umich.edu ''' 2827234Sgblack@eecs.umich.edu usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 2837234Sgblack@eecs.umich.edu { "code": usat16Code, 2847234Sgblack@eecs.umich.edu "predicate_test": pickPredicate(usat16Code) }, []) 2857234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 2867234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 2877234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 2887234Sgblack@eecs.umich.edu 2897234Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 2907234Sgblack@eecs.umich.edu { "code": 2917234Sgblack@eecs.umich.edu "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", 2927234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2937234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 2947234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 2957234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 2967234Sgblack@eecs.umich.edu 2977234Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 2987234Sgblack@eecs.umich.edu { "code": 2997234Sgblack@eecs.umich.edu ''' 3007234Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + 3017234Sgblack@eecs.umich.edu Op1; 3027234Sgblack@eecs.umich.edu ''', 3037234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3047234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 3057234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 3067234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtabIop) 3077234Sgblack@eecs.umich.edu 3087234Sgblack@eecs.umich.edu sxtb16Code = ''' 3097234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3107234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 3117234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3127234Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3137234Sgblack@eecs.umich.edu Dest = resTemp; 3147234Sgblack@eecs.umich.edu ''' 3157234Sgblack@eecs.umich.edu sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 3167234Sgblack@eecs.umich.edu { "code": sxtb16Code, 3177234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3187234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 3197234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 3207234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 3217234Sgblack@eecs.umich.edu 3227234Sgblack@eecs.umich.edu sxtab16Code = ''' 3237234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3247234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 3257234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3267234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3277234Sgblack@eecs.umich.edu sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3287234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3297234Sgblack@eecs.umich.edu Dest = resTemp; 3307234Sgblack@eecs.umich.edu ''' 3317234Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 3327234Sgblack@eecs.umich.edu { "code": sxtab16Code, 3337234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3347234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 3357234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 3367234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 3377234Sgblack@eecs.umich.edu 3387234Sgblack@eecs.umich.edu sxthCode = ''' 3397234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3407234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3417234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 3427234Sgblack@eecs.umich.edu ''' 3437234Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 3447234Sgblack@eecs.umich.edu { "code": sxthCode, 3457234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3467234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 3477234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 3487234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 3497234Sgblack@eecs.umich.edu 3507234Sgblack@eecs.umich.edu sxtahCode = ''' 3517234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 3527234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3537234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 3547234Sgblack@eecs.umich.edu ''' 3557234Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 3567234Sgblack@eecs.umich.edu { "code": sxtahCode, 3577234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3587234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 3597234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 3607234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 3617234Sgblack@eecs.umich.edu 3627234Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 3637234Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1_ud >> imm);", 3647234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3657234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 3667234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 3677234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 3687234Sgblack@eecs.umich.edu 3697234Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 3707234Sgblack@eecs.umich.edu { "code": 3717234Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", 3727234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3737234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 3747234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 3757234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 3767234Sgblack@eecs.umich.edu 3777234Sgblack@eecs.umich.edu uxtb16Code = ''' 3787234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3797234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 3807234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3817234Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3827234Sgblack@eecs.umich.edu Dest = resTemp; 3837234Sgblack@eecs.umich.edu ''' 3847234Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 3857234Sgblack@eecs.umich.edu { "code": uxtb16Code, 3867234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3877234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 3887234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 3897234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 3907234Sgblack@eecs.umich.edu 3917234Sgblack@eecs.umich.edu uxtab16Code = ''' 3927234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3937234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 3947234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3957234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3967234Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3977234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3987234Sgblack@eecs.umich.edu Dest = resTemp; 3997234Sgblack@eecs.umich.edu ''' 4007234Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 4017234Sgblack@eecs.umich.edu { "code": uxtab16Code, 4027234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4037234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 4047234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 4057234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 4067234Sgblack@eecs.umich.edu 4077234Sgblack@eecs.umich.edu uxthCode = ''' 4087234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 4097234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4107234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 4117234Sgblack@eecs.umich.edu ''' 4127234Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 4137234Sgblack@eecs.umich.edu { "code": uxthCode, 4147234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4157234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 4167234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 4177234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 4187239Sgblack@eecs.umich.edu 4197239Sgblack@eecs.umich.edu uxtahCode = ''' 4207239Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 4217239Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4227239Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 4237239Sgblack@eecs.umich.edu ''' 4247239Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 4257239Sgblack@eecs.umich.edu { "code": uxtahCode, 4267239Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4277239Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 4287239Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 4297239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 4307239Sgblack@eecs.umich.edu 4317239Sgblack@eecs.umich.edu selCode = ''' 4327422Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4337239Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4347239Sgblack@eecs.umich.edu int low = i * 8; 4357239Sgblack@eecs.umich.edu int high = low + 7; 4367242Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 4377242Sgblack@eecs.umich.edu bits(CondCodesGE, i) ? 4387242Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 4397242Sgblack@eecs.umich.edu } 4407242Sgblack@eecs.umich.edu Dest = resTemp; 4417242Sgblack@eecs.umich.edu ''' 4427242Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 4437242Sgblack@eecs.umich.edu { "code": selCode, 4447242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4457242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 4467242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 4477242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 4487242Sgblack@eecs.umich.edu 4497242Sgblack@eecs.umich.edu usad8Code = ''' 4507242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4517242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4527242Sgblack@eecs.umich.edu int low = i * 8; 4537242Sgblack@eecs.umich.edu int high = low + 7; 4547242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4557242Sgblack@eecs.umich.edu bits(Op2, high, low); 4567242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4577242Sgblack@eecs.umich.edu } 4587242Sgblack@eecs.umich.edu Dest = resTemp; 4597242Sgblack@eecs.umich.edu ''' 4607242Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 4617242Sgblack@eecs.umich.edu { "code": usad8Code, 4627242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4637242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 4647242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 4657242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 4667242Sgblack@eecs.umich.edu 4677242Sgblack@eecs.umich.edu usada8Code = ''' 4687242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4697242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4707242Sgblack@eecs.umich.edu int low = i * 8; 4717242Sgblack@eecs.umich.edu int high = low + 7; 4727247Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4737797Sgblack@eecs.umich.edu bits(Op2, high, low); 4747848SAli.Saidi@ARM.com resTemp += ((diff < 0) ? -diff : diff); 4757410Sgblack@eecs.umich.edu } 4767410Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 4777410Sgblack@eecs.umich.edu ''' 4787410Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 4797408Sgblack@eecs.umich.edu { "code": usada8Code, 4808065SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 4818065SAli.Saidi@ARM.com header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 4827247Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 4837247Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 4847408Sgblack@eecs.umich.edu 4857408Sgblack@eecs.umich.edu bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 4867418Sgblack@eecs.umich.edu bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 4877418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 4887418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 4897418Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 4907418Sgblack@eecs.umich.edu 4917418Sgblack@eecs.umich.edu nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 4927418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }, 4937418Sgblack@eecs.umich.edu ['IsNop']) 4947418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 4957418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(nopIop) 4967418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(nopIop) 4977418Sgblack@eecs.umich.edu 4987418Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 4997418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 5007418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 5017418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(yieldIop) 5027648SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(yieldIop) 5037418Sgblack@eecs.umich.edu 5047418Sgblack@eecs.umich.edu wfeCode = ''' 5057418Sgblack@eecs.umich.edu#if FULL_SYSTEM 5067418Sgblack@eecs.umich.edu // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending 5077418Sgblack@eecs.umich.edu if (SevMailbox == 1) { 5087418Sgblack@eecs.umich.edu SevMailbox = 0; 5097418Sgblack@eecs.umich.edu PseudoInst::quiesceSkip(xc->tcBase()); 5107418Sgblack@eecs.umich.edu } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) { 5117418Sgblack@eecs.umich.edu PseudoInst::quiesceSkip(xc->tcBase()); 5127418Sgblack@eecs.umich.edu } else { 5137418Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 5147418Sgblack@eecs.umich.edu } 5157418Sgblack@eecs.umich.edu#endif 5167418Sgblack@eecs.umich.edu ''' 5177418Sgblack@eecs.umich.edu wfePredFixUpCode = ''' 5187418Sgblack@eecs.umich.edu#if FULL_SYSTEM 5197418Sgblack@eecs.umich.edu // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 5207418Sgblack@eecs.umich.edu // and SEV interrupts 5217418Sgblack@eecs.umich.edu SevMailbox = 1; 5227418Sgblack@eecs.umich.edu#endif 5237418Sgblack@eecs.umich.edu ''' 5247418Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 5257418Sgblack@eecs.umich.edu { "code" : wfeCode, 5267418Sgblack@eecs.umich.edu "pred_fixup" : wfePredFixUpCode, 5277418Sgblack@eecs.umich.edu "predicate_test" : predicateTest }, 5287418Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsQuiesce", 5297648SAli.Saidi@ARM.com "IsSerializeAfter", "IsUnverifiable"]) 5307418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 5317418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 5327418Sgblack@eecs.umich.edu exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 5337418Sgblack@eecs.umich.edu 5347408Sgblack@eecs.umich.edu wfiCode = ''' 5357408Sgblack@eecs.umich.edu#if FULL_SYSTEM 5367648SAli.Saidi@ARM.com // WFI doesn't sleep if interrupts are pending (masked or not) 5377648SAli.Saidi@ARM.com if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { 5387408Sgblack@eecs.umich.edu PseudoInst::quiesceSkip(xc->tcBase()); 5397408Sgblack@eecs.umich.edu } else { 5407408Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 5417409Sgblack@eecs.umich.edu } 5427409Sgblack@eecs.umich.edu#endif 5437409Sgblack@eecs.umich.edu ''' 5447409Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 5457409Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 5467409Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsQuiesce", 5477409Sgblack@eecs.umich.edu "IsSerializeAfter", "IsUnverifiable"]) 5487409Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 5497409Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 5507409Sgblack@eecs.umich.edu exec_output += QuiescePredOpExecute.subst(wfiIop) 5517409Sgblack@eecs.umich.edu 5527409Sgblack@eecs.umich.edu sevCode = ''' 5537409Sgblack@eecs.umich.edu#if FULL_SYSTEM 5547254Sgblack@eecs.umich.edu SevMailbox = 1; 5557254Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 5567254Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 5577254Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 5587254Sgblack@eecs.umich.edu if (oc == xc->tcBase()) 5597254Sgblack@eecs.umich.edu continue; 5607254Sgblack@eecs.umich.edu // Wake CPU with interrupt if they were sleeping 5617254Sgblack@eecs.umich.edu if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 5627254Sgblack@eecs.umich.edu // Post Interrupt and wake cpu if needed 5637254Sgblack@eecs.umich.edu oc->getCpuPtr()->postInterrupt(INT_SEV, 0); 5647254Sgblack@eecs.umich.edu } 5657254Sgblack@eecs.umich.edu } 5667254Sgblack@eecs.umich.edu#endif 5677254Sgblack@eecs.umich.edu ''' 5687254Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 5697254Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 5707254Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"]) 5717254Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 5727254Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 5737254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 5747254Sgblack@eecs.umich.edu 5757257Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 5767257Sgblack@eecs.umich.edu { "code" : ";", 5777257Sgblack@eecs.umich.edu "predicate_test" : predicateTest }, 5787257Sgblack@eecs.umich.edu ["IsNonSpeculative", "IsSerializeAfter"]) 5797257Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 5807257Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 5817257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 5827257Sgblack@eecs.umich.edu unknownCode = ''' 5837257Sgblack@eecs.umich.edu#if FULL_SYSTEM 5847257Sgblack@eecs.umich.edu return new UndefinedInstruction; 5857257Sgblack@eecs.umich.edu#else 5867257Sgblack@eecs.umich.edu return new UndefinedInstruction(machInst, true); 5877257Sgblack@eecs.umich.edu#endif 5887257Sgblack@eecs.umich.edu ''' 5897257Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 5907257Sgblack@eecs.umich.edu { "code": unknownCode, 5917257Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 5927257Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 5937257Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 5947257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 5957257Sgblack@eecs.umich.edu 5967262Sgblack@eecs.umich.edu ubfxCode = ''' 5977347SAli.Saidi@ARM.com Dest = bits(Op1, imm2, imm1); 5987347SAli.Saidi@ARM.com ''' 5997347SAli.Saidi@ARM.com ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 6007347SAli.Saidi@ARM.com { "code": ubfxCode, 6017347SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 6027347SAli.Saidi@ARM.com header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 6037347SAli.Saidi@ARM.com decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 6047347SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(ubfxIop) 6057347SAli.Saidi@ARM.com 6067347SAli.Saidi@ARM.com sbfxCode = ''' 6077347SAli.Saidi@ARM.com int32_t resTemp = bits(Op1, imm2, imm1); 6087262Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 6097347SAli.Saidi@ARM.com ''' 6107262Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 6117262Sgblack@eecs.umich.edu { "code": sbfxCode, 6127262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6137262Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 6147262Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 6157347SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(sbfxIop) 6167347SAli.Saidi@ARM.com 6177347SAli.Saidi@ARM.com bfcCode = ''' 6187347SAli.Saidi@ARM.com Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 6197347SAli.Saidi@ARM.com ''' 6207347SAli.Saidi@ARM.com bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 6217347SAli.Saidi@ARM.com { "code": bfcCode, 6227347SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 6237347SAli.Saidi@ARM.com header_output += RegRegImmImmOpDeclare.subst(bfcIop) 6247347SAli.Saidi@ARM.com decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 6257347SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(bfcIop) 6267262Sgblack@eecs.umich.edu 6277347SAli.Saidi@ARM.com bfiCode = ''' 6287599Sminkyu.jeong@arm.com uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 6297599Sminkyu.jeong@arm.com Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 6307262Sgblack@eecs.umich.edu ''' 6317262Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 6327262Sgblack@eecs.umich.edu { "code": bfiCode, 6337283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6347420Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 6357420Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 6367420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 6377420Sgblack@eecs.umich.edu 6387420Sgblack@eecs.umich.edu mrc15code = ''' 6397420Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 6407420Sgblack@eecs.umich.edu if (cpsr.mode == MODE_USER) 6417420Sgblack@eecs.umich.edu#if FULL_SYSTEM 6427420Sgblack@eecs.umich.edu return new UndefinedInstruction; 6437599Sminkyu.jeong@arm.com#else 6447599Sminkyu.jeong@arm.com return new UndefinedInstruction(false, mnemonic); 6457420Sgblack@eecs.umich.edu#endif 6467420Sgblack@eecs.umich.edu Dest = MiscOp1; 6477420Sgblack@eecs.umich.edu ''' 6487420Sgblack@eecs.umich.edu 6497283Sgblack@eecs.umich.edu mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 6507797Sgblack@eecs.umich.edu { "code": mrc15code, 6517797Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6527283Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15Iop) 6537283Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15Iop) 6547283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 6557283Sgblack@eecs.umich.edu 6567283Sgblack@eecs.umich.edu 6577283Sgblack@eecs.umich.edu mcr15code = ''' 6587283Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 6597283Sgblack@eecs.umich.edu if (cpsr.mode == MODE_USER) 6607283Sgblack@eecs.umich.edu#if FULL_SYSTEM 6617797Sgblack@eecs.umich.edu return new UndefinedInstruction; 6627797Sgblack@eecs.umich.edu#else 6637283Sgblack@eecs.umich.edu return new UndefinedInstruction(false, mnemonic); 6647283Sgblack@eecs.umich.edu#endif 6657283Sgblack@eecs.umich.edu MiscDest = Op1; 6667283Sgblack@eecs.umich.edu ''' 6677283Sgblack@eecs.umich.edu mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 6687283Sgblack@eecs.umich.edu { "code": mcr15code, 6697283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 6707307Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 6717307Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15Iop) 6727307Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15Iop) 6737307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 6747307Sgblack@eecs.umich.edu 6757307Sgblack@eecs.umich.edu mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 6767307Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 6777307Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6787648SAli.Saidi@ARM.com header_output += RegRegOpDeclare.subst(mrc15UserIop) 6797648SAli.Saidi@ARM.com decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 6807307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15UserIop) 6817307Sgblack@eecs.umich.edu 6827307Sgblack@eecs.umich.edu mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 6837315Sgblack@eecs.umich.edu { "code": "MiscDest = Op1", 6847603SGene.Wu@arm.com "predicate_test": predicateTest }, 6857705Sgblack@eecs.umich.edu ["IsSerializeAfter","IsNonSpeculative"]) 6867705Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15UserIop) 6877603SGene.Wu@arm.com decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 6887603SGene.Wu@arm.com exec_output += PredOpExecute.subst(mcr15UserIop) 6897603SGene.Wu@arm.com 6907603SGene.Wu@arm.com enterxCode = ''' 6917603SGene.Wu@arm.com NextThumb = true; 6927609SGene.Wu@arm.com NextJazelle = true; 6937603SGene.Wu@arm.com ''' 6947603SGene.Wu@arm.com enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 6957609SGene.Wu@arm.com { "code": enterxCode, 6967609SGene.Wu@arm.com "predicate_test": predicateTest }, []) 6977603SGene.Wu@arm.com header_output += BasicDeclare.subst(enterxIop) 6987605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(enterxIop) 6998068SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(enterxIop) 7007605SGene.Wu@arm.com 7017605SGene.Wu@arm.com leavexCode = ''' 7027605SGene.Wu@arm.com NextThumb = true; 7038068SAli.Saidi@ARM.com NextJazelle = false; 7048068SAli.Saidi@ARM.com ''' 7057605SGene.Wu@arm.com leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 7067605SGene.Wu@arm.com { "code": leavexCode, 7077605SGene.Wu@arm.com "predicate_test": predicateTest }, []) 7087605SGene.Wu@arm.com header_output += BasicDeclare.subst(leavexIop) 7097605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(leavexIop) 7108068SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(leavexIop) 7117605SGene.Wu@arm.com 7127605SGene.Wu@arm.com setendCode = ''' 7137605SGene.Wu@arm.com CPSR cpsr = Cpsr; 7148068SAli.Saidi@ARM.com cpsr.e = imm; 7158068SAli.Saidi@ARM.com Cpsr = cpsr; 7167605SGene.Wu@arm.com ''' 7177605SGene.Wu@arm.com setendIop = InstObjParams("setend", "Setend", "ImmOp", 7187605SGene.Wu@arm.com { "code": setendCode, 7197605SGene.Wu@arm.com "predicate_test": predicateTest }, 7207605SGene.Wu@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 7217605SGene.Wu@arm.com header_output += ImmOpDeclare.subst(setendIop) 7227605SGene.Wu@arm.com decoder_output += ImmOpConstructor.subst(setendIop) 7237605SGene.Wu@arm.com exec_output += PredOpExecute.subst(setendIop) 7248068SAli.Saidi@ARM.com 7258068SAli.Saidi@ARM.com clrexCode = ''' 7267605SGene.Wu@arm.com LLSCLock = 0; 7277605SGene.Wu@arm.com ''' 7287605SGene.Wu@arm.com clrexIop = InstObjParams("clrex", "Clrex","PredOp", 7297605SGene.Wu@arm.com { "code": clrexCode, 7307613SGene.Wu@arm.com "predicate_test": predicateTest },[]) 7317613SGene.Wu@arm.com header_output += BasicDeclare.subst(clrexIop) 7327613SGene.Wu@arm.com decoder_output += BasicConstructor.subst(clrexIop) 7337613SGene.Wu@arm.com exec_output += PredOpExecute.subst(clrexIop) 7347613SGene.Wu@arm.com 7357613SGene.Wu@arm.com isbCode = ''' 7367613SGene.Wu@arm.com fault = new FlushPipe; 7377613SGene.Wu@arm.com ''' 7387613SGene.Wu@arm.com isbIop = InstObjParams("isb", "Isb", "PredOp", 7397315Sgblack@eecs.umich.edu {"code": isbCode, 7407315Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 7417315Sgblack@eecs.umich.edu ['IsSerializeAfter']) 7427315Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(isbIop) 7437315Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(isbIop) 7447315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(isbIop) 7457315Sgblack@eecs.umich.edu 7467315Sgblack@eecs.umich.edu dsbCode = ''' 7477400SAli.Saidi@ARM.com fault = new FlushPipe; 7487315Sgblack@eecs.umich.edu ''' 7497315Sgblack@eecs.umich.edu dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 7507315Sgblack@eecs.umich.edu {"code": dsbCode, 7517315Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 7527315Sgblack@eecs.umich.edu ['IsMemBarrier', 'IsSerializeAfter']) 7537315Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(dsbIop) 7547400SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dsbIop) 7557315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(dsbIop) 7567315Sgblack@eecs.umich.edu 7577315Sgblack@eecs.umich.edu dmbCode = ''' 7587315Sgblack@eecs.umich.edu ''' 7597315Sgblack@eecs.umich.edu dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 7607315Sgblack@eecs.umich.edu {"code": dmbCode, 7617315Sgblack@eecs.umich.edu "predicate_test": predicateTest}, 7627315Sgblack@eecs.umich.edu ['IsMemBarrier']) 7637315Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(dmbIop) 7647315Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(dmbIop) 7657315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(dmbIop) 7667599Sminkyu.jeong@arm.com 7677599Sminkyu.jeong@arm.com dbgCode = ''' 7687315Sgblack@eecs.umich.edu ''' 7697315Sgblack@eecs.umich.edu dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 7707315Sgblack@eecs.umich.edu {"code": dbgCode, 7717202Sgblack@eecs.umich.edu "predicate_test": predicateTest}) 772 header_output += BasicDeclare.subst(dbgIop) 773 decoder_output += BasicConstructor.subst(dbgIop) 774 exec_output += PredOpExecute.subst(dbgIop) 775 776 cpsCode = ''' 777 uint32_t mode = bits(imm, 4, 0); 778 uint32_t f = bits(imm, 5); 779 uint32_t i = bits(imm, 6); 780 uint32_t a = bits(imm, 7); 781 bool setMode = bits(imm, 8); 782 bool enable = bits(imm, 9); 783 CPSR cpsr = Cpsr; 784 SCTLR sctlr = Sctlr; 785 if (cpsr.mode != MODE_USER) { 786 if (enable) { 787 if (f) cpsr.f = 0; 788 if (i) cpsr.i = 0; 789 if (a) cpsr.a = 0; 790 } else { 791 if (f && !sctlr.nmfi) cpsr.f = 1; 792 if (i) cpsr.i = 1; 793 if (a) cpsr.a = 1; 794 } 795 if (setMode) { 796 cpsr.mode = mode; 797 } 798 } 799 Cpsr = cpsr; 800 ''' 801 cpsIop = InstObjParams("cps", "Cps", "ImmOp", 802 { "code": cpsCode, 803 "predicate_test": predicateTest }, 804 ["IsSerializeAfter","IsNonSpeculative"]) 805 header_output += ImmOpDeclare.subst(cpsIop) 806 decoder_output += ImmOpConstructor.subst(cpsIop) 807 exec_output += PredOpExecute.subst(cpsIop) 808}}; 809