misc.isa revision 8628
17199Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27199Sgblack@eecs.umich.edu 37199Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47199Sgblack@eecs.umich.edu// All rights reserved 57199Sgblack@eecs.umich.edu// 67199Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77199Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87199Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97199Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107199Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117199Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127199Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137199Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147199Sgblack@eecs.umich.edu// 157199Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167199Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177199Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197199Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207199Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217199Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227199Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237199Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247199Sgblack@eecs.umich.edu// this software without specific prior written permission. 257199Sgblack@eecs.umich.edu// 267199Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277199Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287199Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297199Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307199Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317199Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327199Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337199Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347199Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357199Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367199Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377199Sgblack@eecs.umich.edu// 387199Sgblack@eecs.umich.edu// Authors: Gabe Black 397199Sgblack@eecs.umich.edu 407199Sgblack@eecs.umich.edulet {{ 417199Sgblack@eecs.umich.edu 427199Sgblack@eecs.umich.edu svcCode = ''' 437199Sgblack@eecs.umich.edu#if FULL_SYSTEM 447199Sgblack@eecs.umich.edu fault = new SupervisorCall; 457199Sgblack@eecs.umich.edu#else 467199Sgblack@eecs.umich.edu fault = new SupervisorCall(machInst); 477199Sgblack@eecs.umich.edu#endif 487199Sgblack@eecs.umich.edu ''' 497199Sgblack@eecs.umich.edu 507199Sgblack@eecs.umich.edu svcIop = InstObjParams("svc", "Svc", "PredOp", 517199Sgblack@eecs.umich.edu { "code": svcCode, 528628SAli.Saidi@ARM.com "predicate_test": predicateTest }, 538628SAli.Saidi@ARM.com ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"]) 547199Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(svcIop) 557199Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(svcIop) 567199Sgblack@eecs.umich.edu exec_output = PredOpExecute.subst(svcIop) 577199Sgblack@eecs.umich.edu 587199Sgblack@eecs.umich.edu}}; 597202Sgblack@eecs.umich.edu 607202Sgblack@eecs.umich.edulet {{ 617202Sgblack@eecs.umich.edu 627202Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = "" 637202Sgblack@eecs.umich.edu 648301SAli.Saidi@ARM.com mrsCpsrCode = ''' 658303SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 668303SAli.Saidi@ARM.com cpsr.nz = CondCodesNZ; 678303SAli.Saidi@ARM.com cpsr.c = CondCodesC; 688303SAli.Saidi@ARM.com cpsr.v = CondCodesV; 698303SAli.Saidi@ARM.com cpsr.ge = CondCodesGE; 708303SAli.Saidi@ARM.com Dest = cpsr & 0xF8FF03DF 718301SAli.Saidi@ARM.com ''' 728301SAli.Saidi@ARM.com 737202Sgblack@eecs.umich.edu mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", 747202Sgblack@eecs.umich.edu { "code": mrsCpsrCode, 757599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 767783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 777202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsCpsrIop) 787202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsCpsrIop) 797202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsCpsrIop) 807202Sgblack@eecs.umich.edu 817202Sgblack@eecs.umich.edu mrsSpsrCode = "Dest = Spsr" 827202Sgblack@eecs.umich.edu mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp", 837202Sgblack@eecs.umich.edu { "code": mrsSpsrCode, 847599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 857783SGiacomo.Gabrielli@arm.com ["IsSerializeBefore"]) 867202Sgblack@eecs.umich.edu header_output += MrsDeclare.subst(mrsSpsrIop) 877202Sgblack@eecs.umich.edu decoder_output += MrsConstructor.subst(mrsSpsrIop) 887202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrsSpsrIop) 897202Sgblack@eecs.umich.edu 907202Sgblack@eecs.umich.edu msrCpsrRegCode = ''' 917400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 928303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 938303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 948303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 958303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 968303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 978303SAli.Saidi@ARM.com 988303SAli.Saidi@ARM.com CPSR new_cpsr = 998303SAli.Saidi@ARM.com cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi); 1008303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 1018303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 1028303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 1038303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 1048303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 1057202Sgblack@eecs.umich.edu ''' 1067202Sgblack@eecs.umich.edu msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", 1077202Sgblack@eecs.umich.edu { "code": msrCpsrRegCode, 1087599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 1097599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1107202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrCpsrRegIop) 1117202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrCpsrRegIop) 1127202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrRegIop) 1137202Sgblack@eecs.umich.edu 1147202Sgblack@eecs.umich.edu msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);" 1157202Sgblack@eecs.umich.edu msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp", 1167202Sgblack@eecs.umich.edu { "code": msrSpsrRegCode, 1177599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1187599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1197202Sgblack@eecs.umich.edu header_output += MsrRegDeclare.subst(msrSpsrRegIop) 1207202Sgblack@eecs.umich.edu decoder_output += MsrRegConstructor.subst(msrSpsrRegIop) 1217202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrRegIop) 1227202Sgblack@eecs.umich.edu 1237202Sgblack@eecs.umich.edu msrCpsrImmCode = ''' 1247400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 1258303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 1268303SAli.Saidi@ARM.com old_cpsr.nz = CondCodesNZ; 1278303SAli.Saidi@ARM.com old_cpsr.c = CondCodesC; 1288303SAli.Saidi@ARM.com old_cpsr.v = CondCodesV; 1298303SAli.Saidi@ARM.com old_cpsr.ge = CondCodesGE; 1308303SAli.Saidi@ARM.com CPSR new_cpsr = 1318303SAli.Saidi@ARM.com cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi); 1328303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 1338303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 1348303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 1358303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 1368303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 1377202Sgblack@eecs.umich.edu ''' 1387202Sgblack@eecs.umich.edu msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", 1397202Sgblack@eecs.umich.edu { "code": msrCpsrImmCode, 1407599Sminkyu.jeong@arm.com "predicate_test": condPredicateTest }, 1417599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1427202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrCpsrImmIop) 1437202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrCpsrImmIop) 1447202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrCpsrImmIop) 1457202Sgblack@eecs.umich.edu 1467202Sgblack@eecs.umich.edu msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);" 1477202Sgblack@eecs.umich.edu msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp", 1487202Sgblack@eecs.umich.edu { "code": msrSpsrImmCode, 1497599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 1507599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 1517202Sgblack@eecs.umich.edu header_output += MsrImmDeclare.subst(msrSpsrImmIop) 1527202Sgblack@eecs.umich.edu decoder_output += MsrImmConstructor.subst(msrSpsrImmIop) 1537202Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(msrSpsrImmIop) 1547209Sgblack@eecs.umich.edu 1557209Sgblack@eecs.umich.edu revCode = ''' 1567209Sgblack@eecs.umich.edu uint32_t val = Op1; 1577209Sgblack@eecs.umich.edu Dest = swap_byte(val); 1587209Sgblack@eecs.umich.edu ''' 1597261Sgblack@eecs.umich.edu revIop = InstObjParams("rev", "Rev", "RegRegOp", 1607209Sgblack@eecs.umich.edu { "code": revCode, 1617209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1627261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revIop) 1637261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revIop) 1647209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revIop) 1657209Sgblack@eecs.umich.edu 1667209Sgblack@eecs.umich.edu rev16Code = ''' 1677209Sgblack@eecs.umich.edu uint32_t val = Op1; 1687209Sgblack@eecs.umich.edu Dest = (bits(val, 15, 8) << 0) | 1697209Sgblack@eecs.umich.edu (bits(val, 7, 0) << 8) | 1707209Sgblack@eecs.umich.edu (bits(val, 31, 24) << 16) | 1717209Sgblack@eecs.umich.edu (bits(val, 23, 16) << 24); 1727209Sgblack@eecs.umich.edu ''' 1737261Sgblack@eecs.umich.edu rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp", 1747209Sgblack@eecs.umich.edu { "code": rev16Code, 1757209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1767261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rev16Iop) 1777261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rev16Iop) 1787209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rev16Iop) 1797209Sgblack@eecs.umich.edu 1807209Sgblack@eecs.umich.edu revshCode = ''' 1817209Sgblack@eecs.umich.edu uint16_t val = Op1; 1827209Sgblack@eecs.umich.edu Dest = sext<16>(swap_byte(val)); 1837209Sgblack@eecs.umich.edu ''' 1847261Sgblack@eecs.umich.edu revshIop = InstObjParams("revsh", "Revsh", "RegRegOp", 1857209Sgblack@eecs.umich.edu { "code": revshCode, 1867209Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 1877261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(revshIop) 1887261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(revshIop) 1897209Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(revshIop) 1907226Sgblack@eecs.umich.edu 1917249Sgblack@eecs.umich.edu rbitCode = ''' 1927249Sgblack@eecs.umich.edu uint8_t *opBytes = (uint8_t *)&Op1; 1937249Sgblack@eecs.umich.edu uint32_t resTemp; 1947249Sgblack@eecs.umich.edu uint8_t *destBytes = (uint8_t *)&resTemp; 1957249Sgblack@eecs.umich.edu // This reverses the bytes and bits of the input, or so says the 1967249Sgblack@eecs.umich.edu // internet. 1977249Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1987249Sgblack@eecs.umich.edu uint32_t temp = opBytes[i]; 1997249Sgblack@eecs.umich.edu temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); 2007249Sgblack@eecs.umich.edu destBytes[3 - i] = (temp * 0x10101) >> 16; 2017249Sgblack@eecs.umich.edu } 2027249Sgblack@eecs.umich.edu Dest = resTemp; 2037249Sgblack@eecs.umich.edu ''' 2047261Sgblack@eecs.umich.edu rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", 2057249Sgblack@eecs.umich.edu { "code": rbitCode, 2067249Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2077261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(rbitIop) 2087261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(rbitIop) 2097249Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(rbitIop) 2107249Sgblack@eecs.umich.edu 2117251Sgblack@eecs.umich.edu clzCode = ''' 2127251Sgblack@eecs.umich.edu Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1)); 2137251Sgblack@eecs.umich.edu ''' 2147261Sgblack@eecs.umich.edu clzIop = InstObjParams("clz", "Clz", "RegRegOp", 2157251Sgblack@eecs.umich.edu { "code": clzCode, 2167251Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2177261Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(clzIop) 2187261Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(clzIop) 2197251Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(clzIop) 2207251Sgblack@eecs.umich.edu 2217226Sgblack@eecs.umich.edu ssatCode = ''' 2227226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2237226Sgblack@eecs.umich.edu int32_t res; 2247232Sgblack@eecs.umich.edu if (satInt(res, operand, imm)) 2258302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2267226Sgblack@eecs.umich.edu Dest = res; 2277226Sgblack@eecs.umich.edu ''' 2287232Sgblack@eecs.umich.edu ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", 2297226Sgblack@eecs.umich.edu { "code": ssatCode, 2308304SAli.Saidi@ARM.com "predicate_test": pickPredicate(ssatCode) }, []) 2317232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(ssatIop) 2327232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop) 2337226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssatIop) 2347226Sgblack@eecs.umich.edu 2357226Sgblack@eecs.umich.edu usatCode = ''' 2367226Sgblack@eecs.umich.edu int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); 2377226Sgblack@eecs.umich.edu int32_t res; 2387232Sgblack@eecs.umich.edu if (uSatInt(res, operand, imm)) 2398302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2407226Sgblack@eecs.umich.edu Dest = res; 2417226Sgblack@eecs.umich.edu ''' 2427232Sgblack@eecs.umich.edu usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", 2437226Sgblack@eecs.umich.edu { "code": usatCode, 2448304SAli.Saidi@ARM.com "predicate_test": pickPredicate(usatCode) }, []) 2457232Sgblack@eecs.umich.edu header_output += RegImmRegShiftOpDeclare.subst(usatIop) 2467232Sgblack@eecs.umich.edu decoder_output += RegImmRegShiftOpConstructor.subst(usatIop) 2477226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usatIop) 2487226Sgblack@eecs.umich.edu 2497226Sgblack@eecs.umich.edu ssat16Code = ''' 2507226Sgblack@eecs.umich.edu int32_t res; 2517226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2527226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2537226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2547232Sgblack@eecs.umich.edu if (satInt(res, argLow, imm)) 2558302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2567226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2577232Sgblack@eecs.umich.edu if (satInt(res, argHigh, imm)) 2588302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2597226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2607226Sgblack@eecs.umich.edu Dest = resTemp; 2617226Sgblack@eecs.umich.edu ''' 2627232Sgblack@eecs.umich.edu ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp", 2637226Sgblack@eecs.umich.edu { "code": ssat16Code, 2648304SAli.Saidi@ARM.com "predicate_test": pickPredicate(ssat16Code) }, []) 2657232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(ssat16Iop) 2667232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(ssat16Iop) 2677226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ssat16Iop) 2687226Sgblack@eecs.umich.edu 2697226Sgblack@eecs.umich.edu usat16Code = ''' 2707226Sgblack@eecs.umich.edu int32_t res; 2717226Sgblack@eecs.umich.edu uint32_t resTemp = 0; 2727226Sgblack@eecs.umich.edu int32_t argLow = sext<16>(bits(Op1, 15, 0)); 2737226Sgblack@eecs.umich.edu int32_t argHigh = sext<16>(bits(Op1, 31, 16)); 2747232Sgblack@eecs.umich.edu if (uSatInt(res, argLow, imm)) 2758302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2767226Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, res); 2777232Sgblack@eecs.umich.edu if (uSatInt(res, argHigh, imm)) 2788302SAli.Saidi@ARM.com CpsrQ = 1 << 27; 2797226Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, res); 2807226Sgblack@eecs.umich.edu Dest = resTemp; 2817226Sgblack@eecs.umich.edu ''' 2827232Sgblack@eecs.umich.edu usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp", 2837226Sgblack@eecs.umich.edu { "code": usat16Code, 2848304SAli.Saidi@ARM.com "predicate_test": pickPredicate(usat16Code) }, []) 2857232Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(usat16Iop) 2867232Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(usat16Iop) 2877226Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usat16Iop) 2887234Sgblack@eecs.umich.edu 2897234Sgblack@eecs.umich.edu sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp", 2907234Sgblack@eecs.umich.edu { "code": 2918588Sgblack@eecs.umich.edu "Dest = sext<8>((uint8_t)(Op1_ud >> imm));", 2927234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 2937234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtbIop) 2947234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtbIop) 2957234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtbIop) 2967234Sgblack@eecs.umich.edu 2977234Sgblack@eecs.umich.edu sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp", 2987234Sgblack@eecs.umich.edu { "code": 2997234Sgblack@eecs.umich.edu ''' 3008588Sgblack@eecs.umich.edu Dest = sext<8>((uint8_t)(Op2_ud >> imm)) + 3017234Sgblack@eecs.umich.edu Op1; 3027234Sgblack@eecs.umich.edu ''', 3037234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3047234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtabIop) 3057234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop) 3067234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtabIop) 3077234Sgblack@eecs.umich.edu 3087234Sgblack@eecs.umich.edu sxtb16Code = ''' 3097234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3107234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm))); 3117234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3127234Sgblack@eecs.umich.edu sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3137234Sgblack@eecs.umich.edu Dest = resTemp; 3147234Sgblack@eecs.umich.edu ''' 3157234Sgblack@eecs.umich.edu sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp", 3167234Sgblack@eecs.umich.edu { "code": sxtb16Code, 3177234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3187234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxtb16Iop) 3197234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop) 3207234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtb16Iop) 3217234Sgblack@eecs.umich.edu 3227234Sgblack@eecs.umich.edu sxtab16Code = ''' 3237234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3247234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) + 3257234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3267234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3277234Sgblack@eecs.umich.edu sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3287234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3297234Sgblack@eecs.umich.edu Dest = resTemp; 3307234Sgblack@eecs.umich.edu ''' 3317234Sgblack@eecs.umich.edu sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp", 3327234Sgblack@eecs.umich.edu { "code": sxtab16Code, 3337234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3347234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop) 3357234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop) 3367234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtab16Iop) 3377234Sgblack@eecs.umich.edu 3387234Sgblack@eecs.umich.edu sxthCode = ''' 3397234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 3407234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3417234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated); 3427234Sgblack@eecs.umich.edu ''' 3437234Sgblack@eecs.umich.edu sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp", 3447234Sgblack@eecs.umich.edu { "code": sxthCode, 3457234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3467234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(sxthIop) 3477234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(sxthIop) 3487234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxthIop) 3497234Sgblack@eecs.umich.edu 3507234Sgblack@eecs.umich.edu sxtahCode = ''' 3517234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 3527234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 3537234Sgblack@eecs.umich.edu Dest = sext<16>((uint16_t)rotated) + Op1; 3547234Sgblack@eecs.umich.edu ''' 3557234Sgblack@eecs.umich.edu sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp", 3567234Sgblack@eecs.umich.edu { "code": sxtahCode, 3577234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3587234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(sxtahIop) 3597234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop) 3607234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sxtahIop) 3617234Sgblack@eecs.umich.edu 3627234Sgblack@eecs.umich.edu uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp", 3638588Sgblack@eecs.umich.edu { "code": "Dest = (uint8_t)(Op1_ud >> imm);", 3647234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3657234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtbIop) 3667234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtbIop) 3677234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtbIop) 3687234Sgblack@eecs.umich.edu 3697234Sgblack@eecs.umich.edu uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp", 3707234Sgblack@eecs.umich.edu { "code": 3718588Sgblack@eecs.umich.edu "Dest = (uint8_t)(Op2_ud >> imm) + Op1;", 3727234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3737234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtabIop) 3747234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop) 3757234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtabIop) 3767234Sgblack@eecs.umich.edu 3777234Sgblack@eecs.umich.edu uxtb16Code = ''' 3787234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3797234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm))); 3807234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3817234Sgblack@eecs.umich.edu (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32))); 3827234Sgblack@eecs.umich.edu Dest = resTemp; 3837234Sgblack@eecs.umich.edu ''' 3847234Sgblack@eecs.umich.edu uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp", 3857234Sgblack@eecs.umich.edu { "code": uxtb16Code, 3867234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 3877234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxtb16Iop) 3887234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop) 3897234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtb16Iop) 3907234Sgblack@eecs.umich.edu 3917234Sgblack@eecs.umich.edu uxtab16Code = ''' 3927234Sgblack@eecs.umich.edu uint32_t resTemp = 0; 3937234Sgblack@eecs.umich.edu replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) + 3947234Sgblack@eecs.umich.edu bits(Op1, 15, 0)); 3957234Sgblack@eecs.umich.edu replaceBits(resTemp, 31, 16, 3967234Sgblack@eecs.umich.edu (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) + 3977234Sgblack@eecs.umich.edu bits(Op1, 31, 16)); 3987234Sgblack@eecs.umich.edu Dest = resTemp; 3997234Sgblack@eecs.umich.edu ''' 4007234Sgblack@eecs.umich.edu uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp", 4017234Sgblack@eecs.umich.edu { "code": uxtab16Code, 4027234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4037234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop) 4047234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop) 4057234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtab16Iop) 4067234Sgblack@eecs.umich.edu 4077234Sgblack@eecs.umich.edu uxthCode = ''' 4087234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op1; 4097234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4107234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated; 4117234Sgblack@eecs.umich.edu ''' 4127234Sgblack@eecs.umich.edu uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp", 4137234Sgblack@eecs.umich.edu { "code": uxthCode, 4147234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4157234Sgblack@eecs.umich.edu header_output += RegImmRegOpDeclare.subst(uxthIop) 4167234Sgblack@eecs.umich.edu decoder_output += RegImmRegOpConstructor.subst(uxthIop) 4177234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxthIop) 4187234Sgblack@eecs.umich.edu 4197234Sgblack@eecs.umich.edu uxtahCode = ''' 4207234Sgblack@eecs.umich.edu uint64_t rotated = (uint32_t)Op2; 4217234Sgblack@eecs.umich.edu rotated = (rotated | (rotated << 32)) >> imm; 4227234Sgblack@eecs.umich.edu Dest = (uint16_t)rotated + Op1; 4237234Sgblack@eecs.umich.edu ''' 4247234Sgblack@eecs.umich.edu uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp", 4257234Sgblack@eecs.umich.edu { "code": uxtahCode, 4267234Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4277234Sgblack@eecs.umich.edu header_output += RegRegRegImmOpDeclare.subst(uxtahIop) 4287234Sgblack@eecs.umich.edu decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop) 4297234Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(uxtahIop) 4307239Sgblack@eecs.umich.edu 4317239Sgblack@eecs.umich.edu selCode = ''' 4327239Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4337239Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4347239Sgblack@eecs.umich.edu int low = i * 8; 4357239Sgblack@eecs.umich.edu int high = low + 7; 4367239Sgblack@eecs.umich.edu replaceBits(resTemp, high, low, 4378303SAli.Saidi@ARM.com bits(CondCodesGE, i) ? 4387239Sgblack@eecs.umich.edu bits(Op1, high, low) : bits(Op2, high, low)); 4397239Sgblack@eecs.umich.edu } 4407239Sgblack@eecs.umich.edu Dest = resTemp; 4417239Sgblack@eecs.umich.edu ''' 4427239Sgblack@eecs.umich.edu selIop = InstObjParams("sel", "Sel", "RegRegRegOp", 4437239Sgblack@eecs.umich.edu { "code": selCode, 4448303SAli.Saidi@ARM.com "predicate_test": predicateTest }, []) 4457239Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(selIop) 4467239Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(selIop) 4477239Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(selIop) 4487242Sgblack@eecs.umich.edu 4497242Sgblack@eecs.umich.edu usad8Code = ''' 4507242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4517242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4527242Sgblack@eecs.umich.edu int low = i * 8; 4537242Sgblack@eecs.umich.edu int high = low + 7; 4547242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4557242Sgblack@eecs.umich.edu bits(Op2, high, low); 4567242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4577242Sgblack@eecs.umich.edu } 4587242Sgblack@eecs.umich.edu Dest = resTemp; 4597242Sgblack@eecs.umich.edu ''' 4607242Sgblack@eecs.umich.edu usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp", 4617242Sgblack@eecs.umich.edu { "code": usad8Code, 4627242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4637242Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(usad8Iop) 4647242Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(usad8Iop) 4657242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usad8Iop) 4667242Sgblack@eecs.umich.edu 4677242Sgblack@eecs.umich.edu usada8Code = ''' 4687242Sgblack@eecs.umich.edu uint32_t resTemp = 0; 4697242Sgblack@eecs.umich.edu for (unsigned i = 0; i < 4; i++) { 4707242Sgblack@eecs.umich.edu int low = i * 8; 4717242Sgblack@eecs.umich.edu int high = low + 7; 4727242Sgblack@eecs.umich.edu int32_t diff = bits(Op1, high, low) - 4737242Sgblack@eecs.umich.edu bits(Op2, high, low); 4747242Sgblack@eecs.umich.edu resTemp += ((diff < 0) ? -diff : diff); 4757242Sgblack@eecs.umich.edu } 4767242Sgblack@eecs.umich.edu Dest = Op3 + resTemp; 4777242Sgblack@eecs.umich.edu ''' 4787242Sgblack@eecs.umich.edu usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp", 4797242Sgblack@eecs.umich.edu { "code": usada8Code, 4807242Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 4817242Sgblack@eecs.umich.edu header_output += RegRegRegRegOpDeclare.subst(usada8Iop) 4827242Sgblack@eecs.umich.edu decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) 4837242Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(usada8Iop) 4847247Sgblack@eecs.umich.edu 4857797Sgblack@eecs.umich.edu bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' 4867848SAli.Saidi@ARM.com bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) 4877410Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(bkptIop) 4887410Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(bkptIop) 4897410Sgblack@eecs.umich.edu exec_output += BasicExecute.subst(bkptIop) 4907410Sgblack@eecs.umich.edu 4917408Sgblack@eecs.umich.edu nopIop = InstObjParams("nop", "NopInst", "PredOp", \ 4928065SAli.Saidi@ARM.com { "code" : "", "predicate_test" : predicateTest }, 4938065SAli.Saidi@ARM.com ['IsNop']) 4947247Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(nopIop) 4957247Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(nopIop) 4967408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(nopIop) 4977408Sgblack@eecs.umich.edu 4987418Sgblack@eecs.umich.edu yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \ 4997418Sgblack@eecs.umich.edu { "code" : "", "predicate_test" : predicateTest }) 5007418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(yieldIop) 5017418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(yieldIop) 5027418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(yieldIop) 5037418Sgblack@eecs.umich.edu 5047418Sgblack@eecs.umich.edu wfeCode = ''' 5057418Sgblack@eecs.umich.edu#if FULL_SYSTEM 5068518Sgeoffrey.blake@arm.com // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending 5078285SPrakash.Ramrakhyani@arm.com if (SevMailbox == 1) { 5087418Sgblack@eecs.umich.edu SevMailbox = 0; 5098142SAli.Saidi@ARM.com PseudoInst::quiesceSkip(xc->tcBase()); 5108518Sgeoffrey.blake@arm.com } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) { 5118518Sgeoffrey.blake@arm.com PseudoInst::quiesceSkip(xc->tcBase()); 5128285SPrakash.Ramrakhyani@arm.com } else { 5137418Sgblack@eecs.umich.edu PseudoInst::quiesce(xc->tcBase()); 5148142SAli.Saidi@ARM.com } 5157418Sgblack@eecs.umich.edu#endif 5167418Sgblack@eecs.umich.edu ''' 5178518Sgeoffrey.blake@arm.com wfePredFixUpCode = ''' 5188518Sgeoffrey.blake@arm.com#if FULL_SYSTEM 5198518Sgeoffrey.blake@arm.com // WFE is predicated false, reset SevMailbox to reduce spurious sleeps 5208518Sgeoffrey.blake@arm.com // and SEV interrupts 5218518Sgeoffrey.blake@arm.com SevMailbox = 1; 5228518Sgeoffrey.blake@arm.com#endif 5238518Sgeoffrey.blake@arm.com ''' 5247418Sgblack@eecs.umich.edu wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ 5258518Sgeoffrey.blake@arm.com { "code" : wfeCode, 5268518Sgeoffrey.blake@arm.com "pred_fixup" : wfePredFixUpCode, 5278518Sgeoffrey.blake@arm.com "predicate_test" : predicateTest }, 5287648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 5297418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfeIop) 5307418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfeIop) 5318518Sgeoffrey.blake@arm.com exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) 5327418Sgblack@eecs.umich.edu 5337418Sgblack@eecs.umich.edu wfiCode = ''' 5347418Sgblack@eecs.umich.edu#if FULL_SYSTEM 5358285SPrakash.Ramrakhyani@arm.com // WFI doesn't sleep if interrupts are pending (masked or not) 5368285SPrakash.Ramrakhyani@arm.com if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { 5378285SPrakash.Ramrakhyani@arm.com PseudoInst::quiesceSkip(xc->tcBase()); 5388285SPrakash.Ramrakhyani@arm.com } else { 5398285SPrakash.Ramrakhyani@arm.com PseudoInst::quiesce(xc->tcBase()); 5408285SPrakash.Ramrakhyani@arm.com } 5417418Sgblack@eecs.umich.edu#endif 5427418Sgblack@eecs.umich.edu ''' 5437418Sgblack@eecs.umich.edu wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ 5447418Sgblack@eecs.umich.edu { "code" : wfiCode, "predicate_test" : predicateTest }, 5458142SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"]) 5467418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(wfiIop) 5477418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(wfiIop) 5488142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(wfiIop) 5497418Sgblack@eecs.umich.edu 5507418Sgblack@eecs.umich.edu sevCode = ''' 5518518Sgeoffrey.blake@arm.com#if FULL_SYSTEM 5528142SAli.Saidi@ARM.com SevMailbox = 1; 5537418Sgblack@eecs.umich.edu System *sys = xc->tcBase()->getSystemPtr(); 5547418Sgblack@eecs.umich.edu for (int x = 0; x < sys->numContexts(); x++) { 5557418Sgblack@eecs.umich.edu ThreadContext *oc = sys->getThreadContext(x); 5568285SPrakash.Ramrakhyani@arm.com if (oc == xc->tcBase()) 5578285SPrakash.Ramrakhyani@arm.com continue; 5588518Sgeoffrey.blake@arm.com // Wake CPU with interrupt if they were sleeping 5598285SPrakash.Ramrakhyani@arm.com if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) { 5608518Sgeoffrey.blake@arm.com // Post Interrupt and wake cpu if needed 5618518Sgeoffrey.blake@arm.com oc->getCpuPtr()->postInterrupt(INT_SEV, 0); 5628142SAli.Saidi@ARM.com } 5637418Sgblack@eecs.umich.edu } 5648518Sgeoffrey.blake@arm.com#endif 5657418Sgblack@eecs.umich.edu ''' 5667418Sgblack@eecs.umich.edu sevIop = InstObjParams("sev", "SevInst", "PredOp", \ 5677418Sgblack@eecs.umich.edu { "code" : sevCode, "predicate_test" : predicateTest }, 5688142SAli.Saidi@ARM.com ["IsNonSpeculative", "IsSquashAfter"]) 5697418Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(sevIop) 5707418Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(sevIop) 5717418Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sevIop) 5727418Sgblack@eecs.umich.edu 5737408Sgblack@eecs.umich.edu itIop = InstObjParams("it", "ItInst", "PredOp", \ 5748205SAli.Saidi@ARM.com { "code" : ";", 5757648SAli.Saidi@ARM.com "predicate_test" : predicateTest }, 5767648SAli.Saidi@ARM.com ["IsNonSpeculative", "IsSerializeAfter"]) 5777408Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(itIop) 5787408Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(itIop) 5797408Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(itIop) 5807409Sgblack@eecs.umich.edu unknownCode = ''' 5817409Sgblack@eecs.umich.edu#if FULL_SYSTEM 5827409Sgblack@eecs.umich.edu return new UndefinedInstruction; 5837409Sgblack@eecs.umich.edu#else 5847409Sgblack@eecs.umich.edu return new UndefinedInstruction(machInst, true); 5857409Sgblack@eecs.umich.edu#endif 5867409Sgblack@eecs.umich.edu ''' 5877409Sgblack@eecs.umich.edu unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ 5887409Sgblack@eecs.umich.edu { "code": unknownCode, 5897409Sgblack@eecs.umich.edu "predicate_test": predicateTest }) 5907409Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(unknownIop) 5917409Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(unknownIop) 5927409Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(unknownIop) 5937254Sgblack@eecs.umich.edu 5947254Sgblack@eecs.umich.edu ubfxCode = ''' 5957254Sgblack@eecs.umich.edu Dest = bits(Op1, imm2, imm1); 5967254Sgblack@eecs.umich.edu ''' 5977254Sgblack@eecs.umich.edu ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp", 5987254Sgblack@eecs.umich.edu { "code": ubfxCode, 5997254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6007254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(ubfxIop) 6017254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop) 6027254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(ubfxIop) 6037254Sgblack@eecs.umich.edu 6047254Sgblack@eecs.umich.edu sbfxCode = ''' 6057254Sgblack@eecs.umich.edu int32_t resTemp = bits(Op1, imm2, imm1); 6067254Sgblack@eecs.umich.edu Dest = resTemp | -(resTemp & (1 << (imm2 - imm1))); 6077254Sgblack@eecs.umich.edu ''' 6087254Sgblack@eecs.umich.edu sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp", 6097254Sgblack@eecs.umich.edu { "code": sbfxCode, 6107254Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6117254Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(sbfxIop) 6127254Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop) 6137254Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(sbfxIop) 6147257Sgblack@eecs.umich.edu 6157257Sgblack@eecs.umich.edu bfcCode = ''' 6167257Sgblack@eecs.umich.edu Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1); 6177257Sgblack@eecs.umich.edu ''' 6187257Sgblack@eecs.umich.edu bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp", 6197257Sgblack@eecs.umich.edu { "code": bfcCode, 6207257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6217257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfcIop) 6227257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfcIop) 6237257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfcIop) 6247257Sgblack@eecs.umich.edu 6257257Sgblack@eecs.umich.edu bfiCode = ''' 6267257Sgblack@eecs.umich.edu uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1); 6277257Sgblack@eecs.umich.edu Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask); 6287257Sgblack@eecs.umich.edu ''' 6297257Sgblack@eecs.umich.edu bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp", 6307257Sgblack@eecs.umich.edu { "code": bfiCode, 6317257Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6327257Sgblack@eecs.umich.edu header_output += RegRegImmImmOpDeclare.subst(bfiIop) 6337257Sgblack@eecs.umich.edu decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) 6347257Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(bfiIop) 6357262Sgblack@eecs.umich.edu 6367347SAli.Saidi@ARM.com mrc15code = ''' 6377347SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 6387347SAli.Saidi@ARM.com if (cpsr.mode == MODE_USER) 6397347SAli.Saidi@ARM.com#if FULL_SYSTEM 6407347SAli.Saidi@ARM.com return new UndefinedInstruction; 6417347SAli.Saidi@ARM.com#else 6427347SAli.Saidi@ARM.com return new UndefinedInstruction(false, mnemonic); 6437347SAli.Saidi@ARM.com#endif 6447347SAli.Saidi@ARM.com Dest = MiscOp1; 6457347SAli.Saidi@ARM.com ''' 6467347SAli.Saidi@ARM.com 6477262Sgblack@eecs.umich.edu mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp", 6487347SAli.Saidi@ARM.com { "code": mrc15code, 6497262Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6507262Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15Iop) 6517262Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15Iop) 6527262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15Iop) 6537262Sgblack@eecs.umich.edu 6547347SAli.Saidi@ARM.com 6557347SAli.Saidi@ARM.com mcr15code = ''' 6567347SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 6577347SAli.Saidi@ARM.com if (cpsr.mode == MODE_USER) 6587347SAli.Saidi@ARM.com#if FULL_SYSTEM 6597347SAli.Saidi@ARM.com return new UndefinedInstruction; 6607347SAli.Saidi@ARM.com#else 6617347SAli.Saidi@ARM.com return new UndefinedInstruction(false, mnemonic); 6627347SAli.Saidi@ARM.com#endif 6637347SAli.Saidi@ARM.com MiscDest = Op1; 6647347SAli.Saidi@ARM.com ''' 6657262Sgblack@eecs.umich.edu mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", 6667347SAli.Saidi@ARM.com { "code": mcr15code, 6677599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 6687599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 6697262Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15Iop) 6707262Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15Iop) 6717262Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15Iop) 6727283Sgblack@eecs.umich.edu 6737420Sgblack@eecs.umich.edu mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", 6747420Sgblack@eecs.umich.edu { "code": "Dest = MiscOp1;", 6757420Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6767420Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mrc15UserIop) 6777420Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mrc15UserIop) 6787420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mrc15UserIop) 6797420Sgblack@eecs.umich.edu 6807420Sgblack@eecs.umich.edu mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", 6817420Sgblack@eecs.umich.edu { "code": "MiscDest = Op1", 6827599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 6837599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 6847420Sgblack@eecs.umich.edu header_output += RegRegOpDeclare.subst(mcr15UserIop) 6857420Sgblack@eecs.umich.edu decoder_output += RegRegOpConstructor.subst(mcr15UserIop) 6867420Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(mcr15UserIop) 6877420Sgblack@eecs.umich.edu 6887283Sgblack@eecs.umich.edu enterxCode = ''' 6897797Sgblack@eecs.umich.edu NextThumb = true; 6907797Sgblack@eecs.umich.edu NextJazelle = true; 6917283Sgblack@eecs.umich.edu ''' 6927283Sgblack@eecs.umich.edu enterxIop = InstObjParams("enterx", "Enterx", "PredOp", 6937283Sgblack@eecs.umich.edu { "code": enterxCode, 6947283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 6957283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(enterxIop) 6967283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(enterxIop) 6977283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(enterxIop) 6987283Sgblack@eecs.umich.edu 6997283Sgblack@eecs.umich.edu leavexCode = ''' 7007797Sgblack@eecs.umich.edu NextThumb = true; 7017797Sgblack@eecs.umich.edu NextJazelle = false; 7027283Sgblack@eecs.umich.edu ''' 7037283Sgblack@eecs.umich.edu leavexIop = InstObjParams("leavex", "Leavex", "PredOp", 7047283Sgblack@eecs.umich.edu { "code": leavexCode, 7057283Sgblack@eecs.umich.edu "predicate_test": predicateTest }, []) 7067283Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(leavexIop) 7077283Sgblack@eecs.umich.edu decoder_output += BasicConstructor.subst(leavexIop) 7087283Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(leavexIop) 7097307Sgblack@eecs.umich.edu 7107307Sgblack@eecs.umich.edu setendCode = ''' 7117307Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 7127307Sgblack@eecs.umich.edu cpsr.e = imm; 7137307Sgblack@eecs.umich.edu Cpsr = cpsr; 7147307Sgblack@eecs.umich.edu ''' 7157307Sgblack@eecs.umich.edu setendIop = InstObjParams("setend", "Setend", "ImmOp", 7167307Sgblack@eecs.umich.edu { "code": setendCode, 7177648SAli.Saidi@ARM.com "predicate_test": predicateTest }, 7187648SAli.Saidi@ARM.com ["IsSerializeAfter","IsNonSpeculative"]) 7197307Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(setendIop) 7207307Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(setendIop) 7217307Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(setendIop) 7227315Sgblack@eecs.umich.edu 7237603SGene.Wu@arm.com clrexCode = ''' 7248209SAli.Saidi@ARM.com LLSCLock = 0; 7257603SGene.Wu@arm.com ''' 7267603SGene.Wu@arm.com clrexIop = InstObjParams("clrex", "Clrex","PredOp", 7277603SGene.Wu@arm.com { "code": clrexCode, 7287603SGene.Wu@arm.com "predicate_test": predicateTest },[]) 7298209SAli.Saidi@ARM.com header_output += BasicDeclare.subst(clrexIop) 7307603SGene.Wu@arm.com decoder_output += BasicConstructor.subst(clrexIop) 7317603SGene.Wu@arm.com exec_output += PredOpExecute.subst(clrexIop) 7327603SGene.Wu@arm.com 7337605SGene.Wu@arm.com isbCode = ''' 7348068SAli.Saidi@ARM.com fault = new FlushPipe; 7357605SGene.Wu@arm.com ''' 7367605SGene.Wu@arm.com isbIop = InstObjParams("isb", "Isb", "PredOp", 7377605SGene.Wu@arm.com {"code": isbCode, 7388068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 7398068SAli.Saidi@ARM.com ['IsSerializeAfter']) 7407605SGene.Wu@arm.com header_output += BasicDeclare.subst(isbIop) 7417605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(isbIop) 7427605SGene.Wu@arm.com exec_output += PredOpExecute.subst(isbIop) 7437605SGene.Wu@arm.com 7447605SGene.Wu@arm.com dsbCode = ''' 7458068SAli.Saidi@ARM.com fault = new FlushPipe; 7467605SGene.Wu@arm.com ''' 7477605SGene.Wu@arm.com dsbIop = InstObjParams("dsb", "Dsb", "PredOp", 7487605SGene.Wu@arm.com {"code": dsbCode, 7498068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 7508068SAli.Saidi@ARM.com ['IsMemBarrier', 'IsSerializeAfter']) 7517605SGene.Wu@arm.com header_output += BasicDeclare.subst(dsbIop) 7527605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dsbIop) 7537605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dsbIop) 7547605SGene.Wu@arm.com 7557605SGene.Wu@arm.com dmbCode = ''' 7567605SGene.Wu@arm.com ''' 7577605SGene.Wu@arm.com dmbIop = InstObjParams("dmb", "Dmb", "PredOp", 7587605SGene.Wu@arm.com {"code": dmbCode, 7598068SAli.Saidi@ARM.com "predicate_test": predicateTest}, 7608068SAli.Saidi@ARM.com ['IsMemBarrier']) 7617605SGene.Wu@arm.com header_output += BasicDeclare.subst(dmbIop) 7627605SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dmbIop) 7637605SGene.Wu@arm.com exec_output += PredOpExecute.subst(dmbIop) 7647605SGene.Wu@arm.com 7657613SGene.Wu@arm.com dbgCode = ''' 7667613SGene.Wu@arm.com ''' 7677613SGene.Wu@arm.com dbgIop = InstObjParams("dbg", "Dbg", "PredOp", 7687613SGene.Wu@arm.com {"code": dbgCode, 7697613SGene.Wu@arm.com "predicate_test": predicateTest}) 7707613SGene.Wu@arm.com header_output += BasicDeclare.subst(dbgIop) 7717613SGene.Wu@arm.com decoder_output += BasicConstructor.subst(dbgIop) 7727613SGene.Wu@arm.com exec_output += PredOpExecute.subst(dbgIop) 7737613SGene.Wu@arm.com 7747315Sgblack@eecs.umich.edu cpsCode = ''' 7757315Sgblack@eecs.umich.edu uint32_t mode = bits(imm, 4, 0); 7767315Sgblack@eecs.umich.edu uint32_t f = bits(imm, 5); 7777315Sgblack@eecs.umich.edu uint32_t i = bits(imm, 6); 7787315Sgblack@eecs.umich.edu uint32_t a = bits(imm, 7); 7797315Sgblack@eecs.umich.edu bool setMode = bits(imm, 8); 7807315Sgblack@eecs.umich.edu bool enable = bits(imm, 9); 7817315Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 7827400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 7837315Sgblack@eecs.umich.edu if (cpsr.mode != MODE_USER) { 7847315Sgblack@eecs.umich.edu if (enable) { 7857315Sgblack@eecs.umich.edu if (f) cpsr.f = 0; 7867315Sgblack@eecs.umich.edu if (i) cpsr.i = 0; 7877315Sgblack@eecs.umich.edu if (a) cpsr.a = 0; 7887315Sgblack@eecs.umich.edu } else { 7897400SAli.Saidi@ARM.com if (f && !sctlr.nmfi) cpsr.f = 1; 7907315Sgblack@eecs.umich.edu if (i) cpsr.i = 1; 7917315Sgblack@eecs.umich.edu if (a) cpsr.a = 1; 7927315Sgblack@eecs.umich.edu } 7937315Sgblack@eecs.umich.edu if (setMode) { 7947315Sgblack@eecs.umich.edu cpsr.mode = mode; 7957315Sgblack@eecs.umich.edu } 7967315Sgblack@eecs.umich.edu } 7977315Sgblack@eecs.umich.edu Cpsr = cpsr; 7987315Sgblack@eecs.umich.edu ''' 7997315Sgblack@eecs.umich.edu cpsIop = InstObjParams("cps", "Cps", "ImmOp", 8007315Sgblack@eecs.umich.edu { "code": cpsCode, 8017599Sminkyu.jeong@arm.com "predicate_test": predicateTest }, 8027599Sminkyu.jeong@arm.com ["IsSerializeAfter","IsNonSpeculative"]) 8037315Sgblack@eecs.umich.edu header_output += ImmOpDeclare.subst(cpsIop) 8047315Sgblack@eecs.umich.edu decoder_output += ImmOpConstructor.subst(cpsIop) 8057315Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(cpsIop) 8067202Sgblack@eecs.umich.edu}}; 807