xref: /gem5/src/arch/arm/isa/insts/misc.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

let {{

    svcCode = '''
#if FULL_SYSTEM
    fault = new SupervisorCall;
#else
    fault = new SupervisorCall(machInst);
#endif
    '''

    svcIop = InstObjParams("svc", "Svc", "PredOp",
                           { "code": svcCode,
                             "predicate_test": predicateTest }, ["IsSyscall"])
    header_output = BasicDeclare.subst(svcIop)
    decoder_output = BasicConstructor.subst(svcIop)
    exec_output = PredOpExecute.subst(svcIop)

}};

let {{

    header_output = decoder_output = exec_output = ""

    mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
    mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
                               { "code": mrsCpsrCode,
                                 "predicate_test": condPredicateTest },
                               ["IsSerializeAfter"])
    header_output += MrsDeclare.subst(mrsCpsrIop)
    decoder_output += MrsConstructor.subst(mrsCpsrIop)
    exec_output += PredOpExecute.subst(mrsCpsrIop)

    mrsSpsrCode = "Dest = Spsr"
    mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
                               { "code": mrsSpsrCode,
                                 "predicate_test": predicateTest },
                               ["IsSerializeAfter"])
    header_output += MrsDeclare.subst(mrsSpsrIop)
    decoder_output += MrsConstructor.subst(mrsSpsrIop)
    exec_output += PredOpExecute.subst(mrsSpsrIop)

    msrCpsrRegCode = '''
        SCTLR sctlr = Sctlr;
        uint32_t newCpsr =
            cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
        Cpsr = ~CondCodesMask & newCpsr;
        ArmISA::PCState pc = PCS;
        pc.nextThumb(((CPSR)newCpsr).t);
        pc.nextJazelle(((CPSR)newCpsr).j);
        PCS = pc;
        CondCodes = CondCodesMask & newCpsr;
    '''
    msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
                                  { "code": msrCpsrRegCode,
                                    "predicate_test": condPredicateTest },
                                  ["IsSerializeAfter","IsNonSpeculative"])
    header_output += MsrRegDeclare.subst(msrCpsrRegIop)
    decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
    exec_output += PredOpExecute.subst(msrCpsrRegIop)

    msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
    msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
                                  { "code": msrSpsrRegCode,
                                    "predicate_test": predicateTest },
                                  ["IsSerializeAfter","IsNonSpeculative"])
    header_output += MsrRegDeclare.subst(msrSpsrRegIop)
    decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
    exec_output += PredOpExecute.subst(msrSpsrRegIop)

    msrCpsrImmCode = '''
        SCTLR sctlr = Sctlr;
        uint32_t newCpsr =
            cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
        Cpsr = ~CondCodesMask & newCpsr;
        ArmISA::PCState pc = PCS;
        pc.nextThumb(((CPSR)newCpsr).t);
        pc.nextJazelle(((CPSR)newCpsr).j);
        PCS = pc;
        CondCodes = CondCodesMask & newCpsr;
    '''
    msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
                                  { "code": msrCpsrImmCode,
                                    "predicate_test": condPredicateTest },
                                  ["IsSerializeAfter","IsNonSpeculative"])
    header_output += MsrImmDeclare.subst(msrCpsrImmIop)
    decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
    exec_output += PredOpExecute.subst(msrCpsrImmIop)

    msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
    msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
                                  { "code": msrSpsrImmCode,
                                    "predicate_test": predicateTest },
                                  ["IsSerializeAfter","IsNonSpeculative"])
    header_output += MsrImmDeclare.subst(msrSpsrImmIop)
    decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
    exec_output += PredOpExecute.subst(msrSpsrImmIop)

    revCode = '''
    uint32_t val = Op1;
    Dest = swap_byte(val);
    '''
    revIop = InstObjParams("rev", "Rev", "RegRegOp",
                           { "code": revCode,
                             "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(revIop)
    decoder_output += RegRegOpConstructor.subst(revIop)
    exec_output += PredOpExecute.subst(revIop)

    rev16Code = '''
    uint32_t val = Op1;
    Dest = (bits(val, 15, 8) << 0) |
           (bits(val, 7, 0) << 8) |
           (bits(val, 31, 24) << 16) |
           (bits(val, 23, 16) << 24);
    '''
    rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
                             { "code": rev16Code,
                               "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(rev16Iop)
    decoder_output += RegRegOpConstructor.subst(rev16Iop)
    exec_output += PredOpExecute.subst(rev16Iop)

    revshCode = '''
    uint16_t val = Op1;
    Dest = sext<16>(swap_byte(val));
    '''
    revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
                             { "code": revshCode,
                               "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(revshIop)
    decoder_output += RegRegOpConstructor.subst(revshIop)
    exec_output += PredOpExecute.subst(revshIop)

    rbitCode = '''
    uint8_t *opBytes = (uint8_t *)&Op1;
    uint32_t resTemp;
    uint8_t *destBytes = (uint8_t *)&resTemp;
    // This reverses the bytes and bits of the input, or so says the
    // internet.
    for (int i = 0; i < 4; i++) {
        uint32_t temp = opBytes[i];
        temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
        destBytes[3 - i] = (temp * 0x10101) >> 16;
    }
    Dest = resTemp;
    '''
    rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
                            { "code": rbitCode,
                              "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(rbitIop)
    decoder_output += RegRegOpConstructor.subst(rbitIop)
    exec_output += PredOpExecute.subst(rbitIop)

    clzCode = '''
        Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
    '''
    clzIop = InstObjParams("clz", "Clz", "RegRegOp",
                           { "code": clzCode,
                             "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(clzIop)
    decoder_output += RegRegOpConstructor.subst(clzIop)
    exec_output += PredOpExecute.subst(clzIop)

    ssatCode = '''
        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
        int32_t res;
        if (satInt(res, operand, imm))
            CondCodes = CondCodes | (1 << 27);
        else
            CondCodes = CondCodes;
        Dest = res;
    '''
    ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
                            { "code": ssatCode,
                              "predicate_test": condPredicateTest }, [])
    header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
    decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
    exec_output += PredOpExecute.subst(ssatIop)

    usatCode = '''
        int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
        int32_t res;
        if (uSatInt(res, operand, imm))
            CondCodes = CondCodes | (1 << 27);
        else
            CondCodes = CondCodes;
        Dest = res;
    '''
    usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
                            { "code": usatCode,
                              "predicate_test": condPredicateTest }, [])
    header_output += RegImmRegShiftOpDeclare.subst(usatIop)
    decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
    exec_output += PredOpExecute.subst(usatIop)

    ssat16Code = '''
        int32_t res;
        uint32_t resTemp = 0;
        CondCodes = CondCodes;
        int32_t argLow = sext<16>(bits(Op1, 15, 0));
        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
        if (satInt(res, argLow, imm))
            CondCodes = CondCodes | (1 << 27);
        replaceBits(resTemp, 15, 0, res);
        if (satInt(res, argHigh, imm))
            CondCodes = CondCodes | (1 << 27);
        replaceBits(resTemp, 31, 16, res);
        Dest = resTemp;
    '''
    ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
                              { "code": ssat16Code,
                                "predicate_test": condPredicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(ssat16Iop)
    decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
    exec_output += PredOpExecute.subst(ssat16Iop)

    usat16Code = '''
        int32_t res;
        uint32_t resTemp = 0;
        CondCodes = CondCodes;
        int32_t argLow = sext<16>(bits(Op1, 15, 0));
        int32_t argHigh = sext<16>(bits(Op1, 31, 16));
        if (uSatInt(res, argLow, imm))
            CondCodes = CondCodes | (1 << 27);
        replaceBits(resTemp, 15, 0, res);
        if (uSatInt(res, argHigh, imm))
            CondCodes = CondCodes | (1 << 27);
        replaceBits(resTemp, 31, 16, res);
        Dest = resTemp;
    '''
    usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
                              { "code": usat16Code,
                                "predicate_test": condPredicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(usat16Iop)
    decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
    exec_output += PredOpExecute.subst(usat16Iop)

    sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
                            { "code":
                              "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
                              "predicate_test": predicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(sxtbIop)
    decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
    exec_output += PredOpExecute.subst(sxtbIop)

    sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
                             { "code":
                               '''
                                   Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
                                          Op1;
                               ''',
                               "predicate_test": predicateTest }, [])
    header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
    decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
    exec_output += PredOpExecute.subst(sxtabIop)

    sxtb16Code = '''
    uint32_t resTemp = 0;
    replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
    replaceBits(resTemp, 31, 16,
                sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
    Dest = resTemp;
    '''
    sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
                              { "code": sxtb16Code,
                                "predicate_test": predicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
    decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
    exec_output += PredOpExecute.subst(sxtb16Iop)

    sxtab16Code = '''
    uint32_t resTemp = 0;
    replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
                                        bits(Op1, 15, 0));
    replaceBits(resTemp, 31, 16,
                sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
                bits(Op1, 31, 16));
    Dest = resTemp;
    '''
    sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
                               { "code": sxtab16Code,
                                 "predicate_test": predicateTest }, [])
    header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
    decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
    exec_output += PredOpExecute.subst(sxtab16Iop)

    sxthCode = '''
    uint64_t rotated = (uint32_t)Op1;
    rotated = (rotated | (rotated << 32)) >> imm;
    Dest = sext<16>((uint16_t)rotated);
    '''
    sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
                              { "code": sxthCode,
                                "predicate_test": predicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(sxthIop)
    decoder_output += RegImmRegOpConstructor.subst(sxthIop)
    exec_output += PredOpExecute.subst(sxthIop)

    sxtahCode = '''
    uint64_t rotated = (uint32_t)Op2;
    rotated = (rotated | (rotated << 32)) >> imm;
    Dest = sext<16>((uint16_t)rotated) + Op1;
    '''
    sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
                             { "code": sxtahCode,
                               "predicate_test": predicateTest }, [])
    header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
    decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
    exec_output += PredOpExecute.subst(sxtahIop)

    uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
                            { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
                              "predicate_test": predicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(uxtbIop)
    decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
    exec_output += PredOpExecute.subst(uxtbIop)

    uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
                             { "code":
                               "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
                               "predicate_test": predicateTest }, [])
    header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
    decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
    exec_output += PredOpExecute.subst(uxtabIop)

    uxtb16Code = '''
    uint32_t resTemp = 0;
    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
    replaceBits(resTemp, 31, 16,
                (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
    Dest = resTemp;
    '''
    uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
                              { "code": uxtb16Code,
                                "predicate_test": predicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
    decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
    exec_output += PredOpExecute.subst(uxtb16Iop)

    uxtab16Code = '''
    uint32_t resTemp = 0;
    replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
                                        bits(Op1, 15, 0));
    replaceBits(resTemp, 31, 16,
                (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
                bits(Op1, 31, 16));
    Dest = resTemp;
    '''
    uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
                               { "code": uxtab16Code,
                                 "predicate_test": predicateTest }, [])
    header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
    decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
    exec_output += PredOpExecute.subst(uxtab16Iop)

    uxthCode = '''
    uint64_t rotated = (uint32_t)Op1;
    rotated = (rotated | (rotated << 32)) >> imm;
    Dest = (uint16_t)rotated;
    '''
    uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
                              { "code": uxthCode,
                                "predicate_test": predicateTest }, [])
    header_output += RegImmRegOpDeclare.subst(uxthIop)
    decoder_output += RegImmRegOpConstructor.subst(uxthIop)
    exec_output += PredOpExecute.subst(uxthIop)

    uxtahCode = '''
    uint64_t rotated = (uint32_t)Op2;
    rotated = (rotated | (rotated << 32)) >> imm;
    Dest = (uint16_t)rotated + Op1;
    '''
    uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
                             { "code": uxtahCode,
                               "predicate_test": predicateTest }, [])
    header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
    decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
    exec_output += PredOpExecute.subst(uxtahIop)

    selCode = '''
        uint32_t resTemp = 0;
        for (unsigned i = 0; i < 4; i++) {
            int low = i * 8;
            int high = low + 7;
            replaceBits(resTemp, high, low,
                        bits(CondCodes, 16 + i) ?
                            bits(Op1, high, low) : bits(Op2, high, low));
        }
        Dest = resTemp;
    '''
    selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
                           { "code": selCode,
                             "predicate_test": condPredicateTest }, [])
    header_output += RegRegRegOpDeclare.subst(selIop)
    decoder_output += RegRegRegOpConstructor.subst(selIop)
    exec_output += PredOpExecute.subst(selIop)

    usad8Code = '''
        uint32_t resTemp = 0;
        for (unsigned i = 0; i < 4; i++) {
            int low = i * 8;
            int high = low + 7;
            int32_t diff = bits(Op1, high, low) -
                           bits(Op2, high, low);
            resTemp += ((diff < 0) ? -diff : diff);
        }
        Dest = resTemp;
    '''
    usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
                             { "code": usad8Code,
                               "predicate_test": predicateTest }, [])
    header_output += RegRegRegOpDeclare.subst(usad8Iop)
    decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
    exec_output += PredOpExecute.subst(usad8Iop)

    usada8Code = '''
        uint32_t resTemp = 0;
        for (unsigned i = 0; i < 4; i++) {
            int low = i * 8;
            int high = low + 7;
            int32_t diff = bits(Op1, high, low) -
                           bits(Op2, high, low);
            resTemp += ((diff < 0) ? -diff : diff);
        }
        Dest = Op3 + resTemp;
    '''
    usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
                              { "code": usada8Code,
                                "predicate_test": predicateTest }, [])
    header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
    decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
    exec_output += PredOpExecute.subst(usada8Iop)

    bkptCode = '''
    ArmISA::PCState pc = PCS;
    return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
    '''
    bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
            bkptCode)
    header_output += BasicDeclare.subst(bkptIop)
    decoder_output += BasicConstructor.subst(bkptIop)
    exec_output += BasicExecute.subst(bkptIop)

    nopIop = InstObjParams("nop", "NopInst", "PredOp", \
            { "code" : "", "predicate_test" : predicateTest })
    header_output += BasicDeclare.subst(nopIop)
    decoder_output += BasicConstructor.subst(nopIop)
    exec_output += PredOpExecute.subst(nopIop)

    yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
            { "code" : "", "predicate_test" : predicateTest })
    header_output += BasicDeclare.subst(yieldIop)
    decoder_output += BasicConstructor.subst(yieldIop)
    exec_output += PredOpExecute.subst(yieldIop)

    wfeCode = '''
#if FULL_SYSTEM
    if (SevMailbox)
        SevMailbox = 0;
    else
        PseudoInst::quiesce(xc->tcBase());
#endif
    '''
    wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
            { "code" : wfeCode, "predicate_test" : predicateTest },
            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
    header_output += BasicDeclare.subst(wfeIop)
    decoder_output += BasicConstructor.subst(wfeIop)
    exec_output += PredOpExecute.subst(wfeIop)

    wfiCode = '''
#if FULL_SYSTEM
    PseudoInst::quiesce(xc->tcBase());
#endif
    '''
    wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
            { "code" : wfiCode, "predicate_test" : predicateTest },
            ["IsNonSpeculative", "IsQuiesce"])
    header_output += BasicDeclare.subst(wfiIop)
    decoder_output += BasicConstructor.subst(wfiIop)
    exec_output += PredOpExecute.subst(wfiIop)

    sevCode = '''
    // Need a way for O3 to not scoreboard these accesses as pipe flushes.
    System *sys = xc->tcBase()->getSystemPtr();
    for (int x = 0; x < sys->numContexts(); x++) {
        ThreadContext *oc = sys->getThreadContext(x);
        oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
    }
    '''
    sevIop = InstObjParams("sev", "SevInst", "PredOp", \
            { "code" : sevCode, "predicate_test" : predicateTest },
            ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
    header_output += BasicDeclare.subst(sevIop)
    decoder_output += BasicConstructor.subst(sevIop)
    exec_output += PredOpExecute.subst(sevIop)

    itIop = InstObjParams("it", "ItInst", "PredOp", \
            { "code" : "Itstate = machInst.newItstate;",
              "predicate_test" : predicateTest },
            ["IsNonSpeculative", "IsSerializeAfter"])
    header_output += BasicDeclare.subst(itIop)
    decoder_output += BasicConstructor.subst(itIop)
    exec_output += PredOpExecute.subst(itIop)
    unknownCode = '''
#if FULL_SYSTEM
            return new UndefinedInstruction;
#else
            return new UndefinedInstruction(machInst, true);
#endif
    '''
    unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
                               { "code": unknownCode,
                                 "predicate_test": predicateTest })
    header_output += BasicDeclare.subst(unknownIop)
    decoder_output += BasicConstructor.subst(unknownIop)
    exec_output += PredOpExecute.subst(unknownIop)

    ubfxCode = '''
        Dest = bits(Op1, imm2, imm1);
    '''
    ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
                            { "code": ubfxCode,
                              "predicate_test": predicateTest }, [])
    header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
    decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
    exec_output += PredOpExecute.subst(ubfxIop)

    sbfxCode = '''
        int32_t resTemp = bits(Op1, imm2, imm1);
        Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
    '''
    sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
                            { "code": sbfxCode,
                              "predicate_test": predicateTest }, [])
    header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
    decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
    exec_output += PredOpExecute.subst(sbfxIop)

    bfcCode = '''
        Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
    '''
    bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
                           { "code": bfcCode,
                             "predicate_test": predicateTest }, [])
    header_output += RegRegImmImmOpDeclare.subst(bfcIop)
    decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
    exec_output += PredOpExecute.subst(bfcIop)

    bfiCode = '''
        uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
        Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
    '''
    bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
                           { "code": bfiCode,
                             "predicate_test": predicateTest }, [])
    header_output += RegRegImmImmOpDeclare.subst(bfiIop)
    decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
    exec_output += PredOpExecute.subst(bfiIop)

    mrc15code = '''
    CPSR cpsr = Cpsr;
    if (cpsr.mode == MODE_USER)
#if FULL_SYSTEM
        return new UndefinedInstruction;
#else
        return new UndefinedInstruction(false, mnemonic);
#endif
    Dest = MiscOp1;
    '''

    mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
                             { "code": mrc15code,
                               "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(mrc15Iop)
    decoder_output += RegRegOpConstructor.subst(mrc15Iop)
    exec_output += PredOpExecute.subst(mrc15Iop)


    mcr15code = '''
    CPSR cpsr = Cpsr;
    if (cpsr.mode == MODE_USER)
#if FULL_SYSTEM
        return new UndefinedInstruction;
#else
        return new UndefinedInstruction(false, mnemonic);
#endif
    MiscDest = Op1;
    '''
    mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
                             { "code": mcr15code,
                               "predicate_test": predicateTest },
                               ["IsSerializeAfter","IsNonSpeculative"])
    header_output += RegRegOpDeclare.subst(mcr15Iop)
    decoder_output += RegRegOpConstructor.subst(mcr15Iop)
    exec_output += PredOpExecute.subst(mcr15Iop)

    mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
                                 { "code": "Dest = MiscOp1;",
                                   "predicate_test": predicateTest }, [])
    header_output += RegRegOpDeclare.subst(mrc15UserIop)
    decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
    exec_output += PredOpExecute.subst(mrc15UserIop)

    mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
                                 { "code": "MiscDest = Op1",
                                   "predicate_test": predicateTest },
                                   ["IsSerializeAfter","IsNonSpeculative"])
    header_output += RegRegOpDeclare.subst(mcr15UserIop)
    decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
    exec_output += PredOpExecute.subst(mcr15UserIop)

    enterxCode = '''
        ArmISA::PCState pc = PCS;
        pc.nextThumb(true);
        pc.nextJazelle(true);
        PCS = pc;
    '''
    enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
                              { "code": enterxCode,
                                "predicate_test": predicateTest }, [])
    header_output += BasicDeclare.subst(enterxIop)
    decoder_output += BasicConstructor.subst(enterxIop)
    exec_output += PredOpExecute.subst(enterxIop)

    leavexCode = '''
        ArmISA::PCState pc = PCS;
        pc.nextThumb(true);
        pc.nextJazelle(false);
        PCS = pc;
    '''
    leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
                              { "code": leavexCode,
                                "predicate_test": predicateTest }, [])
    header_output += BasicDeclare.subst(leavexIop)
    decoder_output += BasicConstructor.subst(leavexIop)
    exec_output += PredOpExecute.subst(leavexIop)

    setendCode = '''
        CPSR cpsr = Cpsr;
        cpsr.e = imm;
        Cpsr = cpsr;
    '''
    setendIop = InstObjParams("setend", "Setend", "ImmOp",
                              { "code": setendCode,
                                "predicate_test": predicateTest },
                              ["IsSerializeAfter","IsNonSpeculative"])
    header_output += ImmOpDeclare.subst(setendIop)
    decoder_output += ImmOpConstructor.subst(setendIop)
    exec_output += PredOpExecute.subst(setendIop)

    clrexCode = '''
        unsigned memAccessFlags = Request::CLEAR_LL |
            ArmISA::TLB::AlignWord | Request::LLSC;
        fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
    '''
    clrexIop = InstObjParams("clrex", "Clrex","PredOp",
                             { "code": clrexCode,
                               "predicate_test": predicateTest },[])
    header_output += ClrexDeclare.subst(clrexIop)
    decoder_output += BasicConstructor.subst(clrexIop)
    exec_output += PredOpExecute.subst(clrexIop)
    exec_output += ClrexInitiateAcc.subst(clrexIop)
    exec_output += ClrexCompleteAcc.subst(clrexIop)

    isbCode = '''
    '''
    isbIop = InstObjParams("isb", "Isb", "PredOp",
                             {"code": isbCode,
                               "predicate_test": predicateTest}, ['IsSerializing'])
    header_output += BasicDeclare.subst(isbIop)
    decoder_output += BasicConstructor.subst(isbIop)
    exec_output += PredOpExecute.subst(isbIop)

    dsbCode = '''
    '''
    dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
                             {"code": dsbCode,
                               "predicate_test": predicateTest},['IsMemBarrier'])
    header_output += BasicDeclare.subst(dsbIop)
    decoder_output += BasicConstructor.subst(dsbIop)
    exec_output += PredOpExecute.subst(dsbIop)

    dmbCode = '''
    '''
    dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
                             {"code": dmbCode,
                               "predicate_test": predicateTest},['IsMemBarrier'])
    header_output += BasicDeclare.subst(dmbIop)
    decoder_output += BasicConstructor.subst(dmbIop)
    exec_output += PredOpExecute.subst(dmbIop)

    dbgCode = '''
    '''
    dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
                             {"code": dbgCode,
                               "predicate_test": predicateTest})
    header_output += BasicDeclare.subst(dbgIop)
    decoder_output += BasicConstructor.subst(dbgIop)
    exec_output += PredOpExecute.subst(dbgIop)

    cpsCode = '''
    uint32_t mode = bits(imm, 4, 0);
    uint32_t f = bits(imm, 5);
    uint32_t i = bits(imm, 6);
    uint32_t a = bits(imm, 7);
    bool setMode = bits(imm, 8);
    bool enable = bits(imm, 9);
    CPSR cpsr = Cpsr;
    SCTLR sctlr = Sctlr;
    if (cpsr.mode != MODE_USER) {
        if (enable) {
            if (f) cpsr.f = 0;
            if (i) cpsr.i = 0;
            if (a) cpsr.a = 0;
        } else {
            if (f && !sctlr.nmfi) cpsr.f = 1;
            if (i) cpsr.i = 1;
            if (a) cpsr.a = 1;
        }
        if (setMode) {
            cpsr.mode = mode;
        }
    }
    Cpsr = cpsr;
    '''
    cpsIop = InstObjParams("cps", "Cps", "ImmOp",
                           { "code": cpsCode,
                             "predicate_test": predicateTest },
                           ["IsSerializeAfter","IsNonSpeculative"])
    header_output += ImmOpDeclare.subst(cpsIop)
    decoder_output += ImmOpConstructor.subst(cpsIop)
    exec_output += PredOpExecute.subst(cpsIop)
}};