mem.isa revision 7646:a444dbee8c07
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 class LoadStoreInst(object): 43 def __init__(self): 44 self.fullExecTemplate = eval(self.execBase + 'Execute') 45 self.initiateAccTemplate = eval(self.execBase + 'InitiateAcc') 46 self.completeAccTemplate = eval(self.execBase + 'CompleteAcc') 47 self.declareTemplate = eval(self.decConstBase + 'Declare') 48 self.constructTemplate = eval(self.decConstBase + 'Constructor') 49 50 def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags, 51 base = 'Memory', wbDecl = None): 52 # Make sure flags are in lists (convert to lists if not). 53 memFlags = makeList(memFlags) 54 instFlags = makeList(instFlags) 55 56 eaCode = codeBlobs["ea_code"] 57 58 # This shouldn't be part of the eaCode, but until the exec templates 59 # are converted over it's the easiest place to put it. 60 eaCode += '\n unsigned memAccessFlags = ' 61 eaCode += (string.join(memFlags, '|') + ';') 62 63 codeBlobs["ea_code"] = eaCode 64 65 macroName = Name 66 instFlagsCopy = list(instFlags) 67 codeBlobsCopy = dict(codeBlobs) 68 if wbDecl is not None: 69 instFlagsCopy.append('IsMicroop') 70 Name = Name + 'Acc' 71 codeBlobsCopy['acc_name'] = Name 72 codeBlobsCopy['wb_decl'] = wbDecl 73 codeBlobsCopy['use_uops'] = 0 74 75 iop = InstObjParams(name, Name, base, 76 codeBlobsCopy, instFlagsCopy) 77 78 header_output = self.declareTemplate.subst(iop) 79 decoder_output = self.constructTemplate.subst(iop) 80 exec_output = self.fullExecTemplate.subst(iop) + \ 81 self.initiateAccTemplate.subst(iop) + \ 82 self.completeAccTemplate.subst(iop) 83 84 if wbDecl is not None: 85 iop = InstObjParams(name, macroName, base, 86 { "wb_decl" : wbDecl, 87 "acc_name" : Name, 88 "use_uops" : 1 }, 89 ['IsMacroop']) 90 header_output += self.declareTemplate.subst(iop) 91 decoder_output += self.constructTemplate.subst(iop) 92 exec_output += PanicExecute.subst(iop) + \ 93 PanicInitiateAcc.subst(iop) + \ 94 PanicCompleteAcc.subst(iop) 95 96 return (header_output, decoder_output, exec_output) 97 98 def pickPredicate(blobs): 99 for val in blobs.values(): 100 if re.search('(?<!Opt)CondCodes', val): 101 return condPredicateTest 102 return predicateTest 103 104 def memClassName(base, post, add, writeback, \ 105 size=4, sign=False, user=False): 106 Name = base 107 108 parts = { "P" : post, "A" : add, "W" : writeback, 109 "S" : sign, "U" : user } 110 111 for (letter, val) in parts.items(): 112 if val: 113 Name += "_%sY" % letter 114 else: 115 Name += "_%sN" % letter 116 117 Name += ('_SZ%d' % size) 118 119 return Name 120 121 def buildMemSuffix(sign, size): 122 if size == 4: 123 memSuffix = '' 124 elif size == 2: 125 if sign: 126 memSuffix = '.sh' 127 else: 128 memSuffix = '.uh' 129 elif size == 1: 130 if sign: 131 memSuffix = '.sb' 132 else: 133 memSuffix = '.ub' 134 else: 135 raise Exception, "Unrecognized size for access %d" % size 136 137 return memSuffix 138 139 def buildMemBase(base, post, writeback): 140 if post and writeback: 141 base = "MemoryPostIndex<%s>" % base 142 elif not post and writeback: 143 base = "MemoryPreIndex<%s>" % base 144 elif not post and not writeback: 145 base = "MemoryOffset<%s>" % base 146 else: 147 raise Exception, "Illegal combination of post and writeback" 148 return base 149}}; 150 151