mem.isa revision 7205:e3dfcdf19561
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 def loadStoreBaseWork(name, Name, imm, swp, codeBlobs, memFlags, 42 instFlags, base = 'Memory', execTemplateBase = ''): 43 # Make sure flags are in lists (convert to lists if not). 44 memFlags = makeList(memFlags) 45 instFlags = makeList(instFlags) 46 47 eaCode = codeBlobs["ea_code"] 48 49 # This shouldn't be part of the eaCode, but until the exec templates 50 # are converted over it's the easiest place to put it. 51 eaCode += '\n unsigned memAccessFlags = ' 52 if memFlags: 53 eaCode += (string.join(memFlags, '|') + ';') 54 else: 55 eaCode += '0;' 56 57 codeBlobs["ea_code"] = eaCode 58 59 iop = InstObjParams(name, Name, base, codeBlobs, instFlags) 60 61 fullExecTemplate = eval(execTemplateBase + 'Execute') 62 initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc') 63 completeAccTemplate = eval(execTemplateBase + 'CompleteAcc') 64 65 if swp: 66 declareTemplate = SwapDeclare 67 constructTemplate = SwapConstructor 68 elif imm: 69 declareTemplate = LoadStoreImmDeclare 70 constructTemplate = LoadStoreImmConstructor 71 else: 72 declareTemplate = LoadStoreRegDeclare 73 constructTemplate = LoadStoreRegConstructor 74 75 # (header_output, decoder_output, decode_block, exec_output) 76 return (declareTemplate.subst(iop), 77 constructTemplate.subst(iop), 78 fullExecTemplate.subst(iop) 79 + initiateAccTemplate.subst(iop) 80 + completeAccTemplate.subst(iop)) 81 82 def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags, 83 instFlags, base = 'Memory', execTemplateBase = ''): 84 codeBlobs = { "ea_code": eaCode, 85 "memacc_code": accCode, 86 "predicate_test": predicateTest } 87 return loadStoreBaseWork(name, Name, imm, False, codeBlobs, memFlags, 88 instFlags, base, execTemplateBase) 89 90 def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags, 91 instFlags): 92 codeBlobs = { "ea_code": eaCode, 93 "preacc_code": preAccCode, 94 "postacc_code": postAccCode, 95 "predicate_test": predicateTest } 96 return loadStoreBaseWork(name, Name, False, True, codeBlobs, memFlags, 97 instFlags, 'Swap', 'Swap') 98 99 def memClassName(base, post, add, writeback, \ 100 size=4, sign=False, user=False): 101 Name = base 102 103 if post: 104 Name += '_PY' 105 else: 106 Name += '_PN' 107 108 if add: 109 Name += '_AY' 110 else: 111 Name += '_AN' 112 113 if writeback: 114 Name += '_WY' 115 else: 116 Name += '_WN' 117 118 Name += ('_SZ%d' % size) 119 120 if sign: 121 Name += '_SY' 122 else: 123 Name += '_SN' 124 125 if user: 126 Name += '_UY' 127 else: 128 Name += '_UN' 129 130 return Name 131 132 def buildMemSuffix(sign, size): 133 if size == 4: 134 memSuffix = '' 135 elif size == 2: 136 if sign: 137 memSuffix = '.sh' 138 else: 139 memSuffix = '.uh' 140 elif size == 1: 141 if sign: 142 memSuffix = '.sb' 143 else: 144 memSuffix = '.ub' 145 else: 146 raise Exception, "Unrecognized size for load %d" % size 147 148 return memSuffix 149 150 def buildMemBase(base, post, writeback): 151 if post and writeback: 152 base = "MemoryPostIndex<%s>" % base 153 elif not post and writeback: 154 base = "MemoryPreIndex<%s>" % base 155 elif not post and not writeback: 156 base = "MemoryOffset<%s>" % base 157 else: 158 raise Exception, "Illegal combination of post and writeback" 159 return base 160}}; 161 162