macromem.isa revision 7296:27c60324ec4d
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42// Gabe Black 43 44//////////////////////////////////////////////////////////////////// 45// 46// Load/store microops 47// 48 49let {{ 50 predicateTest = 'testPredicate(CondCodes, condCode)' 51}}; 52 53let {{ 54 microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 55 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 56 'MicroMemOp', 57 {'memacc_code': microLdrUopCode, 58 'ea_code': 'EA = Rb + (up ? imm : -imm);', 59 'predicate_test': predicateTest}, 60 ['IsMicroop']) 61 62 microLdrFpUopCode = "Fa = cSwap(Mem.uw, ((CPSR)Cpsr).e);" 63 microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 64 'MicroMemOp', 65 {'memacc_code': microLdrFpUopCode, 66 'ea_code': 'EA = Rb + (up ? imm : -imm);', 67 'predicate_test': predicateTest}, 68 ['IsMicroop']) 69 70 microLdrRetUopCode = ''' 71 CPSR cpsr = Cpsr; 72 uint32_t newCpsr = 73 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true); 74 Cpsr = ~CondCodesMask & newCpsr; 75 CondCodes = CondCodesMask & newCpsr; 76 IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 77 ''' 78 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 79 'MicroMemOp', 80 {'memacc_code': microLdrRetUopCode, 81 'ea_code': 82 'EA = Rb + (up ? imm : -imm);', 83 'predicate_test': predicateTest}, 84 ['IsMicroop']) 85 86 microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" 87 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 88 'MicroMemOp', 89 {'memacc_code': microStrUopCode, 90 'ea_code': 'EA = Rb + (up ? imm : -imm);', 91 'predicate_test': predicateTest}, 92 ['IsMicroop']) 93 94 microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);" 95 microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', 96 'MicroMemOp', 97 {'memacc_code': microStrFpUopCode, 98 'ea_code': 'EA = Rb + (up ? imm : -imm);', 99 'predicate_test': predicateTest}, 100 ['IsMicroop']) 101 102 header_output = decoder_output = exec_output = '' 103 104 loadIops = (microLdrUopIop, microLdrFpUopIop, microLdrRetUopIop) 105 storeIops = (microStrUopIop, microStrFpUopIop) 106 for iop in loadIops + storeIops: 107 header_output += MicroMemDeclare.subst(iop) 108 decoder_output += MicroMemConstructor.subst(iop) 109 for iop in loadIops: 110 exec_output += LoadExecute.subst(iop) + \ 111 LoadInitiateAcc.subst(iop) + \ 112 LoadCompleteAcc.subst(iop) 113 for iop in storeIops: 114 exec_output += StoreExecute.subst(iop) + \ 115 StoreInitiateAcc.subst(iop) + \ 116 StoreCompleteAcc.subst(iop) 117}}; 118 119//////////////////////////////////////////////////////////////////// 120// 121// Integer = Integer op Immediate microops 122// 123 124let {{ 125 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 126 'MicroIntOp', 127 {'code': 'Ra = Rb + imm;', 128 'predicate_test': predicateTest}, 129 ['IsMicroop']) 130 131 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 132 'MicroIntOp', 133 {'code': 'Ra = Rb - imm;', 134 'predicate_test': predicateTest}, 135 ['IsMicroop']) 136 137 header_output = MicroIntDeclare.subst(microAddiUopIop) + \ 138 MicroIntDeclare.subst(microSubiUopIop) 139 decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \ 140 MicroIntConstructor.subst(microSubiUopIop) 141 exec_output = PredOpExecute.subst(microAddiUopIop) + \ 142 PredOpExecute.subst(microSubiUopIop) 143}}; 144 145let {{ 146 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) 147 header_output = MacroMemDeclare.subst(iop) 148 decoder_output = MacroMemConstructor.subst(iop) 149 150 vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) 151 header_output += MacroVFPMemDeclare.subst(vfpIop) 152 decoder_output += MacroVFPMemConstructor.subst(vfpIop) 153}}; 154