xref: /gem5/src/arch/arm/isa/insts/macromem.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
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//
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// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
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// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
//          Gabe Black

////////////////////////////////////////////////////////////////////
//
// Load/store microops
//

let {{
    predicateTest = 'testPredicate(CondCodes, condCode)'
}};

let {{
    microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
                                   'MicroMemOp',
                                   {'memacc_code': 'Ra = Mem;',
                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
                                    'predicate_test': predicateTest},
                                   ['IsMicroop'])

    microLdrRetUopCode = '''
        Ra = Mem;
        uint32_t newCpsr =
            cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
        Cpsr = ~CondCodesMask & newCpsr;
        CondCodes = CondCodesMask & newCpsr;
    '''
    microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
                                      'MicroMemOp',
                                      {'memacc_code': microLdrRetUopCode,
                                       'ea_code':
                                          'EA = Rb + (up ? imm : -imm);',
                                       'predicate_test': predicateTest},
                                      ['IsMicroop'])

    microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
                                   'MicroMemOp',
                                   {'memacc_code': 'Mem = Ra;',
                                    'ea_code': 'EA = Rb + (up ? imm : -imm);',
                                    'predicate_test': predicateTest},
                                   ['IsMicroop'])

    header_output = MicroMemDeclare.subst(microLdrUopIop) + \
                    MicroMemDeclare.subst(microLdrRetUopIop) + \
                    MicroMemDeclare.subst(microStrUopIop)
    decoder_output = MicroMemConstructor.subst(microLdrUopIop) + \
                     MicroMemConstructor.subst(microLdrRetUopIop) + \
                     MicroMemConstructor.subst(microStrUopIop)
    exec_output = LoadExecute.subst(microLdrUopIop) + \
                  LoadExecute.subst(microLdrRetUopIop) + \
                  StoreExecute.subst(microStrUopIop) + \
                  LoadInitiateAcc.subst(microLdrUopIop) + \
                  LoadInitiateAcc.subst(microLdrRetUopIop) + \
                  StoreInitiateAcc.subst(microStrUopIop) + \
                  LoadCompleteAcc.subst(microLdrUopIop) + \
                  LoadCompleteAcc.subst(microLdrRetUopIop) + \
                  StoreCompleteAcc.subst(microStrUopIop)
}};

////////////////////////////////////////////////////////////////////
//
// Integer = Integer op Immediate microops
//

let {{
    microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
                                    'MicroIntOp',
                                    {'code': 'Ra = Rb + imm;',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])

    microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
                                    'MicroIntOp',
                                    {'code': 'Ra = Rb - imm;',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])

    header_output = MicroIntDeclare.subst(microAddiUopIop) + \
                    MicroIntDeclare.subst(microSubiUopIop)
    decoder_output = MicroIntConstructor.subst(microAddiUopIop) + \
                     MicroIntConstructor.subst(microSubiUopIop)
    exec_output = PredOpExecute.subst(microAddiUopIop) + \
                  PredOpExecute.subst(microSubiUopIop)
}};

let {{
    iop = InstObjParams("ldmstm", "LdmStm", 'PredMacroOp', "", [])
    header_output = MacroMemDeclare.subst(iop)
    decoder_output = MacroMemConstructor.subst(iop)
    exec_output = MacroMemExecute.subst(iop)
}};