macromem.isa revision 10037
16019SN/A// -*- mode:c++ -*- 26019SN/A 310037SARM gem5 Developers// Copyright (c) 2010-2013 ARM Limited 47134Sgblack@eecs.umich.edu// All rights reserved 57134Sgblack@eecs.umich.edu// 67134Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77134Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87134Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97134Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107134Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117134Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127134Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137134Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147134Sgblack@eecs.umich.edu// 156019SN/A// Copyright (c) 2007-2008 The Florida State University 166019SN/A// All rights reserved. 176019SN/A// 186019SN/A// Redistribution and use in source and binary forms, with or without 196019SN/A// modification, are permitted provided that the following conditions are 206019SN/A// met: redistributions of source code must retain the above copyright 216019SN/A// notice, this list of conditions and the following disclaimer; 226019SN/A// redistributions in binary form must reproduce the above copyright 236019SN/A// notice, this list of conditions and the following disclaimer in the 246019SN/A// documentation and/or other materials provided with the distribution; 256019SN/A// neither the name of the copyright holders nor the names of its 266019SN/A// contributors may be used to endorse or promote products derived from 276019SN/A// this software without specific prior written permission. 286019SN/A// 296019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019SN/A// 416019SN/A// Authors: Stephen Hines 426308SN/A// Gabe Black 436308SN/A 446309SN/A//////////////////////////////////////////////////////////////////// 456309SN/A// 466309SN/A// Load/store microops 476309SN/A// 486309SN/A 497134Sgblack@eecs.umich.edulet {{ 508588Sgblack@eecs.umich.edu microLdrUopCode = "IWRa = cSwap(Mem_uw, ((CPSR)Cpsr).e);" 516309SN/A microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop', 526309SN/A 'MicroMemOp', 537296Sgblack@eecs.umich.edu {'memacc_code': microLdrUopCode, 548139SMatt.Horsnell@arm.com 'ea_code': 'EA = URb + (up ? imm : -imm);', 556309SN/A 'predicate_test': predicateTest}, 566309SN/A ['IsMicroop']) 576309SN/A 588588Sgblack@eecs.umich.edu microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" 597174Sgblack@eecs.umich.edu microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 607639Sgblack@eecs.umich.edu 'MicroMemOp', 617639Sgblack@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 627644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + 638139SMatt.Horsnell@arm.com 'EA = URb + (up ? imm : -imm);', 647639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 657639Sgblack@eecs.umich.edu ['IsMicroop']) 667639Sgblack@eecs.umich.edu 678588Sgblack@eecs.umich.edu microLdrDBFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" 687639Sgblack@eecs.umich.edu microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', 697639Sgblack@eecs.umich.edu 'MicroMemOp', 707639Sgblack@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 717644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 728139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) + 737639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 747639Sgblack@eecs.umich.edu ''', 757639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 767639Sgblack@eecs.umich.edu ['IsMicroop']) 777639Sgblack@eecs.umich.edu 788588Sgblack@eecs.umich.edu microLdrDTFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" 797639Sgblack@eecs.umich.edu microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', 807639Sgblack@eecs.umich.edu 'MicroMemOp', 817639Sgblack@eecs.umich.edu {'memacc_code': microLdrFpUopCode, 827644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 838139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) - 847639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 857639Sgblack@eecs.umich.edu ''', 867639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 877639Sgblack@eecs.umich.edu ['IsMicroop']) 887174Sgblack@eecs.umich.edu 898148SAli.Saidi@ARM.com microRetUopCode = ''' 908303SAli.Saidi@ARM.com CPSR old_cpsr = Cpsr; 917400SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 928303SAli.Saidi@ARM.com 938303SAli.Saidi@ARM.com CPSR new_cpsr = 9410037SARM gem5 Developers cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF, true, 9510037SARM gem5 Developers sctlr.nmfi, xc->tcBase()); 968303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 978303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 988303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 998303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 1008303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 1018303SAli.Saidi@ARM.com IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0); 1028205SAli.Saidi@ARM.com NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) 1037858SMatt.Horsnell@arm.com | (((CPSR)Spsr).it1 & 0x3); 1048285SPrakash.Ramrakhyani@arm.com SevMailbox = 1; 1056754SN/A ''' 1068148SAli.Saidi@ARM.com 1076754SN/A microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop', 1086754SN/A 'MicroMemOp', 1098148SAli.Saidi@ARM.com {'memacc_code': 1108588Sgblack@eecs.umich.edu microRetUopCode % 'Mem_uw', 1116754SN/A 'ea_code': 1128139SMatt.Horsnell@arm.com 'EA = URb + (up ? imm : -imm);', 1137422Sgblack@eecs.umich.edu 'predicate_test': condPredicateTest}, 1148148SAli.Saidi@ARM.com ['IsMicroop','IsNonSpeculative', 1158148SAli.Saidi@ARM.com 'IsSerializeAfter']) 1166754SN/A 1178588Sgblack@eecs.umich.edu microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);" 1186309SN/A microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', 1196309SN/A 'MicroMemOp', 1207296Sgblack@eecs.umich.edu {'memacc_code': microStrUopCode, 1217303Sgblack@eecs.umich.edu 'postacc_code': "", 1228139SMatt.Horsnell@arm.com 'ea_code': 'EA = URb + (up ? imm : -imm);', 1236309SN/A 'predicate_test': predicateTest}, 1246309SN/A ['IsMicroop']) 1256309SN/A 1268588Sgblack@eecs.umich.edu microStrFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);" 1277174Sgblack@eecs.umich.edu microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop', 1287174Sgblack@eecs.umich.edu 'MicroMemOp', 1297296Sgblack@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1307303Sgblack@eecs.umich.edu 'postacc_code': "", 1317644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + 1328139SMatt.Horsnell@arm.com 'EA = URb + (up ? imm : -imm);', 1337174Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1347174Sgblack@eecs.umich.edu ['IsMicroop']) 1357174Sgblack@eecs.umich.edu 1368588Sgblack@eecs.umich.edu microStrDBFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);" 1377639Sgblack@eecs.umich.edu microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop', 1387639Sgblack@eecs.umich.edu 'MicroMemOp', 1397639Sgblack@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1407639Sgblack@eecs.umich.edu 'postacc_code': "", 1417644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 1428139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) + 1437639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 1447639Sgblack@eecs.umich.edu ''', 1457639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1467639Sgblack@eecs.umich.edu ['IsMicroop']) 1477639Sgblack@eecs.umich.edu 1488588Sgblack@eecs.umich.edu microStrDTFpUopCode = "Mem = cSwap(Fa_uw, ((CPSR)Cpsr).e);" 1497639Sgblack@eecs.umich.edu microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop', 1507639Sgblack@eecs.umich.edu 'MicroMemOp', 1517639Sgblack@eecs.umich.edu {'memacc_code': microStrFpUopCode, 1527639Sgblack@eecs.umich.edu 'postacc_code': "", 1537644Sali.saidi@arm.com 'ea_code': vfpEnabledCheckCode + ''' 1548139SMatt.Horsnell@arm.com EA = URb + (up ? imm : -imm) - 1557639Sgblack@eecs.umich.edu (((CPSR)Cpsr).e ? 4 : 0); 1567639Sgblack@eecs.umich.edu ''', 1577639Sgblack@eecs.umich.edu 'predicate_test': predicateTest}, 1587639Sgblack@eecs.umich.edu ['IsMicroop']) 1597639Sgblack@eecs.umich.edu 1607174Sgblack@eecs.umich.edu header_output = decoder_output = exec_output = '' 1617174Sgblack@eecs.umich.edu 16210037SARM gem5 Developers loadIops = (microLdrUopIop, microLdrRetUopIop, microLdrFpUopIop, 16310037SARM gem5 Developers microLdrDBFpUopIop, microLdrDTFpUopIop) 1647639Sgblack@eecs.umich.edu storeIops = (microStrUopIop, microStrFpUopIop, 1657639Sgblack@eecs.umich.edu microStrDBFpUopIop, microStrDTFpUopIop) 1667174Sgblack@eecs.umich.edu for iop in loadIops + storeIops: 1677174Sgblack@eecs.umich.edu header_output += MicroMemDeclare.subst(iop) 1687174Sgblack@eecs.umich.edu decoder_output += MicroMemConstructor.subst(iop) 1697174Sgblack@eecs.umich.edu for iop in loadIops: 1707174Sgblack@eecs.umich.edu exec_output += LoadExecute.subst(iop) + \ 1717174Sgblack@eecs.umich.edu LoadInitiateAcc.subst(iop) + \ 1727174Sgblack@eecs.umich.edu LoadCompleteAcc.subst(iop) 1737174Sgblack@eecs.umich.edu for iop in storeIops: 1747174Sgblack@eecs.umich.edu exec_output += StoreExecute.subst(iop) + \ 1757174Sgblack@eecs.umich.edu StoreInitiateAcc.subst(iop) + \ 1767174Sgblack@eecs.umich.edu StoreCompleteAcc.subst(iop) 1776309SN/A}}; 1786308SN/A 1797639Sgblack@eecs.umich.edulet {{ 1807639Sgblack@eecs.umich.edu exec_output = header_output = '' 1817639Sgblack@eecs.umich.edu 18210037SARM gem5 Developers eaCode = 'EA = XURa + imm;' 1837639Sgblack@eecs.umich.edu 1847639Sgblack@eecs.umich.edu for size in (1, 2, 3, 4, 6, 8, 12, 16): 1857639Sgblack@eecs.umich.edu # Set up the memory access. 1867639Sgblack@eecs.umich.edu regs = (size + 3) // 4 1877639Sgblack@eecs.umich.edu subst = { "size" : size, "regs" : regs } 1887639Sgblack@eecs.umich.edu memDecl = ''' 1897639Sgblack@eecs.umich.edu union MemUnion { 1907639Sgblack@eecs.umich.edu uint8_t bytes[%(size)d]; 1917639Sgblack@eecs.umich.edu Element elements[%(size)d / sizeof(Element)]; 1927639Sgblack@eecs.umich.edu uint32_t floatRegBits[%(regs)d]; 1937639Sgblack@eecs.umich.edu }; 1947639Sgblack@eecs.umich.edu ''' % subst 1957639Sgblack@eecs.umich.edu 1967639Sgblack@eecs.umich.edu # Do endian conversion for all the elements. 1977639Sgblack@eecs.umich.edu convCode = ''' 1987639Sgblack@eecs.umich.edu const unsigned eCount = sizeof(memUnion.elements) / 1997639Sgblack@eecs.umich.edu sizeof(memUnion.elements[0]); 2007639Sgblack@eecs.umich.edu if (((CPSR)Cpsr).e) { 2017639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 2027639Sgblack@eecs.umich.edu memUnion.elements[i] = gtobe(memUnion.elements[i]); 2037639Sgblack@eecs.umich.edu } 2047639Sgblack@eecs.umich.edu } else { 2057639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 2067639Sgblack@eecs.umich.edu memUnion.elements[i] = gtole(memUnion.elements[i]); 2077639Sgblack@eecs.umich.edu } 2087639Sgblack@eecs.umich.edu } 2097639Sgblack@eecs.umich.edu ''' 2107639Sgblack@eecs.umich.edu 2117639Sgblack@eecs.umich.edu # Offload everything into registers 2127639Sgblack@eecs.umich.edu regSetCode = '' 2137639Sgblack@eecs.umich.edu for reg in range(regs): 2147639Sgblack@eecs.umich.edu mask = '' 2157639Sgblack@eecs.umich.edu if reg == regs - 1: 2167639Sgblack@eecs.umich.edu mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size)) 2177639Sgblack@eecs.umich.edu regSetCode += ''' 2188588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s; 2197639Sgblack@eecs.umich.edu ''' % { "reg" : reg, "mask" : mask } 2207639Sgblack@eecs.umich.edu 2217639Sgblack@eecs.umich.edu # Pull everything in from registers 2227639Sgblack@eecs.umich.edu regGetCode = '' 2237639Sgblack@eecs.umich.edu for reg in range(regs): 2247639Sgblack@eecs.umich.edu regGetCode += ''' 2258588Sgblack@eecs.umich.edu memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d_uw); 2267639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 2277639Sgblack@eecs.umich.edu 2287639Sgblack@eecs.umich.edu loadMemAccCode = convCode + regSetCode 2297639Sgblack@eecs.umich.edu storeMemAccCode = regGetCode + convCode 2307639Sgblack@eecs.umich.edu 2317639Sgblack@eecs.umich.edu loadIop = InstObjParams('ldrneon%(size)d_uop' % subst, 2327639Sgblack@eecs.umich.edu 'MicroLdrNeon%(size)dUop' % subst, 2337639Sgblack@eecs.umich.edu 'MicroNeonMemOp', 2347639Sgblack@eecs.umich.edu { 'mem_decl' : memDecl, 2357639Sgblack@eecs.umich.edu 'size' : size, 2367639Sgblack@eecs.umich.edu 'memacc_code' : loadMemAccCode, 2377644Sali.saidi@arm.com 'ea_code' : simdEnabledCheckCode + eaCode, 2387639Sgblack@eecs.umich.edu 'predicate_test' : predicateTest }, 2397639Sgblack@eecs.umich.edu [ 'IsMicroop', 'IsMemRef', 'IsLoad' ]) 2407639Sgblack@eecs.umich.edu storeIop = InstObjParams('strneon%(size)d_uop' % subst, 2417639Sgblack@eecs.umich.edu 'MicroStrNeon%(size)dUop' % subst, 2427639Sgblack@eecs.umich.edu 'MicroNeonMemOp', 2437639Sgblack@eecs.umich.edu { 'mem_decl' : memDecl, 2447639Sgblack@eecs.umich.edu 'size' : size, 2457639Sgblack@eecs.umich.edu 'memacc_code' : storeMemAccCode, 2467644Sali.saidi@arm.com 'ea_code' : simdEnabledCheckCode + eaCode, 2477639Sgblack@eecs.umich.edu 'predicate_test' : predicateTest }, 2487639Sgblack@eecs.umich.edu [ 'IsMicroop', 'IsMemRef', 'IsStore' ]) 2497639Sgblack@eecs.umich.edu 2507639Sgblack@eecs.umich.edu exec_output += NeonLoadExecute.subst(loadIop) + \ 2517639Sgblack@eecs.umich.edu NeonLoadInitiateAcc.subst(loadIop) + \ 2527639Sgblack@eecs.umich.edu NeonLoadCompleteAcc.subst(loadIop) + \ 2537639Sgblack@eecs.umich.edu NeonStoreExecute.subst(storeIop) + \ 2547639Sgblack@eecs.umich.edu NeonStoreInitiateAcc.subst(storeIop) + \ 2557639Sgblack@eecs.umich.edu NeonStoreCompleteAcc.subst(storeIop) 2567639Sgblack@eecs.umich.edu header_output += MicroNeonMemDeclare.subst(loadIop) + \ 2577639Sgblack@eecs.umich.edu MicroNeonMemDeclare.subst(storeIop) 2587639Sgblack@eecs.umich.edu}}; 2597639Sgblack@eecs.umich.edu 2607639Sgblack@eecs.umich.edulet {{ 2617639Sgblack@eecs.umich.edu exec_output = '' 2627639Sgblack@eecs.umich.edu for eSize, type in (1, 'uint8_t'), \ 2637639Sgblack@eecs.umich.edu (2, 'uint16_t'), \ 2647639Sgblack@eecs.umich.edu (4, 'uint32_t'), \ 2657639Sgblack@eecs.umich.edu (8, 'uint64_t'): 2667639Sgblack@eecs.umich.edu size = eSize 2677639Sgblack@eecs.umich.edu # An instruction handles no more than 16 bytes and no more than 2687639Sgblack@eecs.umich.edu # 4 elements, or the number of elements needed to fill 8 or 16 bytes. 2697639Sgblack@eecs.umich.edu sizes = set((16, 8)) 2707639Sgblack@eecs.umich.edu for count in 1, 2, 3, 4: 2717639Sgblack@eecs.umich.edu size = count * eSize 2727639Sgblack@eecs.umich.edu if size <= 16: 2737639Sgblack@eecs.umich.edu sizes.add(size) 2747639Sgblack@eecs.umich.edu for size in sizes: 2757639Sgblack@eecs.umich.edu substDict = { 2767639Sgblack@eecs.umich.edu "class_name" : "MicroLdrNeon%dUop" % size, 2777639Sgblack@eecs.umich.edu "targs" : type 2787639Sgblack@eecs.umich.edu } 2797639Sgblack@eecs.umich.edu exec_output += MicroNeonMemExecDeclare.subst(substDict) 2807639Sgblack@eecs.umich.edu substDict["class_name"] = "MicroStrNeon%dUop" % size 2817639Sgblack@eecs.umich.edu exec_output += MicroNeonMemExecDeclare.subst(substDict) 2827639Sgblack@eecs.umich.edu size += eSize 2837639Sgblack@eecs.umich.edu}}; 2847639Sgblack@eecs.umich.edu 2857639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 2867639Sgblack@eecs.umich.edu// 2877639Sgblack@eecs.umich.edu// Neon (de)interlacing microops 2887639Sgblack@eecs.umich.edu// 2897639Sgblack@eecs.umich.edu 2907639Sgblack@eecs.umich.edulet {{ 2917639Sgblack@eecs.umich.edu header_output = exec_output = '' 2927639Sgblack@eecs.umich.edu for dRegs in (2, 3, 4): 2937639Sgblack@eecs.umich.edu loadConv = '' 2947639Sgblack@eecs.umich.edu unloadConv = '' 2957639Sgblack@eecs.umich.edu for dReg in range(dRegs): 2967639Sgblack@eecs.umich.edu loadConv += ''' 2978588Sgblack@eecs.umich.edu conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d_uw); 2988588Sgblack@eecs.umich.edu conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d_uw); 2997639Sgblack@eecs.umich.edu ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } 3007639Sgblack@eecs.umich.edu unloadConv += ''' 3018588Sgblack@eecs.umich.edu FpDestS%(dReg)dP0_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]); 3028588Sgblack@eecs.umich.edu FpDestS%(dReg)dP1_uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]); 3037639Sgblack@eecs.umich.edu ''' % { "dReg" : dReg } 3047639Sgblack@eecs.umich.edu microDeintNeonCode = ''' 3057639Sgblack@eecs.umich.edu const unsigned dRegs = %(dRegs)d; 3067639Sgblack@eecs.umich.edu const unsigned regs = 2 * dRegs; 3077639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 3087639Sgblack@eecs.umich.edu sizeof(Element); 3097639Sgblack@eecs.umich.edu union convStruct { 3107639Sgblack@eecs.umich.edu FloatRegBits cRegs[regs]; 3117639Sgblack@eecs.umich.edu Element elements[dRegs * perDReg]; 3127639Sgblack@eecs.umich.edu } conv1, conv2; 3137639Sgblack@eecs.umich.edu 3147639Sgblack@eecs.umich.edu %(loadConv)s 3157639Sgblack@eecs.umich.edu 3167639Sgblack@eecs.umich.edu unsigned srcElem = 0; 3177639Sgblack@eecs.umich.edu for (unsigned destOffset = 0; 3187639Sgblack@eecs.umich.edu destOffset < perDReg; destOffset++) { 3197639Sgblack@eecs.umich.edu for (unsigned dReg = 0; dReg < dRegs; dReg++) { 3207639Sgblack@eecs.umich.edu conv2.elements[dReg * perDReg + destOffset] = 3217639Sgblack@eecs.umich.edu conv1.elements[srcElem++]; 3227639Sgblack@eecs.umich.edu } 3237639Sgblack@eecs.umich.edu } 3247639Sgblack@eecs.umich.edu 3257639Sgblack@eecs.umich.edu %(unloadConv)s 3267639Sgblack@eecs.umich.edu ''' % { "dRegs" : dRegs, 3277639Sgblack@eecs.umich.edu "loadConv" : loadConv, 3287639Sgblack@eecs.umich.edu "unloadConv" : unloadConv } 3297639Sgblack@eecs.umich.edu microDeintNeonIop = \ 3307639Sgblack@eecs.umich.edu InstObjParams('deintneon%duop' % (dRegs * 2), 3317639Sgblack@eecs.umich.edu 'MicroDeintNeon%dUop' % (dRegs * 2), 3327639Sgblack@eecs.umich.edu 'MicroNeonMixOp', 3337639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 3347639Sgblack@eecs.umich.edu 'code' : microDeintNeonCode }, 3357639Sgblack@eecs.umich.edu ['IsMicroop']) 3367639Sgblack@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microDeintNeonIop) 3377639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microDeintNeonIop) 3387639Sgblack@eecs.umich.edu 3397639Sgblack@eecs.umich.edu loadConv = '' 3407639Sgblack@eecs.umich.edu unloadConv = '' 3417639Sgblack@eecs.umich.edu for dReg in range(dRegs): 3427639Sgblack@eecs.umich.edu loadConv += ''' 3438588Sgblack@eecs.umich.edu conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0_uw); 3448588Sgblack@eecs.umich.edu conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1_uw); 3457639Sgblack@eecs.umich.edu ''' % { "dReg" : dReg } 3467639Sgblack@eecs.umich.edu unloadConv += ''' 3478588Sgblack@eecs.umich.edu FpDestP%(sReg0)d_uw = gtoh(conv2.cRegs[%(sReg0)d]); 3488588Sgblack@eecs.umich.edu FpDestP%(sReg1)d_uw = gtoh(conv2.cRegs[%(sReg1)d]); 3497639Sgblack@eecs.umich.edu ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) } 3507639Sgblack@eecs.umich.edu microInterNeonCode = ''' 3517639Sgblack@eecs.umich.edu const unsigned dRegs = %(dRegs)d; 3527639Sgblack@eecs.umich.edu const unsigned regs = 2 * dRegs; 3537639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 3547639Sgblack@eecs.umich.edu sizeof(Element); 3557639Sgblack@eecs.umich.edu union convStruct { 3567639Sgblack@eecs.umich.edu FloatRegBits cRegs[regs]; 3577639Sgblack@eecs.umich.edu Element elements[dRegs * perDReg]; 3587639Sgblack@eecs.umich.edu } conv1, conv2; 3597639Sgblack@eecs.umich.edu 3607639Sgblack@eecs.umich.edu %(loadConv)s 3617639Sgblack@eecs.umich.edu 3627639Sgblack@eecs.umich.edu unsigned destElem = 0; 3637639Sgblack@eecs.umich.edu for (unsigned srcOffset = 0; 3647639Sgblack@eecs.umich.edu srcOffset < perDReg; srcOffset++) { 3657639Sgblack@eecs.umich.edu for (unsigned dReg = 0; dReg < dRegs; dReg++) { 3667639Sgblack@eecs.umich.edu conv2.elements[destElem++] = 3677639Sgblack@eecs.umich.edu conv1.elements[dReg * perDReg + srcOffset]; 3687639Sgblack@eecs.umich.edu } 3697639Sgblack@eecs.umich.edu } 3707639Sgblack@eecs.umich.edu 3717639Sgblack@eecs.umich.edu %(unloadConv)s 3727639Sgblack@eecs.umich.edu ''' % { "dRegs" : dRegs, 3737639Sgblack@eecs.umich.edu "loadConv" : loadConv, 3747639Sgblack@eecs.umich.edu "unloadConv" : unloadConv } 3757639Sgblack@eecs.umich.edu microInterNeonIop = \ 3767639Sgblack@eecs.umich.edu InstObjParams('interneon%duop' % (dRegs * 2), 3777639Sgblack@eecs.umich.edu 'MicroInterNeon%dUop' % (dRegs * 2), 3787639Sgblack@eecs.umich.edu 'MicroNeonMixOp', 3797639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 3807639Sgblack@eecs.umich.edu 'code' : microInterNeonCode }, 3817639Sgblack@eecs.umich.edu ['IsMicroop']) 3827639Sgblack@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microInterNeonIop) 3837639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microInterNeonIop) 3847639Sgblack@eecs.umich.edu}}; 3857639Sgblack@eecs.umich.edu 3867639Sgblack@eecs.umich.edulet {{ 3877639Sgblack@eecs.umich.edu exec_output = '' 3887639Sgblack@eecs.umich.edu for type in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'): 3897639Sgblack@eecs.umich.edu for dRegs in (2, 3, 4): 3907639Sgblack@eecs.umich.edu Name = "MicroDeintNeon%dUop" % (dRegs * 2) 3917639Sgblack@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 3927639Sgblack@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 3937639Sgblack@eecs.umich.edu Name = "MicroInterNeon%dUop" % (dRegs * 2) 3947639Sgblack@eecs.umich.edu substDict = { "class_name" : Name, "targs" : type } 3957639Sgblack@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 3967639Sgblack@eecs.umich.edu}}; 3977639Sgblack@eecs.umich.edu 3987639Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 3997639Sgblack@eecs.umich.edu// 4007639Sgblack@eecs.umich.edu// Neon microops to pack/unpack a single lane 4017639Sgblack@eecs.umich.edu// 4027639Sgblack@eecs.umich.edu 4037639Sgblack@eecs.umich.edulet {{ 4047639Sgblack@eecs.umich.edu header_output = exec_output = '' 4057639Sgblack@eecs.umich.edu for sRegs in 1, 2: 4067639Sgblack@eecs.umich.edu baseLoadRegs = '' 4077639Sgblack@eecs.umich.edu for reg in range(sRegs): 4087639Sgblack@eecs.umich.edu baseLoadRegs += ''' 4098588Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw); 4108588Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw); 4117639Sgblack@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 4127639Sgblack@eecs.umich.edu "reg1" : (2 * reg + 1) } 4137639Sgblack@eecs.umich.edu for dRegs in range(sRegs, 5): 4147639Sgblack@eecs.umich.edu unloadRegs = '' 4157639Sgblack@eecs.umich.edu loadRegs = baseLoadRegs 4167639Sgblack@eecs.umich.edu for reg in range(dRegs): 4177639Sgblack@eecs.umich.edu loadRegs += ''' 4188588Sgblack@eecs.umich.edu destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0_uw); 4198588Sgblack@eecs.umich.edu destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1_uw); 4207639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 4217639Sgblack@eecs.umich.edu unloadRegs += ''' 4228588Sgblack@eecs.umich.edu FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]); 4238588Sgblack@eecs.umich.edu FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]); 4247639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 4257639Sgblack@eecs.umich.edu microUnpackNeonCode = ''' 4267639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 4277639Sgblack@eecs.umich.edu sizeof(Element); 4287639Sgblack@eecs.umich.edu 4297639Sgblack@eecs.umich.edu union SourceRegs { 4307639Sgblack@eecs.umich.edu FloatRegBits fRegs[2 * %(sRegs)d]; 4317639Sgblack@eecs.umich.edu Element elements[%(sRegs)d * perDReg]; 4327639Sgblack@eecs.umich.edu } sourceRegs; 4337639Sgblack@eecs.umich.edu 4347639Sgblack@eecs.umich.edu union DestReg { 4357639Sgblack@eecs.umich.edu FloatRegBits fRegs[2]; 4367639Sgblack@eecs.umich.edu Element elements[perDReg]; 4377639Sgblack@eecs.umich.edu } destRegs[%(dRegs)d]; 4387639Sgblack@eecs.umich.edu 4397639Sgblack@eecs.umich.edu %(loadRegs)s 4407639Sgblack@eecs.umich.edu 4417639Sgblack@eecs.umich.edu for (unsigned i = 0; i < %(dRegs)d; i++) { 4427639Sgblack@eecs.umich.edu destRegs[i].elements[lane] = sourceRegs.elements[i]; 4437639Sgblack@eecs.umich.edu } 4447639Sgblack@eecs.umich.edu 4457639Sgblack@eecs.umich.edu %(unloadRegs)s 4467639Sgblack@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 4477639Sgblack@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 4487639Sgblack@eecs.umich.edu 4497639Sgblack@eecs.umich.edu microUnpackNeonIop = \ 4507639Sgblack@eecs.umich.edu InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2), 4517639Sgblack@eecs.umich.edu 'MicroUnpackNeon%dto%dUop' % 4527639Sgblack@eecs.umich.edu (sRegs * 2, dRegs * 2), 4537639Sgblack@eecs.umich.edu 'MicroNeonMixLaneOp', 4547639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 4557639Sgblack@eecs.umich.edu 'code' : microUnpackNeonCode }, 4567639Sgblack@eecs.umich.edu ['IsMicroop']) 4577639Sgblack@eecs.umich.edu header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop) 4587639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop) 4597639Sgblack@eecs.umich.edu 4607639Sgblack@eecs.umich.edu for sRegs in 1, 2: 4617639Sgblack@eecs.umich.edu loadRegs = '' 4627639Sgblack@eecs.umich.edu for reg in range(sRegs): 4637639Sgblack@eecs.umich.edu loadRegs += ''' 4648588Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d_uw); 4658588Sgblack@eecs.umich.edu sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d_uw); 4667639Sgblack@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 4677639Sgblack@eecs.umich.edu "reg1" : (2 * reg + 1) } 4687639Sgblack@eecs.umich.edu for dRegs in range(sRegs, 5): 4697639Sgblack@eecs.umich.edu unloadRegs = '' 4707639Sgblack@eecs.umich.edu for reg in range(dRegs): 4717639Sgblack@eecs.umich.edu unloadRegs += ''' 4728588Sgblack@eecs.umich.edu FpDestS%(reg)dP0_uw = gtoh(destRegs[%(reg)d].fRegs[0]); 4738588Sgblack@eecs.umich.edu FpDestS%(reg)dP1_uw = gtoh(destRegs[%(reg)d].fRegs[1]); 4747639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 4757639Sgblack@eecs.umich.edu microUnpackAllNeonCode = ''' 4767639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 4777639Sgblack@eecs.umich.edu sizeof(Element); 4787639Sgblack@eecs.umich.edu 4797639Sgblack@eecs.umich.edu union SourceRegs { 4807639Sgblack@eecs.umich.edu FloatRegBits fRegs[2 * %(sRegs)d]; 4817639Sgblack@eecs.umich.edu Element elements[%(sRegs)d * perDReg]; 4827639Sgblack@eecs.umich.edu } sourceRegs; 4837639Sgblack@eecs.umich.edu 4847639Sgblack@eecs.umich.edu union DestReg { 4857639Sgblack@eecs.umich.edu FloatRegBits fRegs[2]; 4867639Sgblack@eecs.umich.edu Element elements[perDReg]; 4877639Sgblack@eecs.umich.edu } destRegs[%(dRegs)d]; 4887639Sgblack@eecs.umich.edu 4897639Sgblack@eecs.umich.edu %(loadRegs)s 4907639Sgblack@eecs.umich.edu 4917639Sgblack@eecs.umich.edu for (unsigned i = 0; i < %(dRegs)d; i++) { 4927639Sgblack@eecs.umich.edu for (unsigned j = 0; j < perDReg; j++) 4937639Sgblack@eecs.umich.edu destRegs[i].elements[j] = sourceRegs.elements[i]; 4947639Sgblack@eecs.umich.edu } 4957639Sgblack@eecs.umich.edu 4967639Sgblack@eecs.umich.edu %(unloadRegs)s 4977639Sgblack@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 4987639Sgblack@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 4997639Sgblack@eecs.umich.edu 5007639Sgblack@eecs.umich.edu microUnpackAllNeonIop = \ 5017639Sgblack@eecs.umich.edu InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2), 5027639Sgblack@eecs.umich.edu 'MicroUnpackAllNeon%dto%dUop' % 5037639Sgblack@eecs.umich.edu (sRegs * 2, dRegs * 2), 5047639Sgblack@eecs.umich.edu 'MicroNeonMixOp', 5057639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 5067639Sgblack@eecs.umich.edu 'code' : microUnpackAllNeonCode }, 5077639Sgblack@eecs.umich.edu ['IsMicroop']) 5087639Sgblack@eecs.umich.edu header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop) 5097639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop) 5107639Sgblack@eecs.umich.edu 5117639Sgblack@eecs.umich.edu for dRegs in 1, 2: 5127639Sgblack@eecs.umich.edu unloadRegs = '' 5137639Sgblack@eecs.umich.edu for reg in range(dRegs): 5147639Sgblack@eecs.umich.edu unloadRegs += ''' 5158588Sgblack@eecs.umich.edu FpDestP%(reg0)d_uw = gtoh(destRegs.fRegs[%(reg0)d]); 5168588Sgblack@eecs.umich.edu FpDestP%(reg1)d_uw = gtoh(destRegs.fRegs[%(reg1)d]); 5177639Sgblack@eecs.umich.edu ''' % { "reg0" : (2 * reg + 0), 5187639Sgblack@eecs.umich.edu "reg1" : (2 * reg + 1) } 5197639Sgblack@eecs.umich.edu for sRegs in range(dRegs, 5): 5207639Sgblack@eecs.umich.edu loadRegs = '' 5217639Sgblack@eecs.umich.edu for reg in range(sRegs): 5227639Sgblack@eecs.umich.edu loadRegs += ''' 5238588Sgblack@eecs.umich.edu sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0_uw); 5248588Sgblack@eecs.umich.edu sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1_uw); 5257639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 5267639Sgblack@eecs.umich.edu microPackNeonCode = ''' 5277639Sgblack@eecs.umich.edu const unsigned perDReg = (2 * sizeof(FloatRegBits)) / 5287639Sgblack@eecs.umich.edu sizeof(Element); 5297639Sgblack@eecs.umich.edu 5307639Sgblack@eecs.umich.edu union SourceReg { 5317639Sgblack@eecs.umich.edu FloatRegBits fRegs[2]; 5327639Sgblack@eecs.umich.edu Element elements[perDReg]; 5337639Sgblack@eecs.umich.edu } sourceRegs[%(sRegs)d]; 5347639Sgblack@eecs.umich.edu 5357639Sgblack@eecs.umich.edu union DestRegs { 5367639Sgblack@eecs.umich.edu FloatRegBits fRegs[2 * %(dRegs)d]; 5377639Sgblack@eecs.umich.edu Element elements[%(dRegs)d * perDReg]; 5387639Sgblack@eecs.umich.edu } destRegs; 5397639Sgblack@eecs.umich.edu 5407639Sgblack@eecs.umich.edu %(loadRegs)s 5417639Sgblack@eecs.umich.edu 5427639Sgblack@eecs.umich.edu for (unsigned i = 0; i < %(sRegs)d; i++) { 5437639Sgblack@eecs.umich.edu destRegs.elements[i] = sourceRegs[i].elements[lane]; 5447639Sgblack@eecs.umich.edu } 5458309Snate@binkert.org for (unsigned i = %(sRegs)d; i < %(dRegs)d * perDReg; ++i) { 5468309Snate@binkert.org destRegs.elements[i] = 0; 5478309Snate@binkert.org } 5487639Sgblack@eecs.umich.edu 5497639Sgblack@eecs.umich.edu %(unloadRegs)s 5507639Sgblack@eecs.umich.edu ''' % { "sRegs" : sRegs, "dRegs" : dRegs, 5517639Sgblack@eecs.umich.edu "loadRegs" : loadRegs, "unloadRegs" : unloadRegs } 5527639Sgblack@eecs.umich.edu 5537639Sgblack@eecs.umich.edu microPackNeonIop = \ 5547639Sgblack@eecs.umich.edu InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2), 5557639Sgblack@eecs.umich.edu 'MicroPackNeon%dto%dUop' % 5567639Sgblack@eecs.umich.edu (sRegs * 2, dRegs * 2), 5577639Sgblack@eecs.umich.edu 'MicroNeonMixLaneOp', 5587639Sgblack@eecs.umich.edu { 'predicate_test': predicateTest, 5597639Sgblack@eecs.umich.edu 'code' : microPackNeonCode }, 5607639Sgblack@eecs.umich.edu ['IsMicroop']) 5617639Sgblack@eecs.umich.edu header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop) 5627639Sgblack@eecs.umich.edu exec_output += MicroNeonMixExecute.subst(microPackNeonIop) 5637639Sgblack@eecs.umich.edu}}; 5647639Sgblack@eecs.umich.edu 5657639Sgblack@eecs.umich.edulet {{ 5667639Sgblack@eecs.umich.edu exec_output = '' 5678607Sgblack@eecs.umich.edu for typeSize in (8, 16, 32): 5687639Sgblack@eecs.umich.edu for sRegs in 1, 2: 5698607Sgblack@eecs.umich.edu for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)): 5707639Sgblack@eecs.umich.edu for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", 5717639Sgblack@eecs.umich.edu "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", 5727639Sgblack@eecs.umich.edu "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): 5737639Sgblack@eecs.umich.edu Name = format % { "sRegs" : sRegs * 2, 5747639Sgblack@eecs.umich.edu "dRegs" : dRegs * 2 } 5758607Sgblack@eecs.umich.edu substDict = { "class_name" : Name, 5768607Sgblack@eecs.umich.edu "targs" : "uint%d_t" % typeSize } 5777639Sgblack@eecs.umich.edu exec_output += MicroNeonExecDeclare.subst(substDict) 5787639Sgblack@eecs.umich.edu}}; 5797639Sgblack@eecs.umich.edu 5806308SN/A//////////////////////////////////////////////////////////////////// 5816308SN/A// 5826308SN/A// Integer = Integer op Immediate microops 5836308SN/A// 5846308SN/A 5856308SN/Alet {{ 5866308SN/A microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop', 5877639Sgblack@eecs.umich.edu 'MicroIntImmOp', 5888139SMatt.Horsnell@arm.com {'code': 'URa = URb + imm;', 5896308SN/A 'predicate_test': predicateTest}, 5906308SN/A ['IsMicroop']) 5916308SN/A 5928304SAli.Saidi@ARM.com microAddUopCode = ''' 5938304SAli.Saidi@ARM.com URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC); 5948304SAli.Saidi@ARM.com ''' 5958304SAli.Saidi@ARM.com 59610037SARM gem5 Developers microAddXiUopIop = InstObjParams('addxi_uop', 'MicroAddXiUop', 59710037SARM gem5 Developers 'MicroIntImmXOp', 59810037SARM gem5 Developers 'XURa = XURb + imm;', 59910037SARM gem5 Developers ['IsMicroop']) 60010037SARM gem5 Developers 60110037SARM gem5 Developers microAddXiSpAlignUopIop = InstObjParams('addxi_uop', 'MicroAddXiSpAlignUop', 60210037SARM gem5 Developers 'MicroIntImmXOp', ''' 60310037SARM gem5 Developers if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) && 60410037SARM gem5 Developers SPAlignmentCheckEnabled(xc->tcBase())) { 60510037SARM gem5 Developers return new SPAlignmentFault(); 60610037SARM gem5 Developers } 60710037SARM gem5 Developers XURa = XURb + imm; 60810037SARM gem5 Developers ''', ['IsMicroop']) 60910037SARM gem5 Developers 61010037SARM gem5 Developers microAddXERegUopIop = InstObjParams('addxr_uop', 'MicroAddXERegUop', 61110037SARM gem5 Developers 'MicroIntRegXOp', 61210037SARM gem5 Developers 'XURa = XURb + ' + \ 61310037SARM gem5 Developers 'extendReg64(XURc, type, shiftAmt, 64);', 61410037SARM gem5 Developers ['IsMicroop']) 61510037SARM gem5 Developers 6167639Sgblack@eecs.umich.edu microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', 6177646Sgene.wu@arm.com 'MicroIntRegOp', 6188304SAli.Saidi@ARM.com {'code': microAddUopCode, 6198304SAli.Saidi@ARM.com 'predicate_test': pickPredicate(microAddUopCode)}, 6207639Sgblack@eecs.umich.edu ['IsMicroop']) 6217639Sgblack@eecs.umich.edu 6226308SN/A microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop', 6237639Sgblack@eecs.umich.edu 'MicroIntImmOp', 6248139SMatt.Horsnell@arm.com {'code': 'URa = URb - imm;', 6256308SN/A 'predicate_test': predicateTest}, 6266308SN/A ['IsMicroop']) 6276308SN/A 62810037SARM gem5 Developers microSubXiUopIop = InstObjParams('subxi_uop', 'MicroSubXiUop', 62910037SARM gem5 Developers 'MicroIntImmXOp', 63010037SARM gem5 Developers 'XURa = XURb - imm;', 63110037SARM gem5 Developers ['IsMicroop']) 63210037SARM gem5 Developers 6338304SAli.Saidi@ARM.com microSubUopCode = ''' 6348304SAli.Saidi@ARM.com URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, OptShiftRmCondCodesC); 6358304SAli.Saidi@ARM.com ''' 6367646Sgene.wu@arm.com microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', 6377646Sgene.wu@arm.com 'MicroIntRegOp', 6388304SAli.Saidi@ARM.com {'code': microSubUopCode, 6398304SAli.Saidi@ARM.com 'predicate_test': pickPredicate(microSubUopCode)}, 6407646Sgene.wu@arm.com ['IsMicroop']) 6417646Sgene.wu@arm.com 6427646Sgene.wu@arm.com microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', 6437646Sgene.wu@arm.com 'MicroIntMov', 6448139SMatt.Horsnell@arm.com {'code': 'IWRa = URb;', 6457646Sgene.wu@arm.com 'predicate_test': predicateTest}, 6467646Sgene.wu@arm.com ['IsMicroop']) 6477646Sgene.wu@arm.com 6488148SAli.Saidi@ARM.com microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet', 6498148SAli.Saidi@ARM.com 'MicroIntMov', 6508148SAli.Saidi@ARM.com {'code': microRetUopCode % 'URb', 6518148SAli.Saidi@ARM.com 'predicate_test': predicateTest}, 6528148SAli.Saidi@ARM.com ['IsMicroop', 'IsNonSpeculative', 6538148SAli.Saidi@ARM.com 'IsSerializeAfter']) 6548148SAli.Saidi@ARM.com 6558140SMatt.Horsnell@arm.com setPCCPSRDecl = ''' 6568140SMatt.Horsnell@arm.com CPSR cpsrOrCondCodes = URc; 6578140SMatt.Horsnell@arm.com SCTLR sctlr = Sctlr; 6588140SMatt.Horsnell@arm.com pNPC = URa; 6598303SAli.Saidi@ARM.com CPSR new_cpsr = 66010037SARM gem5 Developers cpsrWriteByInstr(cpsrOrCondCodes, URb, Scr, Nsacr, 66110037SARM gem5 Developers 0xF, true, sctlr.nmfi, xc->tcBase()); 6628303SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & new_cpsr; 6638303SAli.Saidi@ARM.com NextThumb = new_cpsr.t; 6648303SAli.Saidi@ARM.com NextJazelle = new_cpsr.j; 6658205SAli.Saidi@ARM.com NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) 6668140SMatt.Horsnell@arm.com | (((CPSR)URb).it1 & 0x3); 6678303SAli.Saidi@ARM.com CondCodesNZ = new_cpsr.nz; 6688303SAli.Saidi@ARM.com CondCodesC = new_cpsr.c; 6698303SAli.Saidi@ARM.com CondCodesV = new_cpsr.v; 6708303SAli.Saidi@ARM.com CondCodesGE = new_cpsr.ge; 6718140SMatt.Horsnell@arm.com ''' 6728140SMatt.Horsnell@arm.com 6738140SMatt.Horsnell@arm.com microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', 6748140SMatt.Horsnell@arm.com 'MicroSetPCCPSR', 6758140SMatt.Horsnell@arm.com {'code': setPCCPSRDecl, 6768140SMatt.Horsnell@arm.com 'predicate_test': predicateTest}, 6778140SMatt.Horsnell@arm.com ['IsMicroop']) 6788140SMatt.Horsnell@arm.com 6797639Sgblack@eecs.umich.edu header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \ 68010037SARM gem5 Developers MicroIntImmDeclare.subst(microAddXiUopIop) + \ 68110037SARM gem5 Developers MicroIntImmDeclare.subst(microAddXiSpAlignUopIop) + \ 6827639Sgblack@eecs.umich.edu MicroIntImmDeclare.subst(microSubiUopIop) + \ 68310037SARM gem5 Developers MicroIntImmDeclare.subst(microSubXiUopIop) + \ 6847646Sgene.wu@arm.com MicroIntRegDeclare.subst(microAddUopIop) + \ 6857646Sgene.wu@arm.com MicroIntRegDeclare.subst(microSubUopIop) + \ 68610037SARM gem5 Developers MicroIntXERegDeclare.subst(microAddXERegUopIop) + \ 6878140SMatt.Horsnell@arm.com MicroIntMovDeclare.subst(microUopRegMovIop) + \ 6888148SAli.Saidi@ARM.com MicroIntMovDeclare.subst(microUopRegMovRetIop) + \ 6898140SMatt.Horsnell@arm.com MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop) 6907646Sgene.wu@arm.com 6917639Sgblack@eecs.umich.edu decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \ 69210037SARM gem5 Developers MicroIntImmXConstructor.subst(microAddXiUopIop) + \ 69310037SARM gem5 Developers MicroIntImmXConstructor.subst(microAddXiSpAlignUopIop) + \ 6947639Sgblack@eecs.umich.edu MicroIntImmConstructor.subst(microSubiUopIop) + \ 69510037SARM gem5 Developers MicroIntImmXConstructor.subst(microSubXiUopIop) + \ 6967646Sgene.wu@arm.com MicroIntRegConstructor.subst(microAddUopIop) + \ 6977646Sgene.wu@arm.com MicroIntRegConstructor.subst(microSubUopIop) + \ 69810037SARM gem5 Developers MicroIntXERegConstructor.subst(microAddXERegUopIop) + \ 6998140SMatt.Horsnell@arm.com MicroIntMovConstructor.subst(microUopRegMovIop) + \ 7008148SAli.Saidi@ARM.com MicroIntMovConstructor.subst(microUopRegMovRetIop) + \ 7018140SMatt.Horsnell@arm.com MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop) 7027646Sgene.wu@arm.com 7036308SN/A exec_output = PredOpExecute.subst(microAddiUopIop) + \ 70410037SARM gem5 Developers BasicExecute.subst(microAddXiUopIop) + \ 70510037SARM gem5 Developers BasicExecute.subst(microAddXiSpAlignUopIop) + \ 7067639Sgblack@eecs.umich.edu PredOpExecute.subst(microSubiUopIop) + \ 70710037SARM gem5 Developers BasicExecute.subst(microSubXiUopIop) + \ 7087646Sgene.wu@arm.com PredOpExecute.subst(microAddUopIop) + \ 7097646Sgene.wu@arm.com PredOpExecute.subst(microSubUopIop) + \ 71010037SARM gem5 Developers BasicExecute.subst(microAddXERegUopIop) + \ 7118140SMatt.Horsnell@arm.com PredOpExecute.subst(microUopRegMovIop) + \ 7128148SAli.Saidi@ARM.com PredOpExecute.subst(microUopRegMovRetIop) + \ 7138140SMatt.Horsnell@arm.com PredOpExecute.subst(microUopSetPCCPSRIop) 7148140SMatt.Horsnell@arm.com 7156308SN/A}}; 7166019SN/A 7177134Sgblack@eecs.umich.edulet {{ 7187170Sgblack@eecs.umich.edu iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", []) 7197134Sgblack@eecs.umich.edu header_output = MacroMemDeclare.subst(iop) 7207134Sgblack@eecs.umich.edu decoder_output = MacroMemConstructor.subst(iop) 7217179Sgblack@eecs.umich.edu 72210037SARM gem5 Developers iop = InstObjParams("ldpstp", "LdpStp", 'PairMemOp', "", []) 72310037SARM gem5 Developers header_output += PairMemDeclare.subst(iop) 72410037SARM gem5 Developers decoder_output += PairMemConstructor.subst(iop) 72510037SARM gem5 Developers 72610037SARM gem5 Developers iopImm = InstObjParams("bigfpmemimm", "BigFpMemImm", "BigFpMemImmOp", "") 72710037SARM gem5 Developers iopPre = InstObjParams("bigfpmempre", "BigFpMemPre", "BigFpMemPreOp", "") 72810037SARM gem5 Developers iopPost = InstObjParams("bigfpmempost", "BigFpMemPost", "BigFpMemPostOp", "") 72910037SARM gem5 Developers for iop in (iopImm, iopPre, iopPost): 73010037SARM gem5 Developers header_output += BigFpMemImmDeclare.subst(iop) 73110037SARM gem5 Developers decoder_output += BigFpMemImmConstructor.subst(iop) 73210037SARM gem5 Developers 73310037SARM gem5 Developers iop = InstObjParams("bigfpmemreg", "BigFpMemReg", "BigFpMemRegOp", "") 73410037SARM gem5 Developers header_output += BigFpMemRegDeclare.subst(iop) 73510037SARM gem5 Developers decoder_output += BigFpMemRegConstructor.subst(iop) 73610037SARM gem5 Developers 73710037SARM gem5 Developers iop = InstObjParams("bigfpmemlit", "BigFpMemLit", "BigFpMemLitOp", "") 73810037SARM gem5 Developers header_output += BigFpMemLitDeclare.subst(iop) 73910037SARM gem5 Developers decoder_output += BigFpMemLitConstructor.subst(iop) 74010037SARM gem5 Developers 7417639Sgblack@eecs.umich.edu iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", []) 7427639Sgblack@eecs.umich.edu header_output += VMemMultDeclare.subst(iop) 7437639Sgblack@eecs.umich.edu decoder_output += VMemMultConstructor.subst(iop) 7447639Sgblack@eecs.umich.edu 7457639Sgblack@eecs.umich.edu iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", []) 7467639Sgblack@eecs.umich.edu header_output += VMemSingleDeclare.subst(iop) 7477639Sgblack@eecs.umich.edu decoder_output += VMemSingleConstructor.subst(iop) 7487639Sgblack@eecs.umich.edu 7497639Sgblack@eecs.umich.edu iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", []) 7507639Sgblack@eecs.umich.edu header_output += VMemMultDeclare.subst(iop) 7517639Sgblack@eecs.umich.edu decoder_output += VMemMultConstructor.subst(iop) 7527639Sgblack@eecs.umich.edu 7537639Sgblack@eecs.umich.edu iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", []) 7547639Sgblack@eecs.umich.edu header_output += VMemSingleDeclare.subst(iop) 7557639Sgblack@eecs.umich.edu decoder_output += VMemSingleConstructor.subst(iop) 7567639Sgblack@eecs.umich.edu 7577179Sgblack@eecs.umich.edu vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", []) 7587179Sgblack@eecs.umich.edu header_output += MacroVFPMemDeclare.subst(vfpIop) 7597179Sgblack@eecs.umich.edu decoder_output += MacroVFPMemConstructor.subst(vfpIop) 7606019SN/A}}; 761