m5ops.isa revision 9554:406fbcf60223
1//
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder.  You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gene Wu
38
39
40let {{
41    header_output = '''
42    uint64_t join32to64(uint32_t r1, uint32_t r0);
43    '''
44    decoder_output = '''
45    uint64_t join32to64(uint32_t r1, uint32_t r0)
46    {
47        uint64_t r = r1;
48        r <<= 32;
49        r |= r0;
50        return r;
51    }
52    '''
53    exec_output = '''
54    uint64_t join32to64(uint32_t r1, uint32_t r0);
55    '''
56
57
58    armCode = '''
59    PseudoInst::arm(xc->tcBase());
60    '''
61    armIop = InstObjParams("arm", "Arm", "PredOp",
62                           { "code": armCode,
63                             "predicate_test": predicateTest },
64                             ["IsNonSpeculative"])
65    header_output += BasicDeclare.subst(armIop)
66    decoder_output += BasicConstructor.subst(armIop)
67    exec_output += PredOpExecute.subst(armIop)
68
69    quiesceCode = '''
70    PseudoInst::quiesce(xc->tcBase());
71    '''
72    quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
73                           { "code": quiesceCode,
74                             "predicate_test": predicateTest },
75                             ["IsNonSpeculative", "IsQuiesce"])
76    header_output += BasicDeclare.subst(quiesceIop)
77    decoder_output += BasicConstructor.subst(quiesceIop)
78    exec_output += QuiescePredOpExecute.subst(quiesceIop)
79
80    quiesceNsCode = '''
81    PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
82    '''
83
84    quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
85                           { "code": quiesceNsCode,
86                             "predicate_test": predicateTest },
87                             ["IsNonSpeculative", "IsQuiesce"])
88    header_output += BasicDeclare.subst(quiesceNsIop)
89    decoder_output += BasicConstructor.subst(quiesceNsIop)
90    exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
91
92    quiesceCyclesCode = '''
93    PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
94    '''
95
96    quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
97                           { "code": quiesceCyclesCode,
98                             "predicate_test": predicateTest },
99                             ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
100    header_output += BasicDeclare.subst(quiesceCyclesIop)
101    decoder_output += BasicConstructor.subst(quiesceCyclesIop)
102    exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
103
104    quiesceTimeCode = '''
105    uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
106    R0 = bits(qt_val, 31, 0);
107    R1 = bits(qt_val, 63, 32);
108    '''
109
110    quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
111                           { "code": quiesceTimeCode,
112                             "predicate_test": predicateTest },
113                             ["IsNonSpeculative", "IsUnverifiable"])
114    header_output += BasicDeclare.subst(quiesceTimeIop)
115    decoder_output += BasicConstructor.subst(quiesceTimeIop)
116    exec_output += PredOpExecute.subst(quiesceTimeIop)
117
118    rpnsCode = '''
119    uint64_t rpns_val = PseudoInst::rpns(xc->tcBase());
120    R0 = bits(rpns_val, 31, 0);
121    R1 = bits(rpns_val, 63, 32);
122    '''
123
124    rpnsIop = InstObjParams("rpns", "Rpns", "PredOp",
125                           { "code": rpnsCode,
126                             "predicate_test": predicateTest },
127                             ["IsNonSpeculative", "IsUnverifiable"])
128    header_output += BasicDeclare.subst(rpnsIop)
129    decoder_output += BasicConstructor.subst(rpnsIop)
130    exec_output += PredOpExecute.subst(rpnsIop)
131
132    wakeCpuCode = '''
133    PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0));
134    '''
135
136    wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp",
137                   { "code": wakeCpuCode,
138                     "predicate_test": predicateTest },
139                     ["IsNonSpeculative", "IsUnverifiable"])
140    header_output += BasicDeclare.subst(wakeCPUIop)
141    decoder_output += BasicConstructor.subst(wakeCPUIop)
142    exec_output += PredOpExecute.subst(wakeCPUIop)
143
144    deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp",
145                           { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''',
146                             "predicate_test": predicateTest })
147    header_output += BasicDeclare.subst(deprecated_ivlbIop)
148    decoder_output += BasicConstructor.subst(deprecated_ivlbIop)
149    exec_output += PredOpExecute.subst(deprecated_ivlbIop)
150
151    deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp",
152                           { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''',
153                             "predicate_test": predicateTest })
154    header_output += BasicDeclare.subst(deprecated_ivleIop)
155    decoder_output += BasicConstructor.subst(deprecated_ivleIop)
156    exec_output += PredOpExecute.subst(deprecated_ivleIop)
157
158    deprecated_exit_code = '''
159        warn_once("Obsolete M5 exit instruction encountered.\\n");
160        PseudoInst::m5exit(xc->tcBase(), 0);
161    '''
162
163    deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp",
164                           { "code": deprecated_exit_code,
165                             "predicate_test": predicateTest },
166                             ["No_OpClass", "IsNonSpeculative"])
167    header_output += BasicDeclare.subst(deprecated_exitIop)
168    decoder_output += BasicConstructor.subst(deprecated_exitIop)
169    exec_output += PredOpExecute.subst(deprecated_exitIop)
170
171    m5exit_code = '''
172        PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0));
173    '''
174    m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp",
175                                   { "code": m5exit_code,
176                                     "predicate_test": predicateTest },
177                                     ["No_OpClass", "IsNonSpeculative"])
178    header_output += BasicDeclare.subst(m5exitIop)
179    decoder_output += BasicConstructor.subst(m5exitIop)
180    exec_output += PredOpExecute.subst(m5exitIop)
181
182    loadsymbolCode = '''
183    PseudoInst::loadsymbol(xc->tcBase());
184    '''
185
186    loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
187                           { "code": loadsymbolCode,
188                             "predicate_test": predicateTest },
189                             ["No_OpClass", "IsNonSpeculative"])
190    header_output += BasicDeclare.subst(loadsymbolIop)
191    decoder_output += BasicConstructor.subst(loadsymbolIop)
192    exec_output += PredOpExecute.subst(loadsymbolIop)
193
194    initparamCode = '''
195    uint64_t ip_val  = PseudoInst::initParam(xc->tcBase());
196    R0 = bits(ip_val, 31, 0);
197    R1 = bits(ip_val, 63, 32);
198    '''
199
200    initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
201                           { "code": initparamCode,
202                             "predicate_test": predicateTest },
203                             ["IsNonSpeculative"])
204    header_output += BasicDeclare.subst(initparamIop)
205    decoder_output += BasicConstructor.subst(initparamIop)
206    exec_output += PredOpExecute.subst(initparamIop)
207
208    resetstats_code = '''
209    PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
210    '''
211
212    resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp",
213                           { "code": resetstats_code,
214                             "predicate_test": predicateTest },
215                             ["IsNonSpeculative"])
216    header_output += BasicDeclare.subst(resetstatsIop)
217    decoder_output += BasicConstructor.subst(resetstatsIop)
218    exec_output += PredOpExecute.subst(resetstatsIop)
219
220    dumpstats_code = '''
221    PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
222    '''
223    dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp",
224                           { "code": dumpstats_code,
225                             "predicate_test": predicateTest },
226                             ["IsNonSpeculative"])
227    header_output += BasicDeclare.subst(dumpstatsIop)
228    decoder_output += BasicConstructor.subst(dumpstatsIop)
229    exec_output += PredOpExecute.subst(dumpstatsIop)
230
231    dumpresetstats_code = '''
232    PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
233    '''
234    dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp",
235                           { "code": dumpresetstats_code,
236                             "predicate_test": predicateTest },
237                             ["IsNonSpeculative"])
238    header_output += BasicDeclare.subst(dumpresetstatsIop)
239    decoder_output += BasicConstructor.subst(dumpresetstatsIop)
240    exec_output += PredOpExecute.subst(dumpresetstatsIop)
241
242    m5checkpoint_code = '''
243    PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2));
244    '''
245    m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
246                           { "code": m5checkpoint_code,
247                             "predicate_test": predicateTest },
248                             ["IsNonSpeculative", "IsUnverifiable"])
249    header_output += BasicDeclare.subst(m5checkpointIop)
250    decoder_output += BasicConstructor.subst(m5checkpointIop)
251    exec_output += PredOpExecute.subst(m5checkpointIop)
252
253    m5readfileCode = '''
254    int n = 4;
255    uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
256    R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
257    '''
258    m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
259                           { "code": m5readfileCode,
260                             "predicate_test": predicateTest },
261                             ["IsNonSpeculative", "IsUnverifiable"])
262    header_output += BasicDeclare.subst(m5readfileIop)
263    decoder_output += BasicConstructor.subst(m5readfileIop)
264    exec_output += PredOpExecute.subst(m5readfileIop)
265
266    m5writefileCode = '''
267    int n = 4;
268    uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
269    n = 6;
270    Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false);
271    R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset,
272                                filenameAddr);
273    '''
274    m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp",
275                           { "code": m5writefileCode,
276                             "predicate_test": predicateTest },
277                             ["IsNonSpeculative"])
278    header_output += BasicDeclare.subst(m5writefileIop)
279    decoder_output += BasicConstructor.subst(m5writefileIop)
280    exec_output += PredOpExecute.subst(m5writefileIop)
281
282    m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
283                           { "code": "PseudoInst::debugbreak(xc->tcBase());",
284                             "predicate_test": predicateTest },
285                             ["IsNonSpeculative"])
286    header_output += BasicDeclare.subst(m5breakIop)
287    decoder_output += BasicConstructor.subst(m5breakIop)
288    exec_output += PredOpExecute.subst(m5breakIop)
289
290    m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp",
291                           { "code": "PseudoInst::switchcpu(xc->tcBase());",
292                             "predicate_test": predicateTest },
293                             ["IsNonSpeculative"])
294    header_output += BasicDeclare.subst(m5switchcpuIop)
295    decoder_output += BasicConstructor.subst(m5switchcpuIop)
296    exec_output += PredOpExecute.subst(m5switchcpuIop)
297
298    m5addsymbolCode = '''
299    PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
300    '''
301    m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
302                           { "code": m5addsymbolCode,
303                             "predicate_test": predicateTest },
304                             ["IsNonSpeculative"])
305    header_output += BasicDeclare.subst(m5addsymbolIop)
306    decoder_output += BasicConstructor.subst(m5addsymbolIop)
307    exec_output += PredOpExecute.subst(m5addsymbolIop)
308
309    m5panicCode = '''panic("M5 panic instruction called at pc=%#x.",
310                     xc->pcState().pc());'''
311    m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp",
312                     { "code": m5panicCode,
313                       "predicate_test": predicateTest },
314                       ["IsNonSpeculative"])
315    header_output += BasicDeclare.subst(m5panicIop)
316    decoder_output += BasicConstructor.subst(m5panicIop)
317    exec_output += PredOpExecute.subst(m5panicIop)
318
319    m5workbeginCode = '''PseudoInst::workbegin(
320                          xc->tcBase(),
321                          join32to64(R1, R0),
322                          join32to64(R3, R2)
323                      );'''
324    m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp",
325                     { "code": m5workbeginCode,
326                       "predicate_test": predicateTest },
327                       ["IsNonSpeculative"])
328    header_output += BasicDeclare.subst(m5workbeginIop)
329    decoder_output += BasicConstructor.subst(m5workbeginIop)
330    exec_output += PredOpExecute.subst(m5workbeginIop)
331
332    m5workendCode = '''PseudoInst::workend(
333                        xc->tcBase(),
334                        join32to64(R1, R0),
335                        join32to64(R3, R2)
336                    );'''
337    m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp",
338                     { "code": m5workendCode,
339                       "predicate_test": predicateTest },
340                       ["IsNonSpeculative"])
341    header_output += BasicDeclare.subst(m5workendIop)
342    decoder_output += BasicConstructor.subst(m5workendIop)
343    exec_output += PredOpExecute.subst(m5workendIop)
344
345}};
346