m5ops.isa revision 8607:5fb918115c07
1// 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// 14// Redistribution and use in source and binary forms, with or without 15// modification, are permitted provided that the following conditions are 16// met: redistributions of source code must retain the above copyright 17// notice, this list of conditions and the following disclaimer; 18// redistributions in binary form must reproduce the above copyright 19// notice, this list of conditions and the following disclaimer in the 20// documentation and/or other materials provided with the distribution; 21// neither the name of the copyright holders nor the names of its 22// contributors may be used to endorse or promote products derived from 23// this software without specific prior written permission. 24// 25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36// 37// Authors: Gene Wu 38 39 40let {{ 41 header_output = "" 42 decoder_output = ''' 43 uint64_t join32to64(uint32_t r1, uint32_t r0) 44 { 45 uint64_t r = r1; 46 r <<= 32; 47 r |= r0; 48 return r; 49 } 50 ''' 51 exec_output = ''' 52 uint64_t join32to64(uint32_t r1, uint32_t r0); 53 ''' 54 55 56 armCode = ''' 57 PseudoInst::arm(xc->tcBase()); 58 ''' 59 armIop = InstObjParams("arm", "Arm", "PredOp", 60 { "code": armCode, 61 "predicate_test": predicateTest }, 62 ["IsNonSpeculative"]) 63 header_output += BasicDeclare.subst(armIop) 64 decoder_output += BasicConstructor.subst(armIop) 65 exec_output += PredOpExecute.subst(armIop) 66 67 quiesceCode = ''' 68 PseudoInst::quiesce(xc->tcBase()); 69 ''' 70 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 71 { "code": quiesceCode, 72 "predicate_test": predicateTest }, 73 ["IsNonSpeculative", "IsQuiesce"]) 74 header_output += BasicDeclare.subst(quiesceIop) 75 decoder_output += BasicConstructor.subst(quiesceIop) 76 exec_output += QuiescePredOpExecute.subst(quiesceIop) 77 78 quiesceNsCode = ''' 79 PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); 80 ''' 81 82 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 83 { "code": quiesceNsCode, 84 "predicate_test": predicateTest }, 85 ["IsNonSpeculative", "IsQuiesce"]) 86 header_output += BasicDeclare.subst(quiesceNsIop) 87 decoder_output += BasicConstructor.subst(quiesceNsIop) 88 exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 89 90 quiesceCyclesCode = ''' 91 PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); 92 ''' 93 94 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 95 { "code": quiesceCyclesCode, 96 "predicate_test": predicateTest }, 97 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 98 header_output += BasicDeclare.subst(quiesceCyclesIop) 99 decoder_output += BasicConstructor.subst(quiesceCyclesIop) 100 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 101 102 quiesceTimeCode = ''' 103 uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); 104 R0 = bits(qt_val, 31, 0); 105 R1 = bits(qt_val, 63, 32); 106 ''' 107 108 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 109 { "code": quiesceTimeCode, 110 "predicate_test": predicateTest }, 111 ["IsNonSpeculative", "IsUnverifiable"]) 112 header_output += BasicDeclare.subst(quiesceTimeIop) 113 decoder_output += BasicConstructor.subst(quiesceTimeIop) 114 exec_output += PredOpExecute.subst(quiesceTimeIop) 115 116 rpnsCode = ''' 117 uint64_t rpns_val = PseudoInst::rpns(xc->tcBase()); 118 R0 = bits(rpns_val, 31, 0); 119 R1 = bits(rpns_val, 63, 32); 120 ''' 121 122 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 123 { "code": rpnsCode, 124 "predicate_test": predicateTest }, 125 ["IsNonSpeculative", "IsUnverifiable"]) 126 header_output += BasicDeclare.subst(rpnsIop) 127 decoder_output += BasicConstructor.subst(rpnsIop) 128 exec_output += PredOpExecute.subst(rpnsIop) 129 130 wakeCpuCode = ''' 131 PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0)); 132 ''' 133 134 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 135 { "code": wakeCpuCode, 136 "predicate_test": predicateTest }, 137 ["IsNonSpeculative", "IsUnverifiable"]) 138 header_output += BasicDeclare.subst(wakeCPUIop) 139 decoder_output += BasicConstructor.subst(wakeCPUIop) 140 exec_output += PredOpExecute.subst(wakeCPUIop) 141 142 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 143 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 144 "predicate_test": predicateTest }) 145 header_output += BasicDeclare.subst(deprecated_ivlbIop) 146 decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 147 exec_output += PredOpExecute.subst(deprecated_ivlbIop) 148 149 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 150 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 151 "predicate_test": predicateTest }) 152 header_output += BasicDeclare.subst(deprecated_ivleIop) 153 decoder_output += BasicConstructor.subst(deprecated_ivleIop) 154 exec_output += PredOpExecute.subst(deprecated_ivleIop) 155 156 deprecated_exit_code = ''' 157 warn_once("Obsolete M5 exit instruction encountered.\\n"); 158 PseudoInst::m5exit(xc->tcBase(), 0); 159 ''' 160 161 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 162 { "code": deprecated_exit_code, 163 "predicate_test": predicateTest }, 164 ["No_OpClass", "IsNonSpeculative"]) 165 header_output += BasicDeclare.subst(deprecated_exitIop) 166 decoder_output += BasicConstructor.subst(deprecated_exitIop) 167 exec_output += PredOpExecute.subst(deprecated_exitIop) 168 169 m5exit_code = ''' 170 PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0)); 171 ''' 172 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 173 { "code": m5exit_code, 174 "predicate_test": predicateTest }, 175 ["No_OpClass", "IsNonSpeculative"]) 176 header_output += BasicDeclare.subst(m5exitIop) 177 decoder_output += BasicConstructor.subst(m5exitIop) 178 exec_output += PredOpExecute.subst(m5exitIop) 179 180 loadsymbolCode = ''' 181 PseudoInst::loadsymbol(xc->tcBase()); 182 ''' 183 184 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 185 { "code": loadsymbolCode, 186 "predicate_test": predicateTest }, 187 ["No_OpClass", "IsNonSpeculative"]) 188 header_output += BasicDeclare.subst(loadsymbolIop) 189 decoder_output += BasicConstructor.subst(loadsymbolIop) 190 exec_output += PredOpExecute.subst(loadsymbolIop) 191 192 initparamCode = ''' 193#if FULL_SYSTEM 194 Rt = PseudoInst::initParam(xc->tcBase()); 195#else 196 PseudoInst::panicFsOnlyPseudoInst("initparam"); 197 Rt = 0; 198#endif 199 ''' 200 201 initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 202 { "code": initparamCode, 203 "predicate_test": predicateTest }) 204 header_output += BasicDeclare.subst(initparamIop) 205 decoder_output += BasicConstructor.subst(initparamIop) 206 exec_output += PredOpExecute.subst(initparamIop) 207 208 resetstats_code = ''' 209 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 210 ''' 211 212 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 213 { "code": resetstats_code, 214 "predicate_test": predicateTest }, 215 ["IsNonSpeculative"]) 216 header_output += BasicDeclare.subst(resetstatsIop) 217 decoder_output += BasicConstructor.subst(resetstatsIop) 218 exec_output += PredOpExecute.subst(resetstatsIop) 219 220 dumpstats_code = ''' 221 PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 222 ''' 223 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 224 { "code": dumpstats_code, 225 "predicate_test": predicateTest }, 226 ["IsNonSpeculative"]) 227 header_output += BasicDeclare.subst(dumpstatsIop) 228 decoder_output += BasicConstructor.subst(dumpstatsIop) 229 exec_output += PredOpExecute.subst(dumpstatsIop) 230 231 dumpresetstats_code = ''' 232 PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 233 ''' 234 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 235 { "code": dumpresetstats_code, 236 "predicate_test": predicateTest }, 237 ["IsNonSpeculative"]) 238 header_output += BasicDeclare.subst(dumpresetstatsIop) 239 decoder_output += BasicConstructor.subst(dumpresetstatsIop) 240 exec_output += PredOpExecute.subst(dumpresetstatsIop) 241 242 m5checkpoint_code = ''' 243 PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 244 ''' 245 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 246 { "code": m5checkpoint_code, 247 "predicate_test": predicateTest }, 248 ["IsNonSpeculative"]) 249 header_output += BasicDeclare.subst(m5checkpointIop) 250 decoder_output += BasicConstructor.subst(m5checkpointIop) 251 exec_output += PredOpExecute.subst(m5checkpointIop) 252 253 m5readfileCode = ''' 254 int n = 4; 255 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 256 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); 257 ''' 258 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 259 { "code": m5readfileCode, 260 "predicate_test": predicateTest }, 261 ["IsNonSpeculative"]) 262 header_output += BasicDeclare.subst(m5readfileIop) 263 decoder_output += BasicConstructor.subst(m5readfileIop) 264 exec_output += PredOpExecute.subst(m5readfileIop) 265 266 m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 267 { "code": "PseudoInst::debugbreak(xc->tcBase());", 268 "predicate_test": predicateTest }, 269 ["IsNonSpeculative"]) 270 header_output += BasicDeclare.subst(m5breakIop) 271 decoder_output += BasicConstructor.subst(m5breakIop) 272 exec_output += PredOpExecute.subst(m5breakIop) 273 274 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 275 { "code": "PseudoInst::switchcpu(xc->tcBase());", 276 "predicate_test": predicateTest }, 277 ["IsNonSpeculative"]) 278 header_output += BasicDeclare.subst(m5switchcpuIop) 279 decoder_output += BasicConstructor.subst(m5switchcpuIop) 280 exec_output += PredOpExecute.subst(m5switchcpuIop) 281 282 m5addsymbolCode = ''' 283 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); 284 ''' 285 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 286 { "code": m5addsymbolCode, 287 "predicate_test": predicateTest }, 288 ["IsNonSpeculative"]) 289 header_output += BasicDeclare.subst(m5addsymbolIop) 290 decoder_output += BasicConstructor.subst(m5addsymbolIop) 291 exec_output += PredOpExecute.subst(m5addsymbolIop) 292 293 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 294 xc->pcState().pc());''' 295 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 296 { "code": m5panicCode, 297 "predicate_test": predicateTest }, 298 ["IsNonSpeculative"]) 299 header_output += BasicDeclare.subst(m5panicIop) 300 decoder_output += BasicConstructor.subst(m5panicIop) 301 exec_output += PredOpExecute.subst(m5panicIop) 302 303 m5workbeginCode = '''PseudoInst::workbegin( 304 xc->tcBase(), 305 join32to64(R1, R0), 306 join32to64(R3, R2) 307 );''' 308 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", 309 { "code": m5workbeginCode, 310 "predicate_test": predicateTest }, 311 ["IsNonSpeculative"]) 312 header_output += BasicDeclare.subst(m5workbeginIop) 313 decoder_output += BasicConstructor.subst(m5workbeginIop) 314 exec_output += PredOpExecute.subst(m5workbeginIop) 315 316 m5workendCode = '''PseudoInst::workend( 317 xc->tcBase(), 318 join32to64(R1, R0), 319 join32to64(R3, R2) 320 );''' 321 m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", 322 { "code": m5workendCode, 323 "predicate_test": predicateTest }, 324 ["IsNonSpeculative"]) 325 header_output += BasicDeclare.subst(m5workendIop) 326 decoder_output += BasicConstructor.subst(m5workendIop) 327 exec_output += PredOpExecute.subst(m5workendIop) 328 329}}; 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