m5ops.isa revision 8734
17732SAli.Saidi@ARM.com// 27732SAli.Saidi@ARM.com// Copyright (c) 2010 ARM Limited 37732SAli.Saidi@ARM.com// All rights reserved 47732SAli.Saidi@ARM.com// 57732SAli.Saidi@ARM.com// The license below extends only to copyright in the software and shall 67732SAli.Saidi@ARM.com// not be construed as granting a license to any other intellectual 77732SAli.Saidi@ARM.com// property including but not limited to intellectual property relating 87732SAli.Saidi@ARM.com// to a hardware implementation of the functionality of the software 97732SAli.Saidi@ARM.com// licensed hereunder. You may use the software subject to the license 107732SAli.Saidi@ARM.com// terms below provided that you ensure that this notice is replicated 117732SAli.Saidi@ARM.com// unmodified and in its entirety in all distributions of the software, 127732SAli.Saidi@ARM.com// modified or unmodified, in source code or in binary form. 137732SAli.Saidi@ARM.com// 147732SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without 157732SAli.Saidi@ARM.com// modification, are permitted provided that the following conditions are 167732SAli.Saidi@ARM.com// met: redistributions of source code must retain the above copyright 177732SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer; 187732SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 197732SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 207732SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution; 217732SAli.Saidi@ARM.com// neither the name of the copyright holders nor the names of its 227732SAli.Saidi@ARM.com// contributors may be used to endorse or promote products derived from 237732SAli.Saidi@ARM.com// this software without specific prior written permission. 247732SAli.Saidi@ARM.com// 257732SAli.Saidi@ARM.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267732SAli.Saidi@ARM.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277732SAli.Saidi@ARM.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287732SAli.Saidi@ARM.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297732SAli.Saidi@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307732SAli.Saidi@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317732SAli.Saidi@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327732SAli.Saidi@ARM.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337732SAli.Saidi@ARM.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347732SAli.Saidi@ARM.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357732SAli.Saidi@ARM.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367732SAli.Saidi@ARM.com// 377732SAli.Saidi@ARM.com// Authors: Gene Wu 387732SAli.Saidi@ARM.com 397732SAli.Saidi@ARM.com 407732SAli.Saidi@ARM.comlet {{ 417732SAli.Saidi@ARM.com header_output = "" 428204SAli.Saidi@ARM.com decoder_output = ''' 438204SAli.Saidi@ARM.com uint64_t join32to64(uint32_t r1, uint32_t r0) 448204SAli.Saidi@ARM.com { 458204SAli.Saidi@ARM.com uint64_t r = r1; 468204SAli.Saidi@ARM.com r <<= 32; 478204SAli.Saidi@ARM.com r |= r0; 488204SAli.Saidi@ARM.com return r; 498204SAli.Saidi@ARM.com } 508204SAli.Saidi@ARM.com ''' 518204SAli.Saidi@ARM.com exec_output = ''' 528204SAli.Saidi@ARM.com uint64_t join32to64(uint32_t r1, uint32_t r0); 538204SAli.Saidi@ARM.com ''' 548204SAli.Saidi@ARM.com 557732SAli.Saidi@ARM.com 567732SAli.Saidi@ARM.com armCode = ''' 577732SAli.Saidi@ARM.com PseudoInst::arm(xc->tcBase()); 587732SAli.Saidi@ARM.com ''' 597732SAli.Saidi@ARM.com armIop = InstObjParams("arm", "Arm", "PredOp", 607732SAli.Saidi@ARM.com { "code": armCode, 617732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 627732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 637732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(armIop) 647732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(armIop) 657732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(armIop) 667732SAli.Saidi@ARM.com 677732SAli.Saidi@ARM.com quiesceCode = ''' 688204SAli.Saidi@ARM.com PseudoInst::quiesce(xc->tcBase()); 697732SAli.Saidi@ARM.com ''' 707732SAli.Saidi@ARM.com quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 717732SAli.Saidi@ARM.com { "code": quiesceCode, 727732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 737732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce"]) 747732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceIop) 757732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceIop) 768142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceIop) 777732SAli.Saidi@ARM.com 787732SAli.Saidi@ARM.com quiesceNsCode = ''' 798204SAli.Saidi@ARM.com PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); 807732SAli.Saidi@ARM.com ''' 817732SAli.Saidi@ARM.com 827732SAli.Saidi@ARM.com quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 837732SAli.Saidi@ARM.com { "code": quiesceNsCode, 847732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 857732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce"]) 867732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceNsIop) 877732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceNsIop) 888142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 897732SAli.Saidi@ARM.com 907732SAli.Saidi@ARM.com quiesceCyclesCode = ''' 918204SAli.Saidi@ARM.com PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); 927732SAli.Saidi@ARM.com ''' 937732SAli.Saidi@ARM.com 947732SAli.Saidi@ARM.com quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 957732SAli.Saidi@ARM.com { "code": quiesceCyclesCode, 967732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 977732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 987732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceCyclesIop) 997732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceCyclesIop) 1008142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 1017732SAli.Saidi@ARM.com 1027732SAli.Saidi@ARM.com quiesceTimeCode = ''' 1038204SAli.Saidi@ARM.com uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); 1048204SAli.Saidi@ARM.com R0 = bits(qt_val, 31, 0); 1058204SAli.Saidi@ARM.com R1 = bits(qt_val, 63, 32); 1067732SAli.Saidi@ARM.com ''' 1077732SAli.Saidi@ARM.com 1087732SAli.Saidi@ARM.com quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 1097732SAli.Saidi@ARM.com { "code": quiesceTimeCode, 1107732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1117732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1127732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceTimeIop) 1137732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceTimeIop) 1147732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(quiesceTimeIop) 1157732SAli.Saidi@ARM.com 1168204SAli.Saidi@ARM.com rpnsCode = ''' 1178204SAli.Saidi@ARM.com uint64_t rpns_val = PseudoInst::rpns(xc->tcBase()); 1188204SAli.Saidi@ARM.com R0 = bits(rpns_val, 31, 0); 1198204SAli.Saidi@ARM.com R1 = bits(rpns_val, 63, 32); 1208204SAli.Saidi@ARM.com ''' 1218204SAli.Saidi@ARM.com 1227732SAli.Saidi@ARM.com rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 1238204SAli.Saidi@ARM.com { "code": rpnsCode, 1247732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1257732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1267732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(rpnsIop) 1277732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(rpnsIop) 1287732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(rpnsIop) 1297732SAli.Saidi@ARM.com 1308204SAli.Saidi@ARM.com wakeCpuCode = ''' 1318204SAli.Saidi@ARM.com PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0)); 1328204SAli.Saidi@ARM.com ''' 1338204SAli.Saidi@ARM.com 1347732SAli.Saidi@ARM.com wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 1358204SAli.Saidi@ARM.com { "code": wakeCpuCode, 1368204SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1378204SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1387732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(wakeCPUIop) 1397732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(wakeCPUIop) 1407732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(wakeCPUIop) 1417732SAli.Saidi@ARM.com 1427732SAli.Saidi@ARM.com deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 1437732SAli.Saidi@ARM.com { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 1447732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1457732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_ivlbIop) 1467732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 1477732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_ivlbIop) 1487732SAli.Saidi@ARM.com 1497732SAli.Saidi@ARM.com deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 1507732SAli.Saidi@ARM.com { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 1517732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1527732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_ivleIop) 1537732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_ivleIop) 1547732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_ivleIop) 1557732SAli.Saidi@ARM.com 1567732SAli.Saidi@ARM.com deprecated_exit_code = ''' 1577732SAli.Saidi@ARM.com warn_once("Obsolete M5 exit instruction encountered.\\n"); 1587732SAli.Saidi@ARM.com PseudoInst::m5exit(xc->tcBase(), 0); 1597732SAli.Saidi@ARM.com ''' 1607732SAli.Saidi@ARM.com 1617732SAli.Saidi@ARM.com deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 1627732SAli.Saidi@ARM.com { "code": deprecated_exit_code, 1637732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1647732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1657732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_exitIop) 1667732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_exitIop) 1677732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_exitIop) 1687732SAli.Saidi@ARM.com 1698204SAli.Saidi@ARM.com m5exit_code = ''' 1708204SAli.Saidi@ARM.com PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0)); 1718204SAli.Saidi@ARM.com ''' 1727732SAli.Saidi@ARM.com m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 1738204SAli.Saidi@ARM.com { "code": m5exit_code, 1748204SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1758204SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1767732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5exitIop) 1777732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5exitIop) 1787732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5exitIop) 1797732SAli.Saidi@ARM.com 1807732SAli.Saidi@ARM.com loadsymbolCode = ''' 1817732SAli.Saidi@ARM.com PseudoInst::loadsymbol(xc->tcBase()); 1827732SAli.Saidi@ARM.com ''' 1837732SAli.Saidi@ARM.com 1847732SAli.Saidi@ARM.com loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 1857732SAli.Saidi@ARM.com { "code": loadsymbolCode, 1867732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1877732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1887732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(loadsymbolIop) 1897732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(loadsymbolIop) 1907732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(loadsymbolIop) 1917732SAli.Saidi@ARM.com 1927732SAli.Saidi@ARM.com initparamCode = ''' 1937732SAli.Saidi@ARM.com#if FULL_SYSTEM 1948659SAli.Saidi@ARM.com uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); 1958659SAli.Saidi@ARM.com R0 = bits(ip_val, 31, 0); 1968659SAli.Saidi@ARM.com R1 = bits(ip_val, 63, 32); 1978607Sgblack@eecs.umich.edu#else 1988607Sgblack@eecs.umich.edu PseudoInst::panicFsOnlyPseudoInst("initparam"); 1997732SAli.Saidi@ARM.com#endif 2007732SAli.Saidi@ARM.com ''' 2017732SAli.Saidi@ARM.com 2027732SAli.Saidi@ARM.com initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 2037732SAli.Saidi@ARM.com { "code": initparamCode, 2048659SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2058659SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2067732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(initparamIop) 2077732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(initparamIop) 2087732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(initparamIop) 2097732SAli.Saidi@ARM.com 2108204SAli.Saidi@ARM.com resetstats_code = ''' 2118204SAli.Saidi@ARM.com PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2128204SAli.Saidi@ARM.com ''' 2138204SAli.Saidi@ARM.com 2147732SAli.Saidi@ARM.com resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 2158204SAli.Saidi@ARM.com { "code": resetstats_code, 2167732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2177732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2187732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(resetstatsIop) 2197732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(resetstatsIop) 2207732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(resetstatsIop) 2217732SAli.Saidi@ARM.com 2228204SAli.Saidi@ARM.com dumpstats_code = ''' 2238204SAli.Saidi@ARM.com PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2248204SAli.Saidi@ARM.com ''' 2257732SAli.Saidi@ARM.com dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 2268204SAli.Saidi@ARM.com { "code": dumpstats_code, 2277732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2287732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2297732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(dumpstatsIop) 2307732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dumpstatsIop) 2317732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(dumpstatsIop) 2327732SAli.Saidi@ARM.com 2338204SAli.Saidi@ARM.com dumpresetstats_code = ''' 2348204SAli.Saidi@ARM.com PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2358204SAli.Saidi@ARM.com ''' 2367732SAli.Saidi@ARM.com dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 2378204SAli.Saidi@ARM.com { "code": dumpresetstats_code, 2387732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2397732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2407732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(dumpresetstatsIop) 2417732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dumpresetstatsIop) 2427732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(dumpresetstatsIop) 2437732SAli.Saidi@ARM.com 2448204SAli.Saidi@ARM.com m5checkpoint_code = ''' 2458204SAli.Saidi@ARM.com PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2468204SAli.Saidi@ARM.com ''' 2477732SAli.Saidi@ARM.com m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 2488204SAli.Saidi@ARM.com { "code": m5checkpoint_code, 2497732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2508733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsUnverifiable"]) 2517732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5checkpointIop) 2527732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5checkpointIop) 2537732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5checkpointIop) 2547732SAli.Saidi@ARM.com 2557732SAli.Saidi@ARM.com m5readfileCode = ''' 2568204SAli.Saidi@ARM.com int n = 4; 2578204SAli.Saidi@ARM.com uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 2588204SAli.Saidi@ARM.com R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); 2597732SAli.Saidi@ARM.com ''' 2607732SAli.Saidi@ARM.com m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 2617732SAli.Saidi@ARM.com { "code": m5readfileCode, 2627732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2638733Sgeoffrey.blake@arm.com ["IsNonSpeculative", "IsUnverifiable"]) 2647732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5readfileIop) 2657732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5readfileIop) 2667732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5readfileIop) 2677732SAli.Saidi@ARM.com 2688734Sdam.sunwoo@arm.com m5writefileCode = ''' 2698734Sdam.sunwoo@arm.com#if FULL_SYSTEM 2708734Sdam.sunwoo@arm.com int n = 4; 2718734Sdam.sunwoo@arm.com uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 2728734Sdam.sunwoo@arm.com n = 6; 2738734Sdam.sunwoo@arm.com Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false); 2748734Sdam.sunwoo@arm.com R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset, 2758734Sdam.sunwoo@arm.com filenameAddr); 2768734Sdam.sunwoo@arm.com#endif 2778734Sdam.sunwoo@arm.com ''' 2788734Sdam.sunwoo@arm.com m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp", 2798734Sdam.sunwoo@arm.com { "code": m5writefileCode, 2808734Sdam.sunwoo@arm.com "predicate_test": predicateTest }, 2818734Sdam.sunwoo@arm.com ["IsNonSpeculative"]) 2828734Sdam.sunwoo@arm.com header_output += BasicDeclare.subst(m5writefileIop) 2838734Sdam.sunwoo@arm.com decoder_output += BasicConstructor.subst(m5writefileIop) 2848734Sdam.sunwoo@arm.com exec_output += PredOpExecute.subst(m5writefileIop) 2858734Sdam.sunwoo@arm.com 2867732SAli.Saidi@ARM.com m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 2877732SAli.Saidi@ARM.com { "code": "PseudoInst::debugbreak(xc->tcBase());", 2887732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2897732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2907732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5breakIop) 2917732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5breakIop) 2927732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5breakIop) 2937732SAli.Saidi@ARM.com 2947732SAli.Saidi@ARM.com m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 2957732SAli.Saidi@ARM.com { "code": "PseudoInst::switchcpu(xc->tcBase());", 2967732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2977732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2987732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5switchcpuIop) 2997732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5switchcpuIop) 3007732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5switchcpuIop) 3017732SAli.Saidi@ARM.com 3027732SAli.Saidi@ARM.com m5addsymbolCode = ''' 3038204SAli.Saidi@ARM.com PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); 3047732SAli.Saidi@ARM.com ''' 3057732SAli.Saidi@ARM.com m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 3067732SAli.Saidi@ARM.com { "code": m5addsymbolCode, 3077732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 3087732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 3097732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5addsymbolIop) 3107732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5addsymbolIop) 3117732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5addsymbolIop) 3127732SAli.Saidi@ARM.com 3137732SAli.Saidi@ARM.com m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 3147732SAli.Saidi@ARM.com xc->pcState().pc());''' 3157732SAli.Saidi@ARM.com m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 3167732SAli.Saidi@ARM.com { "code": m5panicCode, 3177732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 3187732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 3197732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5panicIop) 3207732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5panicIop) 3217732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5panicIop) 3227732SAli.Saidi@ARM.com 3238354Sgedare@gwmail.gwu.edu m5workbeginCode = '''PseudoInst::workbegin( 3248354Sgedare@gwmail.gwu.edu xc->tcBase(), 3258354Sgedare@gwmail.gwu.edu join32to64(R1, R0), 3268354Sgedare@gwmail.gwu.edu join32to64(R3, R2) 3278354Sgedare@gwmail.gwu.edu );''' 3288354Sgedare@gwmail.gwu.edu m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", 3298354Sgedare@gwmail.gwu.edu { "code": m5workbeginCode, 3308354Sgedare@gwmail.gwu.edu "predicate_test": predicateTest }, 3318354Sgedare@gwmail.gwu.edu ["IsNonSpeculative"]) 3328354Sgedare@gwmail.gwu.edu header_output += BasicDeclare.subst(m5workbeginIop) 3338354Sgedare@gwmail.gwu.edu decoder_output += BasicConstructor.subst(m5workbeginIop) 3348354Sgedare@gwmail.gwu.edu exec_output += PredOpExecute.subst(m5workbeginIop) 3358354Sgedare@gwmail.gwu.edu 3368354Sgedare@gwmail.gwu.edu m5workendCode = '''PseudoInst::workend( 3378354Sgedare@gwmail.gwu.edu xc->tcBase(), 3388354Sgedare@gwmail.gwu.edu join32to64(R1, R0), 3398354Sgedare@gwmail.gwu.edu join32to64(R3, R2) 3408354Sgedare@gwmail.gwu.edu );''' 3418354Sgedare@gwmail.gwu.edu m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", 3428354Sgedare@gwmail.gwu.edu { "code": m5workendCode, 3438354Sgedare@gwmail.gwu.edu "predicate_test": predicateTest }, 3448354Sgedare@gwmail.gwu.edu ["IsNonSpeculative"]) 3458354Sgedare@gwmail.gwu.edu header_output += BasicDeclare.subst(m5workendIop) 3468354Sgedare@gwmail.gwu.edu decoder_output += BasicConstructor.subst(m5workendIop) 3478354Sgedare@gwmail.gwu.edu exec_output += PredOpExecute.subst(m5workendIop) 3488354Sgedare@gwmail.gwu.edu 3497732SAli.Saidi@ARM.com}}; 350