m5ops.isa revision 8354
17732SAli.Saidi@ARM.com// 27732SAli.Saidi@ARM.com// Copyright (c) 2010 ARM Limited 37732SAli.Saidi@ARM.com// All rights reserved 47732SAli.Saidi@ARM.com// 57732SAli.Saidi@ARM.com// The license below extends only to copyright in the software and shall 67732SAli.Saidi@ARM.com// not be construed as granting a license to any other intellectual 77732SAli.Saidi@ARM.com// property including but not limited to intellectual property relating 87732SAli.Saidi@ARM.com// to a hardware implementation of the functionality of the software 97732SAli.Saidi@ARM.com// licensed hereunder. You may use the software subject to the license 107732SAli.Saidi@ARM.com// terms below provided that you ensure that this notice is replicated 117732SAli.Saidi@ARM.com// unmodified and in its entirety in all distributions of the software, 127732SAli.Saidi@ARM.com// modified or unmodified, in source code or in binary form. 137732SAli.Saidi@ARM.com// 147732SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without 157732SAli.Saidi@ARM.com// modification, are permitted provided that the following conditions are 167732SAli.Saidi@ARM.com// met: redistributions of source code must retain the above copyright 177732SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer; 187732SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 197732SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 207732SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution; 217732SAli.Saidi@ARM.com// neither the name of the copyright holders nor the names of its 227732SAli.Saidi@ARM.com// contributors may be used to endorse or promote products derived from 237732SAli.Saidi@ARM.com// this software without specific prior written permission. 247732SAli.Saidi@ARM.com// 257732SAli.Saidi@ARM.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267732SAli.Saidi@ARM.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277732SAli.Saidi@ARM.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287732SAli.Saidi@ARM.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297732SAli.Saidi@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307732SAli.Saidi@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317732SAli.Saidi@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327732SAli.Saidi@ARM.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337732SAli.Saidi@ARM.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347732SAli.Saidi@ARM.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357732SAli.Saidi@ARM.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367732SAli.Saidi@ARM.com// 377732SAli.Saidi@ARM.com// Authors: Gene Wu 387732SAli.Saidi@ARM.com 397732SAli.Saidi@ARM.com 407732SAli.Saidi@ARM.comlet {{ 417732SAli.Saidi@ARM.com header_output = "" 428204SAli.Saidi@ARM.com decoder_output = ''' 438204SAli.Saidi@ARM.com uint64_t join32to64(uint32_t r1, uint32_t r0) 448204SAli.Saidi@ARM.com { 458204SAli.Saidi@ARM.com uint64_t r = r1; 468204SAli.Saidi@ARM.com r <<= 32; 478204SAli.Saidi@ARM.com r |= r0; 488204SAli.Saidi@ARM.com return r; 498204SAli.Saidi@ARM.com } 508204SAli.Saidi@ARM.com ''' 518204SAli.Saidi@ARM.com exec_output = ''' 528204SAli.Saidi@ARM.com uint64_t join32to64(uint32_t r1, uint32_t r0); 538204SAli.Saidi@ARM.com ''' 548204SAli.Saidi@ARM.com 557732SAli.Saidi@ARM.com 567732SAli.Saidi@ARM.com armCode = ''' 577732SAli.Saidi@ARM.com#if FULL_SYSTEM 587732SAli.Saidi@ARM.com PseudoInst::arm(xc->tcBase()); 597732SAli.Saidi@ARM.com#endif 607732SAli.Saidi@ARM.com ''' 617732SAli.Saidi@ARM.com armIop = InstObjParams("arm", "Arm", "PredOp", 627732SAli.Saidi@ARM.com { "code": armCode, 637732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 647732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 657732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(armIop) 667732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(armIop) 677732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(armIop) 687732SAli.Saidi@ARM.com 697732SAli.Saidi@ARM.com quiesceCode = ''' 707732SAli.Saidi@ARM.com#if FULL_SYSTEM 718204SAli.Saidi@ARM.com PseudoInst::quiesce(xc->tcBase()); 727732SAli.Saidi@ARM.com#endif 737732SAli.Saidi@ARM.com ''' 747732SAli.Saidi@ARM.com quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 757732SAli.Saidi@ARM.com { "code": quiesceCode, 767732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 777732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce"]) 787732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceIop) 797732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceIop) 808142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceIop) 817732SAli.Saidi@ARM.com 827732SAli.Saidi@ARM.com quiesceNsCode = ''' 837732SAli.Saidi@ARM.com#if FULL_SYSTEM 848204SAli.Saidi@ARM.com PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); 857732SAli.Saidi@ARM.com#endif 867732SAli.Saidi@ARM.com ''' 877732SAli.Saidi@ARM.com 887732SAli.Saidi@ARM.com quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 897732SAli.Saidi@ARM.com { "code": quiesceNsCode, 907732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 917732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce"]) 927732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceNsIop) 937732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceNsIop) 948142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 957732SAli.Saidi@ARM.com 967732SAli.Saidi@ARM.com quiesceCyclesCode = ''' 977732SAli.Saidi@ARM.com#if FULL_SYSTEM 988204SAli.Saidi@ARM.com PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); 997732SAli.Saidi@ARM.com#endif 1007732SAli.Saidi@ARM.com ''' 1017732SAli.Saidi@ARM.com 1027732SAli.Saidi@ARM.com quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 1037732SAli.Saidi@ARM.com { "code": quiesceCyclesCode, 1047732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1057732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 1067732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceCyclesIop) 1077732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceCyclesIop) 1088142SAli.Saidi@ARM.com exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 1097732SAli.Saidi@ARM.com 1107732SAli.Saidi@ARM.com quiesceTimeCode = ''' 1117732SAli.Saidi@ARM.com#if FULL_SYSTEM 1128204SAli.Saidi@ARM.com uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); 1138204SAli.Saidi@ARM.com R0 = bits(qt_val, 31, 0); 1148204SAli.Saidi@ARM.com R1 = bits(qt_val, 63, 32); 1157732SAli.Saidi@ARM.com#endif 1167732SAli.Saidi@ARM.com ''' 1177732SAli.Saidi@ARM.com 1187732SAli.Saidi@ARM.com quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 1197732SAli.Saidi@ARM.com { "code": quiesceTimeCode, 1207732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1217732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1227732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(quiesceTimeIop) 1237732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(quiesceTimeIop) 1247732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(quiesceTimeIop) 1257732SAli.Saidi@ARM.com 1268204SAli.Saidi@ARM.com rpnsCode = ''' 1278204SAli.Saidi@ARM.com uint64_t rpns_val = PseudoInst::rpns(xc->tcBase()); 1288204SAli.Saidi@ARM.com R0 = bits(rpns_val, 31, 0); 1298204SAli.Saidi@ARM.com R1 = bits(rpns_val, 63, 32); 1308204SAli.Saidi@ARM.com ''' 1318204SAli.Saidi@ARM.com 1327732SAli.Saidi@ARM.com rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 1338204SAli.Saidi@ARM.com { "code": rpnsCode, 1347732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1357732SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1367732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(rpnsIop) 1377732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(rpnsIop) 1387732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(rpnsIop) 1397732SAli.Saidi@ARM.com 1408204SAli.Saidi@ARM.com wakeCpuCode = ''' 1418204SAli.Saidi@ARM.com PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0)); 1428204SAli.Saidi@ARM.com ''' 1438204SAli.Saidi@ARM.com 1447732SAli.Saidi@ARM.com wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 1458204SAli.Saidi@ARM.com { "code": wakeCpuCode, 1468204SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1478204SAli.Saidi@ARM.com ["IsNonSpeculative", "IsUnverifiable"]) 1487732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(wakeCPUIop) 1497732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(wakeCPUIop) 1507732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(wakeCPUIop) 1517732SAli.Saidi@ARM.com 1527732SAli.Saidi@ARM.com deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 1537732SAli.Saidi@ARM.com { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 1547732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1557732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_ivlbIop) 1567732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 1577732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_ivlbIop) 1587732SAli.Saidi@ARM.com 1597732SAli.Saidi@ARM.com deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 1607732SAli.Saidi@ARM.com { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 1617732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 1627732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_ivleIop) 1637732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_ivleIop) 1647732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_ivleIop) 1657732SAli.Saidi@ARM.com 1667732SAli.Saidi@ARM.com deprecated_exit_code = ''' 1677732SAli.Saidi@ARM.com warn_once("Obsolete M5 exit instruction encountered.\\n"); 1687732SAli.Saidi@ARM.com PseudoInst::m5exit(xc->tcBase(), 0); 1697732SAli.Saidi@ARM.com ''' 1707732SAli.Saidi@ARM.com 1717732SAli.Saidi@ARM.com deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 1727732SAli.Saidi@ARM.com { "code": deprecated_exit_code, 1737732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1747732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1757732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(deprecated_exitIop) 1767732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(deprecated_exitIop) 1777732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(deprecated_exitIop) 1787732SAli.Saidi@ARM.com 1798204SAli.Saidi@ARM.com m5exit_code = ''' 1808204SAli.Saidi@ARM.com PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0)); 1818204SAli.Saidi@ARM.com ''' 1827732SAli.Saidi@ARM.com m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 1838204SAli.Saidi@ARM.com { "code": m5exit_code, 1848204SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1858204SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 1867732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5exitIop) 1877732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5exitIop) 1887732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5exitIop) 1897732SAli.Saidi@ARM.com 1907732SAli.Saidi@ARM.com loadsymbolCode = ''' 1917732SAli.Saidi@ARM.com#if FULL_SYSTEM 1927732SAli.Saidi@ARM.com PseudoInst::loadsymbol(xc->tcBase()); 1937732SAli.Saidi@ARM.com#endif 1947732SAli.Saidi@ARM.com ''' 1957732SAli.Saidi@ARM.com 1967732SAli.Saidi@ARM.com loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 1977732SAli.Saidi@ARM.com { "code": loadsymbolCode, 1987732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 1997732SAli.Saidi@ARM.com ["No_OpClass", "IsNonSpeculative"]) 2007732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(loadsymbolIop) 2017732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(loadsymbolIop) 2027732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(loadsymbolIop) 2037732SAli.Saidi@ARM.com 2047732SAli.Saidi@ARM.com initparamCode = ''' 2057732SAli.Saidi@ARM.com#if FULL_SYSTEM 2067732SAli.Saidi@ARM.com Rt = xc->tcBase()->getCpuPtr()->system->init_param; 2077732SAli.Saidi@ARM.com#endif 2087732SAli.Saidi@ARM.com ''' 2097732SAli.Saidi@ARM.com 2107732SAli.Saidi@ARM.com initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 2117732SAli.Saidi@ARM.com { "code": initparamCode, 2127732SAli.Saidi@ARM.com "predicate_test": predicateTest }) 2137732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(initparamIop) 2147732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(initparamIop) 2157732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(initparamIop) 2167732SAli.Saidi@ARM.com 2178204SAli.Saidi@ARM.com resetstats_code = ''' 2188204SAli.Saidi@ARM.com PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2198204SAli.Saidi@ARM.com ''' 2208204SAli.Saidi@ARM.com 2217732SAli.Saidi@ARM.com resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 2228204SAli.Saidi@ARM.com { "code": resetstats_code, 2237732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2247732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2257732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(resetstatsIop) 2267732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(resetstatsIop) 2277732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(resetstatsIop) 2287732SAli.Saidi@ARM.com 2298204SAli.Saidi@ARM.com dumpstats_code = ''' 2308204SAli.Saidi@ARM.com PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2318204SAli.Saidi@ARM.com ''' 2327732SAli.Saidi@ARM.com dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 2338204SAli.Saidi@ARM.com { "code": dumpstats_code, 2347732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2357732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2367732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(dumpstatsIop) 2377732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dumpstatsIop) 2387732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(dumpstatsIop) 2397732SAli.Saidi@ARM.com 2408204SAli.Saidi@ARM.com dumpresetstats_code = ''' 2418204SAli.Saidi@ARM.com PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2428204SAli.Saidi@ARM.com ''' 2437732SAli.Saidi@ARM.com dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 2448204SAli.Saidi@ARM.com { "code": dumpresetstats_code, 2457732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2467732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2477732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(dumpresetstatsIop) 2487732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(dumpresetstatsIop) 2497732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(dumpresetstatsIop) 2507732SAli.Saidi@ARM.com 2518204SAli.Saidi@ARM.com m5checkpoint_code = ''' 2528204SAli.Saidi@ARM.com PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 2538204SAli.Saidi@ARM.com ''' 2547732SAli.Saidi@ARM.com m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 2558204SAli.Saidi@ARM.com { "code": m5checkpoint_code, 2567732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2577732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2587732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5checkpointIop) 2597732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5checkpointIop) 2607732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5checkpointIop) 2617732SAli.Saidi@ARM.com 2627732SAli.Saidi@ARM.com m5readfileCode = ''' 2637732SAli.Saidi@ARM.com#if FULL_SYSTEM 2648204SAli.Saidi@ARM.com int n = 4; 2658204SAli.Saidi@ARM.com uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 2668204SAli.Saidi@ARM.com R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); 2677732SAli.Saidi@ARM.com#endif 2687732SAli.Saidi@ARM.com ''' 2697732SAli.Saidi@ARM.com m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 2707732SAli.Saidi@ARM.com { "code": m5readfileCode, 2717732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2727732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2737732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5readfileIop) 2747732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5readfileIop) 2757732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5readfileIop) 2767732SAli.Saidi@ARM.com 2777732SAli.Saidi@ARM.com m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 2787732SAli.Saidi@ARM.com { "code": "PseudoInst::debugbreak(xc->tcBase());", 2797732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2807732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2817732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5breakIop) 2827732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5breakIop) 2837732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5breakIop) 2847732SAli.Saidi@ARM.com 2857732SAli.Saidi@ARM.com m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 2867732SAli.Saidi@ARM.com { "code": "PseudoInst::switchcpu(xc->tcBase());", 2877732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 2887732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 2897732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5switchcpuIop) 2907732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5switchcpuIop) 2917732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5switchcpuIop) 2927732SAli.Saidi@ARM.com 2937732SAli.Saidi@ARM.com m5addsymbolCode = ''' 2947732SAli.Saidi@ARM.com#if FULL_SYSTEM 2958204SAli.Saidi@ARM.com PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); 2967732SAli.Saidi@ARM.com#endif 2977732SAli.Saidi@ARM.com ''' 2987732SAli.Saidi@ARM.com m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 2997732SAli.Saidi@ARM.com { "code": m5addsymbolCode, 3007732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 3017732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 3027732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5addsymbolIop) 3037732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5addsymbolIop) 3047732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5addsymbolIop) 3057732SAli.Saidi@ARM.com 3067732SAli.Saidi@ARM.com m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 3077732SAli.Saidi@ARM.com xc->pcState().pc());''' 3087732SAli.Saidi@ARM.com m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 3097732SAli.Saidi@ARM.com { "code": m5panicCode, 3107732SAli.Saidi@ARM.com "predicate_test": predicateTest }, 3117732SAli.Saidi@ARM.com ["IsNonSpeculative"]) 3127732SAli.Saidi@ARM.com header_output += BasicDeclare.subst(m5panicIop) 3137732SAli.Saidi@ARM.com decoder_output += BasicConstructor.subst(m5panicIop) 3147732SAli.Saidi@ARM.com exec_output += PredOpExecute.subst(m5panicIop) 3157732SAli.Saidi@ARM.com 3168354Sgedare@gwmail.gwu.edu m5workbeginCode = '''PseudoInst::workbegin( 3178354Sgedare@gwmail.gwu.edu xc->tcBase(), 3188354Sgedare@gwmail.gwu.edu join32to64(R1, R0), 3198354Sgedare@gwmail.gwu.edu join32to64(R3, R2) 3208354Sgedare@gwmail.gwu.edu );''' 3218354Sgedare@gwmail.gwu.edu m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", 3228354Sgedare@gwmail.gwu.edu { "code": m5workbeginCode, 3238354Sgedare@gwmail.gwu.edu "predicate_test": predicateTest }, 3248354Sgedare@gwmail.gwu.edu ["IsNonSpeculative"]) 3258354Sgedare@gwmail.gwu.edu header_output += BasicDeclare.subst(m5workbeginIop) 3268354Sgedare@gwmail.gwu.edu decoder_output += BasicConstructor.subst(m5workbeginIop) 3278354Sgedare@gwmail.gwu.edu exec_output += PredOpExecute.subst(m5workbeginIop) 3288354Sgedare@gwmail.gwu.edu 3298354Sgedare@gwmail.gwu.edu m5workendCode = '''PseudoInst::workend( 3308354Sgedare@gwmail.gwu.edu xc->tcBase(), 3318354Sgedare@gwmail.gwu.edu join32to64(R1, R0), 3328354Sgedare@gwmail.gwu.edu join32to64(R3, R2) 3338354Sgedare@gwmail.gwu.edu );''' 3348354Sgedare@gwmail.gwu.edu m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", 3358354Sgedare@gwmail.gwu.edu { "code": m5workendCode, 3368354Sgedare@gwmail.gwu.edu "predicate_test": predicateTest }, 3378354Sgedare@gwmail.gwu.edu ["IsNonSpeculative"]) 3388354Sgedare@gwmail.gwu.edu header_output += BasicDeclare.subst(m5workendIop) 3398354Sgedare@gwmail.gwu.edu decoder_output += BasicConstructor.subst(m5workendIop) 3408354Sgedare@gwmail.gwu.edu exec_output += PredOpExecute.subst(m5workendIop) 3418354Sgedare@gwmail.gwu.edu 3427732SAli.Saidi@ARM.com}}; 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