ldr.isa revision 7400:f6c9b27c4dbe
11060SN/A// -*- mode:c++ -*- 214025Sgiacomo.gabrielli@arm.com 39920Syasuko.eckert@amd.com// Copyright (c) 2010 ARM Limited 47944SGiacomo.Gabrielli@arm.com// All rights reserved 57944SGiacomo.Gabrielli@arm.com// 67944SGiacomo.Gabrielli@arm.com// The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com// not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com// property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com// to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com// licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com// terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com// unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com// modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com// 152702Sktlim@umich.edu// Redistribution and use in source and binary forms, with or without 166973Stjones1@inf.ed.ac.uk// modification, are permitted provided that the following conditions are 171060SN/A// met: redistributions of source code must retain the above copyright 181060SN/A// notice, this list of conditions and the following disclaimer; 191060SN/A// redistributions in binary form must reproduce the above copyright 201060SN/A// notice, this list of conditions and the following disclaimer in the 211060SN/A// documentation and/or other materials provided with the distribution; 221060SN/A// neither the name of the copyright holders nor the names of its 231060SN/A// contributors may be used to endorse or promote products derived from 241060SN/A// this software without specific prior written permission. 251060SN/A// 261060SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 271060SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 281060SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 291060SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 301060SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 311060SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 321060SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 331060SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 341060SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 351060SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 361060SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 371060SN/A// 381060SN/A// Authors: Gabe Black 391060SN/A 401060SN/Alet {{ 412665Ssaidi@eecs.umich.edu 422665Ssaidi@eecs.umich.edu header_output = "" 436973Stjones1@inf.ed.ac.uk decoder_output = "" 441060SN/A exec_output = "" 451060SN/A 461464SN/A def loadImmClassName(post, add, writeback, \ 471464SN/A size=4, sign=False, user=False): 481060SN/A return memClassName("LOAD_IMM", post, add, writeback, 4910835Sandreas.hansson@arm.com size, sign, user) 502731Sktlim@umich.edu 5112109SRekai.GonzalezAlberquilla@arm.com def loadRegClassName(post, add, writeback, \ 522292SN/A size=4, sign=False, user=False): 531464SN/A return memClassName("LOAD_REG", post, add, writeback, 541060SN/A size, sign, user) 5510687SAndreas.Sandberg@ARM.com 567720Sgblack@eecs.umich.edu def loadDoubleImmClassName(post, add, writeback): 571060SN/A return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 586658Snate@binkert.org 598887Sgeoffrey.blake@arm.com def loadDoubleRegClassName(post, add, writeback): 6010319SAndreas.Sandberg@ARM.com return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 611464SN/A 6212107SRekai.GonzalezAlberquilla@arm.com def emitLoad(name, Name, imm, eaCode, accCode, \ 631464SN/A memFlags, instFlags, base, double=False): 642669Sktlim@umich.edu global header_output, decoder_output, exec_output 651060SN/A 666973Stjones1@inf.ed.ac.uk (newHeader, 672669Sktlim@umich.edu newDecoder, 6811608Snikos.nikoleris@arm.com newExec) = loadStoreBase(name, Name, imm, 697678Sgblack@eecs.umich.edu eaCode, accCode, "", 702292SN/A memFlags, instFlags, double, False, 711060SN/A base, execTemplateBase = 'Load') 721060SN/A 731060SN/A header_output += newHeader 741060SN/A decoder_output += newDecoder 751060SN/A exec_output += newExec 761060SN/A 771060SN/A def buildImmLoad(mnem, post, add, writeback, \ 7810319SAndreas.Sandberg@ARM.com size=4, sign=False, user=False, \ 791060SN/A prefetch=False, ldrex=False, vldr=False): 801060SN/A name = mnem 811060SN/A Name = loadImmClassName(post, add, writeback, \ 822733Sktlim@umich.edu size, sign, user) 832733Sktlim@umich.edu 8412109SRekai.GonzalezAlberquilla@arm.com if add: 851060SN/A op = " +" 8613590Srekai.gonzalezalberquilla@arm.com else: 8713590Srekai.gonzalezalberquilla@arm.com op = " -" 8813590Srekai.gonzalezalberquilla@arm.com 8913590Srekai.gonzalezalberquilla@arm.com offset = op + " imm" 902292SN/A eaCode = "EA = Base" 912292SN/A if not post: 928486Sgblack@eecs.umich.edu eaCode += offset 932292SN/A eaCode += ";" 942292SN/A 952292SN/A memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 962292SN/A if prefetch: 971060SN/A Name = "%s_%s" % (mnem.upper(), Name) 985543Ssaidi@eecs.umich.edu memFlags.append("Request::PREFETCH") 998902Sandreas.hansson@arm.com accCode = ''' 1001060SN/A uint64_t temp = Mem%s;\n 1011060SN/A temp = temp; 1029046SAli.Saidi@ARM.com ''' % buildMemSuffix(sign, size) 1039046SAli.Saidi@ARM.com elif vldr: 1049046SAli.Saidi@ARM.com Name = "%s_%s" % (mnem.upper(), Name) 1059046SAli.Saidi@ARM.com accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" % \ 1069046SAli.Saidi@ARM.com buildMemSuffix(sign, size) 1079046SAli.Saidi@ARM.com else: 1089046SAli.Saidi@ARM.com if ldrex: 1099046SAli.Saidi@ARM.com memFlags.append("Request::LLSC") 1109046SAli.Saidi@ARM.com Name = "%s_%s" % (mnem.upper(), Name) 1119046SAli.Saidi@ARM.com accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \ 1129046SAli.Saidi@ARM.com buildMemSuffix(sign, size) 1139046SAli.Saidi@ARM.com 1149046SAli.Saidi@ARM.com if not prefetch and not ldrex and not vldr: 1159046SAli.Saidi@ARM.com memFlags.append("ArmISA::TLB::AllowUnaligned") 1169046SAli.Saidi@ARM.com 1179046SAli.Saidi@ARM.com if writeback: 1189046SAli.Saidi@ARM.com accCode += "Base = Base %s;\n" % offset 11914025Sgiacomo.gabrielli@arm.com base = buildMemBase("MemoryImm", post, writeback) 12014025Sgiacomo.gabrielli@arm.com 12114025Sgiacomo.gabrielli@arm.com emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 1229046SAli.Saidi@ARM.com 1239046SAli.Saidi@ARM.com def buildRfeLoad(mnem, post, add, writeback): 1249046SAli.Saidi@ARM.com name = mnem 1259046SAli.Saidi@ARM.com Name = "RFE_" + loadImmClassName(post, add, writeback, 8) 1269046SAli.Saidi@ARM.com 1279046SAli.Saidi@ARM.com offset = 0 1289046SAli.Saidi@ARM.com if post != add: 1299046SAli.Saidi@ARM.com offset += 4 1309046SAli.Saidi@ARM.com if not add: 1319046SAli.Saidi@ARM.com offset -= 8 1329046SAli.Saidi@ARM.com 13312421Sgabeblack@google.com eaCode = "EA = Base + %d;" % offset 1349046SAli.Saidi@ARM.com 1359046SAli.Saidi@ARM.com wbDiff = -8 1369046SAli.Saidi@ARM.com if add: 1379046SAli.Saidi@ARM.com wbDiff = 8 1389046SAli.Saidi@ARM.com accCode = ''' 1399046SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 1409046SAli.Saidi@ARM.com SCTLR sctlr = Sctlr; 14113953Sgiacomo.gabrielli@arm.com NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); 1429046SAli.Saidi@ARM.com uint32_t newCpsr = 14310824SAndreas.Sandberg@ARM.com cpsrWriteByInstr(cpsr | CondCodes, 1449046SAli.Saidi@ARM.com cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 1459046SAli.Saidi@ARM.com 0xF, true, sctlr.nmfi); 1469046SAli.Saidi@ARM.com Cpsr = ~CondCodesMask & newCpsr; 1479046SAli.Saidi@ARM.com CondCodes = CondCodesMask & newCpsr; 1489046SAli.Saidi@ARM.com ''' 1499046SAli.Saidi@ARM.com if writeback: 1509046SAli.Saidi@ARM.com accCode += "Base = Base + %s;\n" % wbDiff 1519046SAli.Saidi@ARM.com 1529046SAli.Saidi@ARM.com global header_output, decoder_output, exec_output 1532292SN/A 15410417Sandreas.hansson@arm.com (newHeader, 1559046SAli.Saidi@ARM.com newDecoder, 1569046SAli.Saidi@ARM.com newExec) = RfeBase(name, Name, eaCode, accCode, 1579046SAli.Saidi@ARM.com ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], []) 1589046SAli.Saidi@ARM.com 15910030SAli.Saidi@ARM.com header_output += newHeader 16010030SAli.Saidi@ARM.com decoder_output += newDecoder 1619046SAli.Saidi@ARM.com exec_output += newExec 1629046SAli.Saidi@ARM.com 1639046SAli.Saidi@ARM.com def buildRegLoad(mnem, post, add, writeback, size=4, sign=False, \ 1649046SAli.Saidi@ARM.com user=False, prefetch=False): 1659046SAli.Saidi@ARM.com name = mnem 1669046SAli.Saidi@ARM.com Name = loadRegClassName(post, add, writeback, 1679046SAli.Saidi@ARM.com size, sign, user) 1689046SAli.Saidi@ARM.com 1699046SAli.Saidi@ARM.com if add: 1709046SAli.Saidi@ARM.com op = " +" 1719046SAli.Saidi@ARM.com else: 1729046SAli.Saidi@ARM.com op = " -" 1739046SAli.Saidi@ARM.com 17412107SRekai.GonzalezAlberquilla@arm.com offset = op + " shift_rm_imm(Index, shiftAmt," + \ 1759046SAli.Saidi@ARM.com " shiftType, CondCodes<29:>)" 1769046SAli.Saidi@ARM.com eaCode = "EA = Base" 1779046SAli.Saidi@ARM.com if not post: 1789046SAli.Saidi@ARM.com eaCode += offset 17914025Sgiacomo.gabrielli@arm.com eaCode += ";" 1809046SAli.Saidi@ARM.com 1819046SAli.Saidi@ARM.com memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"] 1829046SAli.Saidi@ARM.com if prefetch: 1839046SAli.Saidi@ARM.com Name = "%s_%s" % (mnem.upper(), Name) 1849046SAli.Saidi@ARM.com memFlags.append("Request::PREFETCH") 1859046SAli.Saidi@ARM.com accCode = ''' 18614025Sgiacomo.gabrielli@arm.com uint64_t temp = Mem%s;\n 1879046SAli.Saidi@ARM.com temp = temp; 1889046SAli.Saidi@ARM.com ''' % buildMemSuffix(sign, size) 1899046SAli.Saidi@ARM.com else: 1909046SAli.Saidi@ARM.com accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \ 1919046SAli.Saidi@ARM.com buildMemSuffix(sign, size) 1929046SAli.Saidi@ARM.com if writeback: 1939046SAli.Saidi@ARM.com accCode += "Base = Base %s;\n" % offset 1949046SAli.Saidi@ARM.com 1959046SAli.Saidi@ARM.com if not prefetch: 1969046SAli.Saidi@ARM.com memFlags.append("ArmISA::TLB::AllowUnaligned") 1979046SAli.Saidi@ARM.com 1989046SAli.Saidi@ARM.com base = buildMemBase("MemoryReg", post, writeback) 1999046SAli.Saidi@ARM.com 2009046SAli.Saidi@ARM.com emitLoad(name, Name, False, eaCode, accCode, \ 2019046SAli.Saidi@ARM.com memFlags, [], base) 2029046SAli.Saidi@ARM.com 2039046SAli.Saidi@ARM.com def buildDoubleImmLoad(mnem, post, add, writeback, \ 20410417Sandreas.hansson@arm.com ldrex=False, vldr=False): 2051060SN/A name = mnem 2069046SAli.Saidi@ARM.com Name = loadDoubleImmClassName(post, add, writeback) 2079046SAli.Saidi@ARM.com 2089046SAli.Saidi@ARM.com if add: 2099046SAli.Saidi@ARM.com op = " +" 2109046SAli.Saidi@ARM.com else: 2119046SAli.Saidi@ARM.com op = " -" 2129046SAli.Saidi@ARM.com 2139046SAli.Saidi@ARM.com offset = op + " imm" 2149046SAli.Saidi@ARM.com eaCode = "EA = Base" 21513590Srekai.gonzalezalberquilla@arm.com if not post: 2169046SAli.Saidi@ARM.com eaCode += offset 2179046SAli.Saidi@ARM.com eaCode += ";" 2189046SAli.Saidi@ARM.com 2199046SAli.Saidi@ARM.com if not vldr: 2209046SAli.Saidi@ARM.com accCode = ''' 2219046SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 2229046SAli.Saidi@ARM.com Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 2239046SAli.Saidi@ARM.com Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 22414112Sgabor.dozsa@arm.com ''' 2259046SAli.Saidi@ARM.com else: 2269046SAli.Saidi@ARM.com accCode = ''' 2279046SAli.Saidi@ARM.com uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 2289046SAli.Saidi@ARM.com FpDest.uw = (uint32_t)swappedMem; 2299046SAli.Saidi@ARM.com FpDest2.uw = (uint32_t)(swappedMem >> 32); 2309046SAli.Saidi@ARM.com ''' 23113590Srekai.gonzalezalberquilla@arm.com if ldrex: 2329046SAli.Saidi@ARM.com memFlags = ["Request::LLSC"] 2339046SAli.Saidi@ARM.com else: 2349046SAli.Saidi@ARM.com memFlags = [] 23513590Srekai.gonzalezalberquilla@arm.com if ldrex or vldr: 2369046SAli.Saidi@ARM.com Name = "%s_%s" % (mnem.upper(), Name) 2379046SAli.Saidi@ARM.com if writeback: 2389046SAli.Saidi@ARM.com accCode += "Base = Base %s;\n" % offset 2399046SAli.Saidi@ARM.com base = buildMemBase("MemoryDImm", post, writeback) 24013590Srekai.gonzalezalberquilla@arm.com 2419046SAli.Saidi@ARM.com memFlags.extend(["ArmISA::TLB::MustBeOne", 2429046SAli.Saidi@ARM.com "ArmISA::TLB::AlignWord"]) 24313590Srekai.gonzalezalberquilla@arm.com 2449046SAli.Saidi@ARM.com emitLoad(name, Name, True, eaCode, accCode, \ 2459046SAli.Saidi@ARM.com memFlags, [], base, double=True) 2469046SAli.Saidi@ARM.com 2479046SAli.Saidi@ARM.com def buildDoubleRegLoad(mnem, post, add, writeback): 2489046SAli.Saidi@ARM.com name = mnem 2499046SAli.Saidi@ARM.com Name = loadDoubleRegClassName(post, add, writeback) 2509046SAli.Saidi@ARM.com 2519046SAli.Saidi@ARM.com if add: 2529046SAli.Saidi@ARM.com op = " +" 25312104Snathanael.premillieu@arm.com else: 2549046SAli.Saidi@ARM.com op = " -" 2559046SAli.Saidi@ARM.com 2569046SAli.Saidi@ARM.com offset = op + " shift_rm_imm(Index, shiftAmt," + \ 2579046SAli.Saidi@ARM.com " shiftType, CondCodes<29:>)" 25812105Snathanael.premillieu@arm.com eaCode = "EA = Base" 2599046SAli.Saidi@ARM.com if not post: 2609046SAli.Saidi@ARM.com eaCode += offset 2619046SAli.Saidi@ARM.com eaCode += ";" 2629046SAli.Saidi@ARM.com 26312105Snathanael.premillieu@arm.com accCode = ''' 2649046SAli.Saidi@ARM.com CPSR cpsr = Cpsr; 2659046SAli.Saidi@ARM.com Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 2669046SAli.Saidi@ARM.com Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 2679046SAli.Saidi@ARM.com ''' 26812105Snathanael.premillieu@arm.com if writeback: 2699046SAli.Saidi@ARM.com accCode += "Base = Base %s;\n" % offset 2709046SAli.Saidi@ARM.com base = buildMemBase("MemoryDReg", post, writeback) 2719046SAli.Saidi@ARM.com 2729046SAli.Saidi@ARM.com emitLoad(name, Name, False, eaCode, accCode, 2739046SAli.Saidi@ARM.com ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"], 2749046SAli.Saidi@ARM.com [], base, double=True) 2759046SAli.Saidi@ARM.com 2769046SAli.Saidi@ARM.com def buildLoads(mnem, size=4, sign=False, user=False): 27713590Srekai.gonzalezalberquilla@arm.com buildImmLoad(mnem, True, True, True, size, sign, user) 2789046SAli.Saidi@ARM.com buildRegLoad(mnem, True, True, True, size, sign, user) 2799046SAli.Saidi@ARM.com buildImmLoad(mnem, True, False, True, size, sign, user) 2809046SAli.Saidi@ARM.com buildRegLoad(mnem, True, False, True, size, sign, user) 2819046SAli.Saidi@ARM.com buildImmLoad(mnem, False, True, True, size, sign, user) 2829046SAli.Saidi@ARM.com buildRegLoad(mnem, False, True, True, size, sign, user) 28312421Sgabeblack@google.com buildImmLoad(mnem, False, False, True, size, sign, user) 28412421Sgabeblack@google.com buildRegLoad(mnem, False, False, True, size, sign, user) 28512421Sgabeblack@google.com buildImmLoad(mnem, False, True, False, size, sign, user) 2869046SAli.Saidi@ARM.com buildRegLoad(mnem, False, True, False, size, sign, user) 2871060SN/A buildImmLoad(mnem, False, False, False, size, sign, user) 2881060SN/A buildRegLoad(mnem, False, False, False, size, sign, user) 2891060SN/A 2901060SN/A def buildDoubleLoads(mnem): 2911060SN/A buildDoubleImmLoad(mnem, True, True, True) 2921060SN/A buildDoubleRegLoad(mnem, True, True, True) 2935358Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, True, False, True) 2945358Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, True, False, True) 2955358Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, True, True) 2965358Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, True, True) 2975358Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, True) 2985358Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, False, True) 2995358Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, True, False) 3005358Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, True, False) 3015358Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, False) 3025358Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, False, False) 3035358Sgblack@eecs.umich.edu 3045358Sgblack@eecs.umich.edu def buildRfeLoads(mnem): 3055358Sgblack@eecs.umich.edu buildRfeLoad(mnem, True, True, True) 30613954Sgiacomo.gabrielli@arm.com buildRfeLoad(mnem, True, True, False) 30713954Sgiacomo.gabrielli@arm.com buildRfeLoad(mnem, True, False, True) 3087520Sgblack@eecs.umich.edu buildRfeLoad(mnem, True, False, False) 30911608Snikos.nikoleris@arm.com buildRfeLoad(mnem, False, True, True) 31013954Sgiacomo.gabrielli@arm.com buildRfeLoad(mnem, False, True, False) 31113954Sgiacomo.gabrielli@arm.com buildRfeLoad(mnem, False, False, True) 3127520Sgblack@eecs.umich.edu buildRfeLoad(mnem, False, False, False) 31313652Sqtt2@cornell.edu 31414297Sjordi.vaquero@metempsy.com def buildPrefetches(mnem): 31513652Sqtt2@cornell.edu buildRegLoad(mnem, False, False, False, size=1, prefetch=True) 3167944SGiacomo.Gabrielli@arm.com buildImmLoad(mnem, False, False, False, size=1, prefetch=True) 3179046SAli.Saidi@ARM.com buildRegLoad(mnem, False, True, False, size=1, prefetch=True) 3189046SAli.Saidi@ARM.com buildImmLoad(mnem, False, True, False, size=1, prefetch=True) 3197944SGiacomo.Gabrielli@arm.com 3207944SGiacomo.Gabrielli@arm.com buildLoads("ldr") 3219046SAli.Saidi@ARM.com buildLoads("ldrt", user=True) 3229046SAli.Saidi@ARM.com buildLoads("ldrb", size=1) 3237944SGiacomo.Gabrielli@arm.com buildLoads("ldrbt", size=1, user=True) 3248545Ssaidi@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 3258545Ssaidi@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 3268545Ssaidi@eecs.umich.edu buildLoads("ldrh", size=2) 3278545Ssaidi@eecs.umich.edu buildLoads("ldrht", size=2, user=True) 3288545Ssaidi@eecs.umich.edu buildLoads("hdrsh", size=2, sign=True) 3299046SAli.Saidi@ARM.com buildLoads("ldrsht", size=2, sign=True, user=True) 3309046SAli.Saidi@ARM.com 3318545Ssaidi@eecs.umich.edu buildDoubleLoads("ldrd") 3328545Ssaidi@eecs.umich.edu 3338545Ssaidi@eecs.umich.edu buildRfeLoads("rfe") 3348545Ssaidi@eecs.umich.edu 3358545Ssaidi@eecs.umich.edu buildPrefetches("pld") 3369046SAli.Saidi@ARM.com buildPrefetches("pldw") 3379046SAli.Saidi@ARM.com buildPrefetches("pli") 3388545Ssaidi@eecs.umich.edu 3397944SGiacomo.Gabrielli@arm.com buildImmLoad("ldrex", False, True, False, size=4, ldrex=True) 3407944SGiacomo.Gabrielli@arm.com buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True) 3417944SGiacomo.Gabrielli@arm.com buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True) 3427944SGiacomo.Gabrielli@arm.com buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True) 3437944SGiacomo.Gabrielli@arm.com 3447944SGiacomo.Gabrielli@arm.com buildImmLoad("vldr", False, True, False, size=4, vldr=True) 3459046SAli.Saidi@ARM.com buildImmLoad("vldr", False, False, False, size=4, vldr=True) 3467944SGiacomo.Gabrielli@arm.com buildDoubleImmLoad("vldr", False, True, False, vldr=True) 3477944SGiacomo.Gabrielli@arm.com buildDoubleImmLoad("vldr", False, False, False, vldr=True) 3481060SN/A}}; 3492292SN/A