ldr.isa revision 7336:52dc042584d6
12SN/A// -*- mode:c++ -*- 29448SAndreas.Sandberg@ARM.com 38733Sgeoffrey.blake@arm.com// Copyright (c) 2010 ARM Limited 48733Sgeoffrey.blake@arm.com// All rights reserved 58733Sgeoffrey.blake@arm.com// 68733Sgeoffrey.blake@arm.com// The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com// not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com// property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com// to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com// licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com// terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com// unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com// modified or unmodified, in source code or in binary form. 141762SN/A// 152SN/A// Redistribution and use in source and binary forms, with or without 162SN/A// modification, are permitted provided that the following conditions are 172SN/A// met: redistributions of source code must retain the above copyright 182SN/A// notice, this list of conditions and the following disclaimer; 192SN/A// redistributions in binary form must reproduce the above copyright 202SN/A// notice, this list of conditions and the following disclaimer in the 212SN/A// documentation and/or other materials provided with the distribution; 222SN/A// neither the name of the copyright holders nor the names of its 232SN/A// contributors may be used to endorse or promote products derived from 242SN/A// this software without specific prior written permission. 252SN/A// 262SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 322SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 332SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372SN/A// 382SN/A// Authors: Gabe Black 392665Ssaidi@eecs.umich.edu 402665Ssaidi@eecs.umich.edulet {{ 412665Ssaidi@eecs.umich.edu 422665Ssaidi@eecs.umich.edu header_output = "" 432SN/A decoder_output = "" 442SN/A exec_output = "" 452623SN/A 462623SN/A def loadImmClassName(post, add, writeback, \ 472SN/A size=4, sign=False, user=False): 481354SN/A return memClassName("LOAD_IMM", post, add, writeback, 496658Snate@binkert.org size, sign, user) 501717SN/A 518887Sgeoffrey.blake@arm.com def loadRegClassName(post, add, writeback, \ 528229Snate@binkert.org size=4, sign=False, user=False): 532683Sktlim@umich.edu return memClassName("LOAD_REG", post, add, writeback, 541354SN/A size, sign, user) 552387SN/A 562387SN/A def loadDoubleImmClassName(post, add, writeback): 572387SN/A return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 5856SN/A 598779Sgblack@eecs.umich.edu def loadDoubleRegClassName(post, add, writeback): 605348Ssaidi@eecs.umich.edu return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 612SN/A 622SN/A def emitLoad(name, Name, imm, eaCode, accCode, \ 638779Sgblack@eecs.umich.edu memFlags, instFlags, base, double=False): 648779Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 652SN/A 668779Sgblack@eecs.umich.edu (newHeader, 672SN/A newDecoder, 684182Sgblack@eecs.umich.edu newExec) = loadStoreBase(name, Name, imm, 694182Sgblack@eecs.umich.edu eaCode, accCode, "", 708779Sgblack@eecs.umich.edu memFlags, instFlags, double, False, 718779Sgblack@eecs.umich.edu base, execTemplateBase = 'Load') 724182Sgblack@eecs.umich.edu 732SN/A header_output += newHeader 742SN/A decoder_output += newDecoder 752SN/A exec_output += newExec 762SN/A 772SN/A def buildImmLoad(mnem, post, add, writeback, \ 788737Skoansin.tan@gmail.com size=4, sign=False, user=False, \ 795529Snate@binkert.org prefetch=False, ldrex=False, vldr=False): 802420SN/A name = mnem 812623SN/A Name = loadImmClassName(post, add, writeback, \ 822SN/A size, sign, user) 832107SN/A 842159SN/A if add: 852455SN/A op = " +" 862455SN/A else: 872386SN/A op = " -" 882623SN/A 892SN/A offset = op + " imm" 901371SN/A eaCode = "EA = Base" 915348Ssaidi@eecs.umich.edu if not post: 927720Sgblack@eecs.umich.edu eaCode += offset 935348Ssaidi@eecs.umich.edu eaCode += ";" 947720Sgblack@eecs.umich.edu 955348Ssaidi@eecs.umich.edu memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 967720Sgblack@eecs.umich.edu if prefetch: 977720Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 985348Ssaidi@eecs.umich.edu memFlags.append("Request::PREFETCH") 995348Ssaidi@eecs.umich.edu accCode = ''' 1002SN/A uint64_t temp = Mem%s;\n 1015807Snate@binkert.org temp = temp; 1022SN/A ''' % buildMemSuffix(sign, size) 1032SN/A elif vldr: 1042SN/A Name = "%s_%s" % (mnem.upper(), Name) 1052SN/A accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" % \ 1062SN/A buildMemSuffix(sign, size) 1072SN/A else: 1082SN/A if ldrex: 1092SN/A memFlags.append("Request::LLSC") 1102SN/A Name = "%s_%s" % (mnem.upper(), Name) 1111400SN/A accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \ 1125529Snate@binkert.org buildMemSuffix(sign, size) 1132623SN/A 1142SN/A if not prefetch and not ldrex and not vldr: 1151400SN/A memFlags.append("ArmISA::TLB::AllowUnaligned") 1162683Sktlim@umich.edu 1172683Sktlim@umich.edu if writeback: 1182190SN/A accCode += "Base = Base %s;\n" % offset 1192683Sktlim@umich.edu base = buildMemBase("MemoryImm", post, writeback) 1202683Sktlim@umich.edu 1212683Sktlim@umich.edu emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 1222680Sktlim@umich.edu 1238733Sgeoffrey.blake@arm.com def buildRfeLoad(mnem, post, add, writeback): 1248733Sgeoffrey.blake@arm.com name = mnem 1258887Sgeoffrey.blake@arm.com Name = "RFE_" + loadImmClassName(post, add, writeback, 8) 1265169Ssaidi@eecs.umich.edu 1275169Ssaidi@eecs.umich.edu offset = 0 1285496Ssaidi@eecs.umich.edu if post != add: 1295496Ssaidi@eecs.umich.edu offset += 4 1305496Ssaidi@eecs.umich.edu if not add: 1318276SAli.Saidi@ARM.com offset -= 8 1325894Sgblack@eecs.umich.edu 1335496Ssaidi@eecs.umich.edu eaCode = "EA = Base + %d;" % offset 1345496Ssaidi@eecs.umich.edu 1355496Ssaidi@eecs.umich.edu wbDiff = -8 1365894Sgblack@eecs.umich.edu if add: 1375496Ssaidi@eecs.umich.edu wbDiff = 8 1385496Ssaidi@eecs.umich.edu accCode = ''' 1395496Ssaidi@eecs.umich.edu CPSR cpsr = Cpsr; 1405496Ssaidi@eecs.umich.edu NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); 1415496Ssaidi@eecs.umich.edu uint32_t newCpsr = 1425496Ssaidi@eecs.umich.edu cpsrWriteByInstr(cpsr | CondCodes, 1435496Ssaidi@eecs.umich.edu cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 1445169Ssaidi@eecs.umich.edu 0xF, true); 1452SN/A Cpsr = ~CondCodesMask & newCpsr; 1462SN/A CondCodes = CondCodesMask & newCpsr; 1472SN/A ''' 1482SN/A if writeback: 1492SN/A accCode += "Base = Base + %s;\n" % wbDiff 1502SN/A 1514181Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1524181Sgblack@eecs.umich.edu 1532107SN/A (newHeader, 1543276Sgblack@eecs.umich.edu newDecoder, 1551469SN/A newExec) = RfeBase(name, Name, eaCode, accCode, 1564377Sgblack@eecs.umich.edu ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], []) 1574377Sgblack@eecs.umich.edu 1584377Sgblack@eecs.umich.edu header_output += newHeader 1594377Sgblack@eecs.umich.edu decoder_output += newDecoder 1604377Sgblack@eecs.umich.edu exec_output += newExec 1614377Sgblack@eecs.umich.edu 1622623SN/A def buildRegLoad(mnem, post, add, writeback, size=4, sign=False, \ 1635894Sgblack@eecs.umich.edu user=False, prefetch=False): 1642623SN/A name = mnem 1652623SN/A Name = loadRegClassName(post, add, writeback, 1662623SN/A size, sign, user) 167180SN/A 1688737Skoansin.tan@gmail.com if add: 1698737Skoansin.tan@gmail.com op = " +" 1702SN/A else: 1712SN/A op = " -" 172334SN/A 173334SN/A offset = op + " shift_rm_imm(Index, shiftAmt," + \ 1742SN/A " shiftType, CondCodes<29:>)" 1759461Snilay@cs.wisc.edu eaCode = "EA = Base" 1769461Snilay@cs.wisc.edu if not post: 1772SN/A eaCode += offset 1782SN/A eaCode += ";" 179334SN/A 1805999Snate@binkert.org memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"] 1818834Satgutier@umich.edu if prefetch: 1828834Satgutier@umich.edu Name = "%s_%s" % (mnem.upper(), Name) 1838834Satgutier@umich.edu memFlags.append("Request::PREFETCH") 184707SN/A accCode = ''' 1854998Sgblack@eecs.umich.edu uint64_t temp = Mem%s;\n 1864998Sgblack@eecs.umich.edu temp = temp; 1878834Satgutier@umich.edu ''' % buildMemSuffix(sign, size) 1888834Satgutier@umich.edu else: 1898834Satgutier@umich.edu accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" % \ 1908834Satgutier@umich.edu buildMemSuffix(sign, size) 1918834Satgutier@umich.edu if writeback: 1928834Satgutier@umich.edu accCode += "Base = Base %s;\n" % offset 1938834Satgutier@umich.edu 1947897Shestness@cs.utexas.edu if not prefetch: 1954998Sgblack@eecs.umich.edu memFlags.append("ArmISA::TLB::AllowUnaligned") 1964998Sgblack@eecs.umich.edu 1974998Sgblack@eecs.umich.edu base = buildMemBase("MemoryReg", post, writeback) 1988834Satgutier@umich.edu 199707SN/A emitLoad(name, Name, False, eaCode, accCode, \ 200707SN/A memFlags, [], base) 201707SN/A 2022SN/A def buildDoubleImmLoad(mnem, post, add, writeback, \ 2038834Satgutier@umich.edu ldrex=False, vldr=False): 2048834Satgutier@umich.edu name = mnem 2058834Satgutier@umich.edu Name = loadDoubleImmClassName(post, add, writeback) 2068834Satgutier@umich.edu 2078834Satgutier@umich.edu if add: 2087897Shestness@cs.utexas.edu op = " +" 2097897Shestness@cs.utexas.edu else: 2107897Shestness@cs.utexas.edu op = " -" 2117897Shestness@cs.utexas.edu 2127897Shestness@cs.utexas.edu offset = op + " imm" 2137897Shestness@cs.utexas.edu eaCode = "EA = Base" 2147897Shestness@cs.utexas.edu if not post: 2157897Shestness@cs.utexas.edu eaCode += offset 2167897Shestness@cs.utexas.edu eaCode += ";" 2177897Shestness@cs.utexas.edu 2187897Shestness@cs.utexas.edu if not vldr: 2197897Shestness@cs.utexas.edu accCode = ''' 2207897Shestness@cs.utexas.edu CPSR cpsr = Cpsr; 2217897Shestness@cs.utexas.edu Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 2227897Shestness@cs.utexas.edu Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 2237897Shestness@cs.utexas.edu ''' 2247897Shestness@cs.utexas.edu else: 2257897Shestness@cs.utexas.edu accCode = ''' 2267897Shestness@cs.utexas.edu uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 2277897Shestness@cs.utexas.edu FpDest.uw = (uint32_t)swappedMem; 2287897Shestness@cs.utexas.edu FpDest2.uw = (uint32_t)(swappedMem >> 32); 2297897Shestness@cs.utexas.edu ''' 2307897Shestness@cs.utexas.edu if ldrex: 2317897Shestness@cs.utexas.edu memFlags = ["Request::LLSC"] 2327897Shestness@cs.utexas.edu else: 2337897Shestness@cs.utexas.edu memFlags = [] 2342SN/A if ldrex or vldr: 2355999Snate@binkert.org Name = "%s_%s" % (mnem.upper(), Name) 2367897Shestness@cs.utexas.edu if writeback: 2377897Shestness@cs.utexas.edu accCode += "Base = Base %s;\n" % offset 2387897Shestness@cs.utexas.edu base = buildMemBase("MemoryDImm", post, writeback) 2397897Shestness@cs.utexas.edu 2407897Shestness@cs.utexas.edu memFlags.extend(["ArmISA::TLB::MustBeOne", 2417897Shestness@cs.utexas.edu "ArmISA::TLB::AlignWord"]) 2427897Shestness@cs.utexas.edu 2437897Shestness@cs.utexas.edu emitLoad(name, Name, True, eaCode, accCode, \ 2442SN/A memFlags, [], base, double=True) 245124SN/A 246124SN/A def buildDoubleRegLoad(mnem, post, add, writeback): 247334SN/A name = mnem 248124SN/A Name = loadDoubleRegClassName(post, add, writeback) 2492SN/A 2505999Snate@binkert.org if add: 251729SN/A op = " +" 2522SN/A else: 2532390SN/A op = " -" 2545999Snate@binkert.org 2552SN/A offset = op + " shift_rm_imm(Index, shiftAmt," + \ 2562SN/A " shiftType, CondCodes<29:>)" 2572390SN/A eaCode = "EA = Base" 2585999Snate@binkert.org if not post: 2592390SN/A eaCode += offset 2602390SN/A eaCode += ";" 2612390SN/A 2625999Snate@binkert.org accCode = ''' 2632SN/A CPSR cpsr = Cpsr; 2642SN/A Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 2652390SN/A Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 2665999Snate@binkert.org ''' 2672390SN/A if writeback: 2682390SN/A accCode += "Base = Base %s;\n" % offset 2699448SAndreas.Sandberg@ARM.com base = buildMemBase("MemoryDReg", post, writeback) 2709448SAndreas.Sandberg@ARM.com 2719448SAndreas.Sandberg@ARM.com emitLoad(name, Name, False, eaCode, accCode, 2722SN/A ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"], 2731371SN/A [], base, double=True) 2741371SN/A 2752623SN/A def buildLoads(mnem, size=4, sign=False, user=False): 2765543Ssaidi@eecs.umich.edu buildImmLoad(mnem, True, True, True, size, sign, user) 2773918Ssaidi@eecs.umich.edu buildRegLoad(mnem, True, True, True, size, sign, user) 2781371SN/A buildImmLoad(mnem, True, False, True, size, sign, user) 279726SN/A buildRegLoad(mnem, True, False, True, size, sign, user) 280726SN/A buildImmLoad(mnem, False, True, True, size, sign, user) 281726SN/A buildRegLoad(mnem, False, True, True, size, sign, user) 282726SN/A buildImmLoad(mnem, False, False, True, size, sign, user) 283726SN/A buildRegLoad(mnem, False, False, True, size, sign, user) 284726SN/A buildImmLoad(mnem, False, True, False, size, sign, user) 285726SN/A buildRegLoad(mnem, False, True, False, size, sign, user) 286726SN/A buildImmLoad(mnem, False, False, False, size, sign, user) 287726SN/A buildRegLoad(mnem, False, False, False, size, sign, user) 288726SN/A 289705SN/A def buildDoubleLoads(mnem): 2903735Sstever@eecs.umich.edu buildDoubleImmLoad(mnem, True, True, True) 291726SN/A buildDoubleRegLoad(mnem, True, True, True) 2927897Shestness@cs.utexas.edu buildDoubleImmLoad(mnem, True, False, True) 2932683Sktlim@umich.edu buildDoubleRegLoad(mnem, True, False, True) 294726SN/A buildDoubleImmLoad(mnem, False, True, True) 295705SN/A buildDoubleRegLoad(mnem, False, True, True) 2963735Sstever@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, True) 297726SN/A buildDoubleRegLoad(mnem, False, False, True) 2987897Shestness@cs.utexas.edu buildDoubleImmLoad(mnem, False, True, False) 2999918Ssteve.reinhardt@amd.com buildDoubleRegLoad(mnem, False, True, False) 3002683Sktlim@umich.edu buildDoubleImmLoad(mnem, False, False, False) 301726SN/A buildDoubleRegLoad(mnem, False, False, False) 302705SN/A 3033735Sstever@eecs.umich.edu def buildRfeLoads(mnem): 3042455SN/A buildRfeLoad(mnem, True, True, True) 3057897Shestness@cs.utexas.edu buildRfeLoad(mnem, True, True, False) 3069918Ssteve.reinhardt@amd.com buildRfeLoad(mnem, True, False, True) 3072683Sktlim@umich.edu buildRfeLoad(mnem, True, False, False) 308726SN/A buildRfeLoad(mnem, False, True, True) 309705SN/A buildRfeLoad(mnem, False, True, False) 3103735Sstever@eecs.umich.edu buildRfeLoad(mnem, False, False, True) 311726SN/A buildRfeLoad(mnem, False, False, False) 3127897Shestness@cs.utexas.edu 3132683Sktlim@umich.edu def buildPrefetches(mnem): 314726SN/A buildRegLoad(mnem, False, False, False, size=1, prefetch=True) 315705SN/A buildImmLoad(mnem, False, False, False, size=1, prefetch=True) 3163735Sstever@eecs.umich.edu buildRegLoad(mnem, False, True, False, size=1, prefetch=True) 317726SN/A buildImmLoad(mnem, False, True, False, size=1, prefetch=True) 3187897Shestness@cs.utexas.edu 3199918Ssteve.reinhardt@amd.com buildLoads("ldr") 3202683Sktlim@umich.edu buildLoads("ldrt", user=True) 321726SN/A buildLoads("ldrb", size=1) 322726SN/A buildLoads("ldrbt", size=1, user=True) 3233735Sstever@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 3243735Sstever@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 3252455SN/A buildLoads("ldrh", size=2) 3267897Shestness@cs.utexas.edu buildLoads("ldrht", size=2, user=True) 3279918Ssteve.reinhardt@amd.com buildLoads("hdrsh", size=2, sign=True) 3282683Sktlim@umich.edu buildLoads("ldrsht", size=2, sign=True, user=True) 329726SN/A 330705SN/A buildDoubleLoads("ldrd") 3317597Sminkyu.jeong@arm.com 3327597Sminkyu.jeong@arm.com buildRfeLoads("rfe") 3337600Sminkyu.jeong@arm.com 3347600Sminkyu.jeong@arm.com buildPrefetches("pld") 3357600Sminkyu.jeong@arm.com buildPrefetches("pldw") 3367600Sminkyu.jeong@arm.com buildPrefetches("pli") 3377600Sminkyu.jeong@arm.com 3387600Sminkyu.jeong@arm.com buildImmLoad("ldrex", False, True, False, size=4, ldrex=True) 3397720Sgblack@eecs.umich.edu buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True) 3407720Sgblack@eecs.umich.edu buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True) 3417720Sgblack@eecs.umich.edu buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True) 3427720Sgblack@eecs.umich.edu 3437720Sgblack@eecs.umich.edu buildImmLoad("vldr", False, True, False, size=4, vldr=True) 344705SN/A buildImmLoad("vldr", False, False, False, size=4, vldr=True) 3454172Ssaidi@eecs.umich.edu buildDoubleImmLoad("vldr", False, True, False, vldr=True) 3464172Ssaidi@eecs.umich.edu buildDoubleImmLoad("vldr", False, False, False, vldr=True) 3474172Ssaidi@eecs.umich.edu}}; 3484172Ssaidi@eecs.umich.edu