ldr.isa revision 7244:d7fa6d111644
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 def loadImmClassName(post, add, writeback, \ 47 size=4, sign=False, user=False): 48 return memClassName("LOAD_IMM", post, add, writeback, 49 size, sign, user) 50 51 def loadRegClassName(post, add, writeback, \ 52 size=4, sign=False, user=False): 53 return memClassName("LOAD_REG", post, add, writeback, 54 size, sign, user) 55 56 def loadDoubleImmClassName(post, add, writeback): 57 return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 58 59 def loadDoubleRegClassName(post, add, writeback): 60 return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 61 62 def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base): 63 global header_output, decoder_output, exec_output 64 65 (newHeader, 66 newDecoder, 67 newExec) = loadStoreBase(name, Name, imm, 68 eaCode, accCode, 69 memFlags, instFlags, 70 base, execTemplateBase = 'Load') 71 72 header_output += newHeader 73 decoder_output += newDecoder 74 exec_output += newExec 75 76 def buildImmLoad(mnem, post, add, writeback, \ 77 size=4, sign=False, user=False, \ 78 prefetch=False, ldrex=False): 79 name = mnem 80 Name = loadImmClassName(post, add, writeback, \ 81 size, sign, user) 82 83 if add: 84 op = " +" 85 else: 86 op = " -" 87 88 offset = op + " imm" 89 eaCode = "EA = Base" 90 if not post: 91 eaCode += offset 92 eaCode += ";" 93 94 if prefetch: 95 Name = "%s_%s" % (mnem.upper(), Name) 96 memFlags = ["Request::PREFETCH"] 97 accCode = ''' 98 uint64_t temp = Mem%s;\n 99 temp = temp; 100 ''' % buildMemSuffix(sign, size) 101 else: 102 if ldrex: 103 memFlags = ["Request::LLSC"] 104 Name = "%s_%s" % (mnem.upper(), Name) 105 else: 106 memFlags = [] 107 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 108 if writeback: 109 accCode += "Base = Base %s;\n" % offset 110 base = buildMemBase("MemoryImm", post, writeback) 111 112 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 113 114 def buildRegLoad(mnem, post, add, writeback, \ 115 size=4, sign=False, user=False, prefetch=False): 116 name = mnem 117 Name = loadRegClassName(post, add, writeback, 118 size, sign, user) 119 120 if add: 121 op = " +" 122 else: 123 op = " -" 124 125 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 126 " shiftType, CondCodes<29:>)" 127 eaCode = "EA = Base" 128 if not post: 129 eaCode += offset 130 eaCode += ";" 131 132 if prefetch: 133 Name = "%s_%s" % (mnem.upper(), Name) 134 memFlags = ["Request::PREFETCH"] 135 accCode = ''' 136 uint64_t temp = Mem%s;\n 137 temp = temp; 138 ''' % buildMemSuffix(sign, size) 139 else: 140 memFlags = [] 141 accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 142 if writeback: 143 accCode += "Base = Base %s;\n" % offset 144 base = buildMemBase("MemoryReg", post, writeback) 145 146 emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base) 147 148 def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False): 149 name = mnem 150 Name = loadDoubleImmClassName(post, add, writeback) 151 152 if add: 153 op = " +" 154 else: 155 op = " -" 156 157 offset = op + " imm" 158 eaCode = "EA = Base" 159 if not post: 160 eaCode += offset 161 eaCode += ";" 162 163 accCode = ''' 164 Rdo = bits(Mem.ud, 31, 0); 165 Rde = bits(Mem.ud, 63, 32); 166 ''' 167 if ldrex: 168 memFlags = ["Request::LLSC"] 169 Name = "%s_%s" % (mnem.upper(), Name) 170 else: 171 memFlags = [] 172 if writeback: 173 accCode += "Base = Base %s;\n" % offset 174 base = buildMemBase("MemoryImm", post, writeback) 175 176 emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 177 178 def buildDoubleRegLoad(mnem, post, add, writeback): 179 name = mnem 180 Name = loadDoubleRegClassName(post, add, writeback) 181 182 if add: 183 op = " +" 184 else: 185 op = " -" 186 187 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 188 " shiftType, CondCodes<29:>)" 189 eaCode = "EA = Base" 190 if not post: 191 eaCode += offset 192 eaCode += ";" 193 194 accCode = ''' 195 Rdo = bits(Mem.ud, 31, 0); 196 Rde = bits(Mem.ud, 63, 32); 197 ''' 198 if writeback: 199 accCode += "Base = Base %s;\n" % offset 200 base = buildMemBase("MemoryReg", post, writeback) 201 202 emitLoad(name, Name, False, eaCode, accCode, [], [], base) 203 204 def buildLoads(mnem, size=4, sign=False, user=False): 205 buildImmLoad(mnem, True, True, True, size, sign, user) 206 buildRegLoad(mnem, True, True, True, size, sign, user) 207 buildImmLoad(mnem, True, False, True, size, sign, user) 208 buildRegLoad(mnem, True, False, True, size, sign, user) 209 buildImmLoad(mnem, False, True, True, size, sign, user) 210 buildRegLoad(mnem, False, True, True, size, sign, user) 211 buildImmLoad(mnem, False, False, True, size, sign, user) 212 buildRegLoad(mnem, False, False, True, size, sign, user) 213 buildImmLoad(mnem, False, True, False, size, sign, user) 214 buildRegLoad(mnem, False, True, False, size, sign, user) 215 buildImmLoad(mnem, False, False, False, size, sign, user) 216 buildRegLoad(mnem, False, False, False, size, sign, user) 217 218 def buildDoubleLoads(mnem): 219 buildDoubleImmLoad(mnem, True, True, True) 220 buildDoubleRegLoad(mnem, True, True, True) 221 buildDoubleImmLoad(mnem, True, False, True) 222 buildDoubleRegLoad(mnem, True, False, True) 223 buildDoubleImmLoad(mnem, False, True, True) 224 buildDoubleRegLoad(mnem, False, True, True) 225 buildDoubleImmLoad(mnem, False, False, True) 226 buildDoubleRegLoad(mnem, False, False, True) 227 buildDoubleImmLoad(mnem, False, True, False) 228 buildDoubleRegLoad(mnem, False, True, False) 229 buildDoubleImmLoad(mnem, False, False, False) 230 buildDoubleRegLoad(mnem, False, False, False) 231 232 def buildPrefetches(mnem): 233 buildRegLoad(mnem, False, False, False, size=1, prefetch=True) 234 buildImmLoad(mnem, False, False, False, size=1, prefetch=True) 235 buildRegLoad(mnem, False, True, False, size=1, prefetch=True) 236 buildImmLoad(mnem, False, True, False, size=1, prefetch=True) 237 238 buildLoads("ldr") 239 buildLoads("ldrt", user=True) 240 buildLoads("ldrb", size=1) 241 buildLoads("ldrbt", size=1, user=True) 242 buildLoads("ldrsb", size=1, sign=True) 243 buildLoads("ldrsbt", size=1, sign=True, user=True) 244 buildLoads("ldrh", size=2) 245 buildLoads("ldrht", size=2, user=True) 246 buildLoads("hdrsh", size=2, sign=True) 247 buildLoads("ldrsht", size=2, sign=True, user=True) 248 249 buildDoubleLoads("ldrd") 250 251 buildPrefetches("pld") 252 buildPrefetches("pldw") 253 buildPrefetches("pli") 254 255 buildImmLoad("ldrex", False, True, False, size=4, ldrex=True) 256 buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True) 257 buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True) 258 buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True) 259}}; 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