ldr.isa revision 7192:939e4ce4f1db 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    def loadImmClassName(post, add, writeback, \
47                         size=4, sign=False, user=False):
48        return memClassName("LOAD_IMM", post, add, writeback,
49                            size, sign, user)
50
51    def loadRegClassName(post, add, writeback, \
52                         size=4, sign=False, user=False):
53        return memClassName("LOAD_REG", post, add, writeback,
54                            size, sign, user)
55
56    def loadDoubleImmClassName(post, add, writeback):
57        return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
58
59    def loadDoubleRegClassName(post, add, writeback):
60        return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
61
62    def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
63        global header_output, decoder_output, exec_output
64
65        (newHeader,
66         newDecoder,
67         newExec) = loadStoreBase(name, Name, imm,
68                                  eaCode, accCode,
69                                  memFlags, instFlags,
70                                  base, execTemplateBase = 'Load')
71
72        header_output += newHeader
73        decoder_output += newDecoder
74        exec_output += newExec
75
76    def buildImmLoad(mnem, post, add, writeback, \
77                     size=4, sign=False, user=False, prefetch=False):
78        name = mnem
79        Name = loadImmClassName(post, add, writeback, \
80                                size, sign, user)
81
82        if add:
83            op = " +"
84        else:
85            op = " -"
86
87        offset = op + " imm"
88        eaCode = "EA = Base"
89        if not post:
90            eaCode += offset
91        eaCode += ";"
92
93        if prefetch:
94            Name = "%s_%s" % (mnem.upper(), Name)
95            memFlags = ["Request::PREFETCH"]
96            accCode = '''
97            uint64_t temp = Mem%s;\n
98            temp = temp;
99            ''' % buildMemSuffix(sign, size)
100        else:
101            memFlags = []
102            accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
103        if writeback:
104            accCode += "Base = Base %s;\n" % offset
105        base = buildMemBase("MemoryImm", post, writeback)
106
107        emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
108
109    def buildRegLoad(mnem, post, add, writeback, \
110                     size=4, sign=False, user=False, prefetch=False):
111        name = mnem
112        Name = loadRegClassName(post, add, writeback,
113                                size, sign, user)
114
115        if add:
116            op = " +"
117        else:
118            op = " -"
119
120        offset = op + " shift_rm_imm(Index, shiftAmt," + \
121                      " shiftType, CondCodes<29:>)"
122        eaCode = "EA = Base"
123        if not post:
124            eaCode += offset
125        eaCode += ";"
126
127        if prefetch:
128            Name = "%s_%s" % (mnem.upper(), Name)
129            memFlags = ["Request::PREFETCH"]
130            accCode = '''
131            uint64_t temp = Mem%s;\n
132            temp = temp;
133            ''' % buildMemSuffix(sign, size)
134        else:
135            memFlags = []
136            accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
137        if writeback:
138            accCode += "Base = Base %s;\n" % offset
139        base = buildMemBase("MemoryReg", post, writeback)
140
141        emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base)
142
143    def buildDoubleImmLoad(mnem, post, add, writeback):
144        name = mnem
145        Name = loadDoubleImmClassName(post, add, writeback)
146
147        if add:
148            op = " +"
149        else:
150            op = " -"
151
152        offset = op + " imm"
153        eaCode = "EA = Base"
154        if not post:
155            eaCode += offset
156        eaCode += ";"
157
158        accCode = '''
159        Rdo = bits(Mem.ud, 31, 0);
160        Rde = bits(Mem.ud, 63, 32);
161        '''
162        if writeback:
163            accCode += "Base = Base %s;\n" % offset
164        base = buildMemBase("MemoryImm", post, writeback)
165
166        emitLoad(name, Name, True, eaCode, accCode, [], [], base)
167
168    def buildDoubleRegLoad(mnem, post, add, writeback):
169        name = mnem
170        Name = loadDoubleRegClassName(post, add, writeback)
171
172        if add:
173            op = " +"
174        else:
175            op = " -"
176
177        offset = op + " shift_rm_imm(Index, shiftAmt," + \
178                      " shiftType, CondCodes<29:>)"
179        eaCode = "EA = Base"
180        if not post:
181            eaCode += offset
182        eaCode += ";"
183
184        accCode = '''
185        Rdo = bits(Mem.ud, 31, 0);
186        Rde = bits(Mem.ud, 63, 32);
187        '''
188        if writeback:
189            accCode += "Base = Base %s;\n" % offset
190        base = buildMemBase("MemoryReg", post, writeback)
191
192        emitLoad(name, Name, False, eaCode, accCode, [], [], base)
193
194    def buildLoads(mnem, size=4, sign=False, user=False):
195        buildImmLoad(mnem, True, True, True, size, sign, user)
196        buildRegLoad(mnem, True, True, True, size, sign, user)
197        buildImmLoad(mnem, True, False, True, size, sign, user)
198        buildRegLoad(mnem, True, False, True, size, sign, user)
199        buildImmLoad(mnem, False, True, True, size, sign, user)
200        buildRegLoad(mnem, False, True, True, size, sign, user)
201        buildImmLoad(mnem, False, False, True, size, sign, user)
202        buildRegLoad(mnem, False, False, True, size, sign, user)
203        buildImmLoad(mnem, False, True, False, size, sign, user)
204        buildRegLoad(mnem, False, True, False, size, sign, user)
205        buildImmLoad(mnem, False, False, False, size, sign, user)
206        buildRegLoad(mnem, False, False, False, size, sign, user)
207
208    def buildDoubleLoads(mnem):
209        buildDoubleImmLoad(mnem, True, True, True)
210        buildDoubleRegLoad(mnem, True, True, True)
211        buildDoubleImmLoad(mnem, True, False, True)
212        buildDoubleRegLoad(mnem, True, False, True)
213        buildDoubleImmLoad(mnem, False, True, True)
214        buildDoubleRegLoad(mnem, False, True, True)
215        buildDoubleImmLoad(mnem, False, False, True)
216        buildDoubleRegLoad(mnem, False, False, True)
217        buildDoubleImmLoad(mnem, False, True, False)
218        buildDoubleRegLoad(mnem, False, True, False)
219        buildDoubleImmLoad(mnem, False, False, False)
220        buildDoubleRegLoad(mnem, False, False, False)
221
222    def buildPrefetches(mnem):
223        buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
224        buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
225        buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
226        buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
227
228    buildLoads("ldr")
229    buildLoads("ldrt", user=True)
230    buildLoads("ldrb", size=1)
231    buildLoads("ldrbt", size=1, user=True)
232    buildLoads("ldrsb", size=1, sign=True)
233    buildLoads("ldrsbt", size=1, sign=True, user=True)
234    buildLoads("ldrh", size=2)
235    buildLoads("ldrht", size=2, user=True)
236    buildLoads("hdrsh", size=2, sign=True)
237    buildLoads("ldrsht", size=2, sign=True, user=True)
238
239    buildDoubleLoads("ldrd")
240
241    buildPrefetches("pld")
242    buildPrefetches("pldw")
243    buildPrefetches("pli")
244}};
245