ldr.isa revision 8303
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37119Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47119Sgblack@eecs.umich.edu// All rights reserved 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77119Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87119Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97119Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107119Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117119Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127119Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137119Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147119Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.edulet {{ 417119Sgblack@eecs.umich.edu 427119Sgblack@eecs.umich.edu header_output = "" 437119Sgblack@eecs.umich.edu decoder_output = "" 447119Sgblack@eecs.umich.edu exec_output = "" 457119Sgblack@eecs.umich.edu 467590Sgblack@eecs.umich.edu class LoadInst(LoadStoreInst): 477590Sgblack@eecs.umich.edu execBase = 'Load' 487119Sgblack@eecs.umich.edu 497590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback, 507590Sgblack@eecs.umich.edu size=4, sign=False, user=False, flavor="normal"): 517590Sgblack@eecs.umich.edu super(LoadInst, self).__init__() 527590Sgblack@eecs.umich.edu 537590Sgblack@eecs.umich.edu self.name = mnem 547590Sgblack@eecs.umich.edu self.post = post 557590Sgblack@eecs.umich.edu self.add = add 567590Sgblack@eecs.umich.edu self.writeback = writeback 577590Sgblack@eecs.umich.edu self.size = size 587590Sgblack@eecs.umich.edu self.sign = sign 597590Sgblack@eecs.umich.edu self.user = user 607590Sgblack@eecs.umich.edu self.flavor = flavor 618203SAli.Saidi@ARM.com self.rasPop = False 627590Sgblack@eecs.umich.edu 637590Sgblack@eecs.umich.edu if self.add: 647590Sgblack@eecs.umich.edu self.op = " +" 657590Sgblack@eecs.umich.edu else: 667590Sgblack@eecs.umich.edu self.op = " -" 677590Sgblack@eecs.umich.edu 687590Sgblack@eecs.umich.edu self.memFlags = ["ArmISA::TLB::MustBeOne"] 697590Sgblack@eecs.umich.edu self.codeBlobs = {"postacc_code" : ""} 707590Sgblack@eecs.umich.edu 718140SMatt.Horsnell@arm.com def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None): 727590Sgblack@eecs.umich.edu 737590Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 747590Sgblack@eecs.umich.edu 757590Sgblack@eecs.umich.edu codeBlobs = self.codeBlobs 767590Sgblack@eecs.umich.edu codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 777590Sgblack@eecs.umich.edu (newHeader, 787590Sgblack@eecs.umich.edu newDecoder, 797590Sgblack@eecs.umich.edu newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 808140SMatt.Horsnell@arm.com self.memFlags, instFlags, base, 818203SAli.Saidi@ARM.com wbDecl, pcDecl, self.rasPop) 827590Sgblack@eecs.umich.edu 837590Sgblack@eecs.umich.edu header_output += newHeader 847590Sgblack@eecs.umich.edu decoder_output += newDecoder 857590Sgblack@eecs.umich.edu exec_output += newExec 867590Sgblack@eecs.umich.edu 877590Sgblack@eecs.umich.edu class RfeInst(LoadInst): 887590Sgblack@eecs.umich.edu decConstBase = 'Rfe' 897590Sgblack@eecs.umich.edu 907590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback): 917590Sgblack@eecs.umich.edu super(RfeInst, self).__init__(mnem, post, add, writeback) 927590Sgblack@eecs.umich.edu self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8) 937590Sgblack@eecs.umich.edu 947590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AlignWord") 957590Sgblack@eecs.umich.edu 967590Sgblack@eecs.umich.edu def emit(self): 977590Sgblack@eecs.umich.edu offset = 0 987590Sgblack@eecs.umich.edu if self.post != self.add: 997590Sgblack@eecs.umich.edu offset += 4 1007590Sgblack@eecs.umich.edu if not self.add: 1017590Sgblack@eecs.umich.edu offset -= 8 1027590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 1037590Sgblack@eecs.umich.edu 1047590Sgblack@eecs.umich.edu wbDiff = -8 1057590Sgblack@eecs.umich.edu if self.add: 1067590Sgblack@eecs.umich.edu wbDiff = 8 1077590Sgblack@eecs.umich.edu accCode = ''' 1087590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 1098303SAli.Saidi@ARM.com cpsr.nz = CondCodesNZ; 1108303SAli.Saidi@ARM.com cpsr.c = CondCodesC; 1118303SAli.Saidi@ARM.com cpsr.v = CondCodesV; 1128303SAli.Saidi@ARM.com cpsr.ge = CondCodesGE; 1138303SAli.Saidi@ARM.com URc = cpsr; 1148140SMatt.Horsnell@arm.com URa = cSwap<uint32_t>(Mem.ud, cpsr.e); 1158140SMatt.Horsnell@arm.com URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 1167590Sgblack@eecs.umich.edu ''' 1177590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 1187590Sgblack@eecs.umich.edu 1197646Sgene.wu@arm.com wbDecl = None 1208140SMatt.Horsnell@arm.com pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);" 1218140SMatt.Horsnell@arm.com 1227646Sgene.wu@arm.com if self.writeback: 1237646Sgene.wu@arm.com wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff 1248140SMatt.Horsnell@arm.com self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl) 1257590Sgblack@eecs.umich.edu 1267590Sgblack@eecs.umich.edu class LoadImmInst(LoadInst): 1277590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1287590Sgblack@eecs.umich.edu super(LoadImmInst, self).__init__(*args, **kargs) 1297590Sgblack@eecs.umich.edu self.offset = self.op + " imm" 1307590Sgblack@eecs.umich.edu 1317646Sgene.wu@arm.com if self.add: 1327646Sgene.wu@arm.com self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 1337646Sgene.wu@arm.com else: 1347646Sgene.wu@arm.com self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 1357646Sgene.wu@arm.com 1368203SAli.Saidi@ARM.com if self.add and self.post and self.writeback and not self.sign and \ 1378203SAli.Saidi@ARM.com not self.user and self.size == 4: 1388203SAli.Saidi@ARM.com self.rasPop = True 1398203SAli.Saidi@ARM.com 1407590Sgblack@eecs.umich.edu class LoadRegInst(LoadInst): 1417590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1427590Sgblack@eecs.umich.edu super(LoadRegInst, self).__init__(*args, **kargs) 1437590Sgblack@eecs.umich.edu self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 1448303SAli.Saidi@ARM.com " shiftType, CondCodesC)" 1457646Sgene.wu@arm.com if self.add: 1467646Sgene.wu@arm.com self.wbDecl = ''' 1477646Sgene.wu@arm.com MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 1487646Sgene.wu@arm.com ''' 1497646Sgene.wu@arm.com else: 1507646Sgene.wu@arm.com self.wbDecl = ''' 1517646Sgene.wu@arm.com MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 1527646Sgene.wu@arm.com ''' 1537590Sgblack@eecs.umich.edu 1547590Sgblack@eecs.umich.edu class LoadSingle(LoadInst): 1557590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1567590Sgblack@eecs.umich.edu super(LoadSingle, self).__init__(*args, **kargs) 1577590Sgblack@eecs.umich.edu 1587590Sgblack@eecs.umich.edu # Build the default class name 1597590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback, 1607590Sgblack@eecs.umich.edu self.size, self.sign, self.user) 1617590Sgblack@eecs.umich.edu 1627590Sgblack@eecs.umich.edu # Add memory request flags where necessary 1637590Sgblack@eecs.umich.edu self.memFlags.append("%d" % (self.size - 1)) 1647590Sgblack@eecs.umich.edu if self.user: 1657590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::UserMode") 1667590Sgblack@eecs.umich.edu 1677725SAli.Saidi@ARM.com self.instFlags = [] 1687725SAli.Saidi@ARM.com if self.flavor == "dprefetch": 1697590Sgblack@eecs.umich.edu self.memFlags.append("Request::PREFETCH") 1707725SAli.Saidi@ARM.com self.instFlags = ['IsDataPrefetch'] 1717725SAli.Saidi@ARM.com elif self.flavor == "iprefetch": 1727725SAli.Saidi@ARM.com self.memFlags.append("Request::PREFETCH") 1737725SAli.Saidi@ARM.com self.instFlags = ['IsInstPrefetch'] 1747590Sgblack@eecs.umich.edu elif self.flavor == "exclusive": 1757590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 1767590Sgblack@eecs.umich.edu elif self.flavor == "normal": 1777590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AllowUnaligned") 1787590Sgblack@eecs.umich.edu 1797590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of loads 1807590Sgblack@eecs.umich.edu if self.flavor != "normal": 1817590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 1827590Sgblack@eecs.umich.edu 1837590Sgblack@eecs.umich.edu def emit(self): 1847590Sgblack@eecs.umich.edu # Address compuation code 1857590Sgblack@eecs.umich.edu eaCode = "EA = Base" 1867590Sgblack@eecs.umich.edu if not self.post: 1877590Sgblack@eecs.umich.edu eaCode += self.offset 1887590Sgblack@eecs.umich.edu eaCode += ";" 1897644Sali.saidi@arm.com 1907644Sali.saidi@arm.com if self.flavor == "fp": 1917644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 1927644Sali.saidi@arm.com 1937590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 1947590Sgblack@eecs.umich.edu 1957590Sgblack@eecs.umich.edu # Code that actually handles the access 1967725SAli.Saidi@ARM.com if self.flavor == "dprefetch" or self.flavor == "iprefetch": 1977590Sgblack@eecs.umich.edu accCode = 'uint64_t temp = Mem%s; temp = temp;' 1987590Sgblack@eecs.umich.edu elif self.flavor == "fp": 1997590Sgblack@eecs.umich.edu accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" 2007590Sgblack@eecs.umich.edu else: 2017590Sgblack@eecs.umich.edu accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" 2027590Sgblack@eecs.umich.edu accCode = accCode % buildMemSuffix(self.sign, self.size) 2037590Sgblack@eecs.umich.edu 2047590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2057590Sgblack@eecs.umich.edu 2067590Sgblack@eecs.umich.edu # Push it out to the output files 2077590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2087646Sgene.wu@arm.com wbDecl = None 2097646Sgene.wu@arm.com if self.writeback: 2107646Sgene.wu@arm.com wbDecl = self.wbDecl 2117725SAli.Saidi@ARM.com self.emitHelper(base, wbDecl, self.instFlags) 2127590Sgblack@eecs.umich.edu 2137590Sgblack@eecs.umich.edu def loadImmClassName(post, add, writeback, size=4, sign=False, user=False): 2147590Sgblack@eecs.umich.edu return memClassName("LOAD_IMM", post, add, writeback, size, sign, user) 2157590Sgblack@eecs.umich.edu 2167590Sgblack@eecs.umich.edu class LoadImm(LoadImmInst, LoadSingle): 2177646Sgene.wu@arm.com decConstBase = 'LoadImm' 2187590Sgblack@eecs.umich.edu basePrefix = 'MemoryImm' 2197590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadImmClassName) 2207590Sgblack@eecs.umich.edu 2217590Sgblack@eecs.umich.edu def loadRegClassName(post, add, writeback, size=4, sign=False, user=False): 2227590Sgblack@eecs.umich.edu return memClassName("LOAD_REG", post, add, writeback, size, sign, user) 2237590Sgblack@eecs.umich.edu 2247590Sgblack@eecs.umich.edu class LoadReg(LoadRegInst, LoadSingle): 2257646Sgene.wu@arm.com decConstBase = 'LoadReg' 2267590Sgblack@eecs.umich.edu basePrefix = 'MemoryReg' 2277590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadRegClassName) 2287590Sgblack@eecs.umich.edu 2297590Sgblack@eecs.umich.edu class LoadDouble(LoadInst): 2307590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 2317590Sgblack@eecs.umich.edu super(LoadDouble, self).__init__(*args, **kargs) 2327590Sgblack@eecs.umich.edu 2337590Sgblack@eecs.umich.edu # Build the default class name 2347590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback) 2357590Sgblack@eecs.umich.edu 2367590Sgblack@eecs.umich.edu # Add memory request flags where necessary 2377590Sgblack@eecs.umich.edu if self.flavor == "exclusive": 2387590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 2397593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 2407593SAli.Saidi@arm.com else: 2417593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignWord") 2427590Sgblack@eecs.umich.edu 2437590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of loads 2447590Sgblack@eecs.umich.edu if self.flavor != "normal": 2457590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 2467590Sgblack@eecs.umich.edu 2477590Sgblack@eecs.umich.edu def emit(self): 2487590Sgblack@eecs.umich.edu # Address computation code 2497590Sgblack@eecs.umich.edu eaCode = "EA = Base" 2507590Sgblack@eecs.umich.edu if not self.post: 2517590Sgblack@eecs.umich.edu eaCode += self.offset 2527590Sgblack@eecs.umich.edu eaCode += ";" 2537644Sali.saidi@arm.com 2547644Sali.saidi@arm.com if self.flavor == "fp": 2557644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 2567644Sali.saidi@arm.com 2577590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 2587590Sgblack@eecs.umich.edu 2597590Sgblack@eecs.umich.edu # Code that actually handles the access 2607590Sgblack@eecs.umich.edu if self.flavor != "fp": 2617590Sgblack@eecs.umich.edu accCode = ''' 2627590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 2637590Sgblack@eecs.umich.edu Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 2647590Sgblack@eecs.umich.edu Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 2657590Sgblack@eecs.umich.edu ''' 2667590Sgblack@eecs.umich.edu else: 2677590Sgblack@eecs.umich.edu accCode = ''' 2687590Sgblack@eecs.umich.edu uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 2697590Sgblack@eecs.umich.edu FpDest.uw = (uint32_t)swappedMem; 2707590Sgblack@eecs.umich.edu FpDest2.uw = (uint32_t)(swappedMem >> 32); 2717590Sgblack@eecs.umich.edu ''' 2727590Sgblack@eecs.umich.edu 2737590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2747590Sgblack@eecs.umich.edu 2757590Sgblack@eecs.umich.edu # Push it out to the output files 2767590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2777646Sgene.wu@arm.com wbDecl = None 2787646Sgene.wu@arm.com if self.writeback: 2797646Sgene.wu@arm.com wbDecl = self.wbDecl 2807646Sgene.wu@arm.com self.emitHelper(base, wbDecl) 2817119Sgblack@eecs.umich.edu 2827128Sgblack@eecs.umich.edu def loadDoubleImmClassName(post, add, writeback): 2837128Sgblack@eecs.umich.edu return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 2847128Sgblack@eecs.umich.edu 2857590Sgblack@eecs.umich.edu class LoadDoubleImm(LoadImmInst, LoadDouble): 2867590Sgblack@eecs.umich.edu decConstBase = 'LoadStoreDImm' 2877590Sgblack@eecs.umich.edu basePrefix = 'MemoryDImm' 2887590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadDoubleImmClassName) 2897590Sgblack@eecs.umich.edu 2907128Sgblack@eecs.umich.edu def loadDoubleRegClassName(post, add, writeback): 2917128Sgblack@eecs.umich.edu return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 2927128Sgblack@eecs.umich.edu 2937590Sgblack@eecs.umich.edu class LoadDoubleReg(LoadRegInst, LoadDouble): 2947646Sgene.wu@arm.com decConstBase = 'LoadDReg' 2957590Sgblack@eecs.umich.edu basePrefix = 'MemoryDReg' 2967590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadDoubleRegClassName) 2977128Sgblack@eecs.umich.edu 2987119Sgblack@eecs.umich.edu def buildLoads(mnem, size=4, sign=False, user=False): 2997590Sgblack@eecs.umich.edu LoadImm(mnem, True, True, True, size, sign, user).emit() 3007590Sgblack@eecs.umich.edu LoadReg(mnem, True, True, True, size, sign, user).emit() 3017590Sgblack@eecs.umich.edu LoadImm(mnem, True, False, True, size, sign, user).emit() 3027590Sgblack@eecs.umich.edu LoadReg(mnem, True, False, True, size, sign, user).emit() 3037590Sgblack@eecs.umich.edu LoadImm(mnem, False, True, True, size, sign, user).emit() 3047590Sgblack@eecs.umich.edu LoadReg(mnem, False, True, True, size, sign, user).emit() 3057590Sgblack@eecs.umich.edu LoadImm(mnem, False, False, True, size, sign, user).emit() 3067590Sgblack@eecs.umich.edu LoadReg(mnem, False, False, True, size, sign, user).emit() 3077590Sgblack@eecs.umich.edu LoadImm(mnem, False, True, False, size, sign, user).emit() 3087590Sgblack@eecs.umich.edu LoadReg(mnem, False, True, False, size, sign, user).emit() 3097590Sgblack@eecs.umich.edu LoadImm(mnem, False, False, False, size, sign, user).emit() 3107590Sgblack@eecs.umich.edu LoadReg(mnem, False, False, False, size, sign, user).emit() 3117119Sgblack@eecs.umich.edu 3127128Sgblack@eecs.umich.edu def buildDoubleLoads(mnem): 3137590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, True, True, True).emit() 3147590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, True, True, True).emit() 3157590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, True, False, True).emit() 3167590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, True, False, True).emit() 3177590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, True, True).emit() 3187590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, True, True).emit() 3197590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, False, True).emit() 3207590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, False, True).emit() 3217590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, True, False).emit() 3227590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, True, False).emit() 3237590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, False, False).emit() 3247590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, False, False).emit() 3257128Sgblack@eecs.umich.edu 3267292Sgblack@eecs.umich.edu def buildRfeLoads(mnem): 3277590Sgblack@eecs.umich.edu RfeInst(mnem, True, True, True).emit() 3287590Sgblack@eecs.umich.edu RfeInst(mnem, True, True, False).emit() 3297590Sgblack@eecs.umich.edu RfeInst(mnem, True, False, True).emit() 3307590Sgblack@eecs.umich.edu RfeInst(mnem, True, False, False).emit() 3317590Sgblack@eecs.umich.edu RfeInst(mnem, False, True, True).emit() 3327590Sgblack@eecs.umich.edu RfeInst(mnem, False, True, False).emit() 3337590Sgblack@eecs.umich.edu RfeInst(mnem, False, False, True).emit() 3347590Sgblack@eecs.umich.edu RfeInst(mnem, False, False, False).emit() 3357292Sgblack@eecs.umich.edu 3367725SAli.Saidi@ARM.com def buildPrefetches(mnem, type): 3377725SAli.Saidi@ARM.com LoadReg(mnem, False, False, False, size=1, flavor=type).emit() 3387725SAli.Saidi@ARM.com LoadImm(mnem, False, False, False, size=1, flavor=type).emit() 3397725SAli.Saidi@ARM.com LoadReg(mnem, False, True, False, size=1, flavor=type).emit() 3407725SAli.Saidi@ARM.com LoadImm(mnem, False, True, False, size=1, flavor=type).emit() 3417192Sgblack@eecs.umich.edu 3427119Sgblack@eecs.umich.edu buildLoads("ldr") 3437119Sgblack@eecs.umich.edu buildLoads("ldrt", user=True) 3447119Sgblack@eecs.umich.edu buildLoads("ldrb", size=1) 3457119Sgblack@eecs.umich.edu buildLoads("ldrbt", size=1, user=True) 3467119Sgblack@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 3477119Sgblack@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 3487119Sgblack@eecs.umich.edu buildLoads("ldrh", size=2) 3497119Sgblack@eecs.umich.edu buildLoads("ldrht", size=2, user=True) 3507119Sgblack@eecs.umich.edu buildLoads("hdrsh", size=2, sign=True) 3517119Sgblack@eecs.umich.edu buildLoads("ldrsht", size=2, sign=True, user=True) 3527128Sgblack@eecs.umich.edu 3537128Sgblack@eecs.umich.edu buildDoubleLoads("ldrd") 3547192Sgblack@eecs.umich.edu 3557292Sgblack@eecs.umich.edu buildRfeLoads("rfe") 3567292Sgblack@eecs.umich.edu 3577725SAli.Saidi@ARM.com buildPrefetches("pld", "dprefetch") 3587725SAli.Saidi@ARM.com buildPrefetches("pldw", "dprefetch") 3597725SAli.Saidi@ARM.com buildPrefetches("pli", "iprefetch") 3607244Sgblack@eecs.umich.edu 3617590Sgblack@eecs.umich.edu LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() 3627590Sgblack@eecs.umich.edu LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() 3637590Sgblack@eecs.umich.edu LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() 3647590Sgblack@eecs.umich.edu LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() 3657336Sgblack@eecs.umich.edu 3667590Sgblack@eecs.umich.edu LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() 3677590Sgblack@eecs.umich.edu LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() 3687590Sgblack@eecs.umich.edu LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() 3697590Sgblack@eecs.umich.edu LoadDoubleImm("vldr", False, False, False, flavor="fp").emit() 3707119Sgblack@eecs.umich.edu}}; 371