ldr.isa revision 7725
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37119Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47119Sgblack@eecs.umich.edu// All rights reserved 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77119Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87119Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97119Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107119Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117119Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127119Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137119Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147119Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.edulet {{ 417119Sgblack@eecs.umich.edu 427119Sgblack@eecs.umich.edu header_output = "" 437119Sgblack@eecs.umich.edu decoder_output = "" 447119Sgblack@eecs.umich.edu exec_output = "" 457119Sgblack@eecs.umich.edu 467590Sgblack@eecs.umich.edu class LoadInst(LoadStoreInst): 477590Sgblack@eecs.umich.edu execBase = 'Load' 487119Sgblack@eecs.umich.edu 497590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback, 507590Sgblack@eecs.umich.edu size=4, sign=False, user=False, flavor="normal"): 517590Sgblack@eecs.umich.edu super(LoadInst, self).__init__() 527590Sgblack@eecs.umich.edu 537590Sgblack@eecs.umich.edu self.name = mnem 547590Sgblack@eecs.umich.edu self.post = post 557590Sgblack@eecs.umich.edu self.add = add 567590Sgblack@eecs.umich.edu self.writeback = writeback 577590Sgblack@eecs.umich.edu self.size = size 587590Sgblack@eecs.umich.edu self.sign = sign 597590Sgblack@eecs.umich.edu self.user = user 607590Sgblack@eecs.umich.edu self.flavor = flavor 617590Sgblack@eecs.umich.edu 627590Sgblack@eecs.umich.edu if self.add: 637590Sgblack@eecs.umich.edu self.op = " +" 647590Sgblack@eecs.umich.edu else: 657590Sgblack@eecs.umich.edu self.op = " -" 667590Sgblack@eecs.umich.edu 677590Sgblack@eecs.umich.edu self.memFlags = ["ArmISA::TLB::MustBeOne"] 687590Sgblack@eecs.umich.edu self.codeBlobs = {"postacc_code" : ""} 697590Sgblack@eecs.umich.edu 707648SAli.Saidi@ARM.com def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []): 717590Sgblack@eecs.umich.edu 727590Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 737590Sgblack@eecs.umich.edu 747590Sgblack@eecs.umich.edu codeBlobs = self.codeBlobs 757590Sgblack@eecs.umich.edu codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 767590Sgblack@eecs.umich.edu (newHeader, 777590Sgblack@eecs.umich.edu newDecoder, 787590Sgblack@eecs.umich.edu newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 797648SAli.Saidi@ARM.com self.memFlags, instFlags, base, wbDecl) 807590Sgblack@eecs.umich.edu 817590Sgblack@eecs.umich.edu header_output += newHeader 827590Sgblack@eecs.umich.edu decoder_output += newDecoder 837590Sgblack@eecs.umich.edu exec_output += newExec 847590Sgblack@eecs.umich.edu 857590Sgblack@eecs.umich.edu class RfeInst(LoadInst): 867590Sgblack@eecs.umich.edu decConstBase = 'Rfe' 877590Sgblack@eecs.umich.edu 887590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback): 897590Sgblack@eecs.umich.edu super(RfeInst, self).__init__(mnem, post, add, writeback) 907590Sgblack@eecs.umich.edu self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8) 917590Sgblack@eecs.umich.edu 927590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AlignWord") 937590Sgblack@eecs.umich.edu 947590Sgblack@eecs.umich.edu def emit(self): 957590Sgblack@eecs.umich.edu offset = 0 967590Sgblack@eecs.umich.edu if self.post != self.add: 977590Sgblack@eecs.umich.edu offset += 4 987590Sgblack@eecs.umich.edu if not self.add: 997590Sgblack@eecs.umich.edu offset -= 8 1007590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 1017590Sgblack@eecs.umich.edu 1027590Sgblack@eecs.umich.edu wbDiff = -8 1037590Sgblack@eecs.umich.edu if self.add: 1047590Sgblack@eecs.umich.edu wbDiff = 8 1057590Sgblack@eecs.umich.edu accCode = ''' 1067590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 1077590Sgblack@eecs.umich.edu SCTLR sctlr = Sctlr; 1087720Sgblack@eecs.umich.edu ArmISA::PCState pc = PCS; 1097720Sgblack@eecs.umich.edu pc.instNPC(cSwap<uint32_t>(Mem.ud, cpsr.e)); 1107590Sgblack@eecs.umich.edu uint32_t newCpsr = 1117590Sgblack@eecs.umich.edu cpsrWriteByInstr(cpsr | CondCodes, 1127590Sgblack@eecs.umich.edu cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), 1137590Sgblack@eecs.umich.edu 0xF, true, sctlr.nmfi); 1147590Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1157720Sgblack@eecs.umich.edu pc.nextThumb(((CPSR)newCpsr).t); 1167720Sgblack@eecs.umich.edu pc.nextJazelle(((CPSR)newCpsr).j); 1177720Sgblack@eecs.umich.edu PCS = pc; 1187590Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 1197590Sgblack@eecs.umich.edu ''' 1207590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 1217590Sgblack@eecs.umich.edu 1227646Sgene.wu@arm.com wbDecl = None 1237646Sgene.wu@arm.com if self.writeback: 1247646Sgene.wu@arm.com wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff 1257648SAli.Saidi@ARM.com self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"]) 1267590Sgblack@eecs.umich.edu 1277590Sgblack@eecs.umich.edu class LoadImmInst(LoadInst): 1287590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1297590Sgblack@eecs.umich.edu super(LoadImmInst, self).__init__(*args, **kargs) 1307590Sgblack@eecs.umich.edu self.offset = self.op + " imm" 1317590Sgblack@eecs.umich.edu 1327646Sgene.wu@arm.com if self.add: 1337646Sgene.wu@arm.com self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 1347646Sgene.wu@arm.com else: 1357646Sgene.wu@arm.com self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 1367646Sgene.wu@arm.com 1377590Sgblack@eecs.umich.edu class LoadRegInst(LoadInst): 1387590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1397590Sgblack@eecs.umich.edu super(LoadRegInst, self).__init__(*args, **kargs) 1407590Sgblack@eecs.umich.edu self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 1417590Sgblack@eecs.umich.edu " shiftType, CondCodes<29:>)" 1427646Sgene.wu@arm.com if self.add: 1437646Sgene.wu@arm.com self.wbDecl = ''' 1447646Sgene.wu@arm.com MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 1457646Sgene.wu@arm.com ''' 1467646Sgene.wu@arm.com else: 1477646Sgene.wu@arm.com self.wbDecl = ''' 1487646Sgene.wu@arm.com MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 1497646Sgene.wu@arm.com ''' 1507590Sgblack@eecs.umich.edu 1517590Sgblack@eecs.umich.edu class LoadSingle(LoadInst): 1527590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1537590Sgblack@eecs.umich.edu super(LoadSingle, self).__init__(*args, **kargs) 1547590Sgblack@eecs.umich.edu 1557590Sgblack@eecs.umich.edu # Build the default class name 1567590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback, 1577590Sgblack@eecs.umich.edu self.size, self.sign, self.user) 1587590Sgblack@eecs.umich.edu 1597590Sgblack@eecs.umich.edu # Add memory request flags where necessary 1607590Sgblack@eecs.umich.edu self.memFlags.append("%d" % (self.size - 1)) 1617590Sgblack@eecs.umich.edu if self.user: 1627590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::UserMode") 1637590Sgblack@eecs.umich.edu 1647725SAli.Saidi@ARM.com self.instFlags = [] 1657725SAli.Saidi@ARM.com if self.flavor == "dprefetch": 1667590Sgblack@eecs.umich.edu self.memFlags.append("Request::PREFETCH") 1677725SAli.Saidi@ARM.com self.instFlags = ['IsDataPrefetch'] 1687725SAli.Saidi@ARM.com elif self.flavor == "iprefetch": 1697725SAli.Saidi@ARM.com self.memFlags.append("Request::PREFETCH") 1707725SAli.Saidi@ARM.com self.instFlags = ['IsInstPrefetch'] 1717590Sgblack@eecs.umich.edu elif self.flavor == "exclusive": 1727590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 1737590Sgblack@eecs.umich.edu elif self.flavor == "normal": 1747590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AllowUnaligned") 1757590Sgblack@eecs.umich.edu 1767590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of loads 1777590Sgblack@eecs.umich.edu if self.flavor != "normal": 1787590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 1797590Sgblack@eecs.umich.edu 1807590Sgblack@eecs.umich.edu def emit(self): 1817590Sgblack@eecs.umich.edu # Address compuation code 1827590Sgblack@eecs.umich.edu eaCode = "EA = Base" 1837590Sgblack@eecs.umich.edu if not self.post: 1847590Sgblack@eecs.umich.edu eaCode += self.offset 1857590Sgblack@eecs.umich.edu eaCode += ";" 1867644Sali.saidi@arm.com 1877644Sali.saidi@arm.com if self.flavor == "fp": 1887644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 1897644Sali.saidi@arm.com 1907590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 1917590Sgblack@eecs.umich.edu 1927590Sgblack@eecs.umich.edu # Code that actually handles the access 1937725SAli.Saidi@ARM.com if self.flavor == "dprefetch" or self.flavor == "iprefetch": 1947590Sgblack@eecs.umich.edu accCode = 'uint64_t temp = Mem%s; temp = temp;' 1957590Sgblack@eecs.umich.edu elif self.flavor == "fp": 1967590Sgblack@eecs.umich.edu accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" 1977590Sgblack@eecs.umich.edu else: 1987590Sgblack@eecs.umich.edu accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" 1997590Sgblack@eecs.umich.edu accCode = accCode % buildMemSuffix(self.sign, self.size) 2007590Sgblack@eecs.umich.edu 2017590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2027590Sgblack@eecs.umich.edu 2037590Sgblack@eecs.umich.edu # Push it out to the output files 2047590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2057646Sgene.wu@arm.com wbDecl = None 2067646Sgene.wu@arm.com if self.writeback: 2077646Sgene.wu@arm.com wbDecl = self.wbDecl 2087725SAli.Saidi@ARM.com self.emitHelper(base, wbDecl, self.instFlags) 2097590Sgblack@eecs.umich.edu 2107590Sgblack@eecs.umich.edu def loadImmClassName(post, add, writeback, size=4, sign=False, user=False): 2117590Sgblack@eecs.umich.edu return memClassName("LOAD_IMM", post, add, writeback, size, sign, user) 2127590Sgblack@eecs.umich.edu 2137590Sgblack@eecs.umich.edu class LoadImm(LoadImmInst, LoadSingle): 2147646Sgene.wu@arm.com decConstBase = 'LoadImm' 2157590Sgblack@eecs.umich.edu basePrefix = 'MemoryImm' 2167590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadImmClassName) 2177590Sgblack@eecs.umich.edu 2187590Sgblack@eecs.umich.edu def loadRegClassName(post, add, writeback, size=4, sign=False, user=False): 2197590Sgblack@eecs.umich.edu return memClassName("LOAD_REG", post, add, writeback, size, sign, user) 2207590Sgblack@eecs.umich.edu 2217590Sgblack@eecs.umich.edu class LoadReg(LoadRegInst, LoadSingle): 2227646Sgene.wu@arm.com decConstBase = 'LoadReg' 2237590Sgblack@eecs.umich.edu basePrefix = 'MemoryReg' 2247590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadRegClassName) 2257590Sgblack@eecs.umich.edu 2267590Sgblack@eecs.umich.edu class LoadDouble(LoadInst): 2277590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 2287590Sgblack@eecs.umich.edu super(LoadDouble, self).__init__(*args, **kargs) 2297590Sgblack@eecs.umich.edu 2307590Sgblack@eecs.umich.edu # Build the default class name 2317590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback) 2327590Sgblack@eecs.umich.edu 2337590Sgblack@eecs.umich.edu # Add memory request flags where necessary 2347590Sgblack@eecs.umich.edu if self.flavor == "exclusive": 2357590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 2367593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 2377593SAli.Saidi@arm.com else: 2387593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignWord") 2397590Sgblack@eecs.umich.edu 2407590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of loads 2417590Sgblack@eecs.umich.edu if self.flavor != "normal": 2427590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 2437590Sgblack@eecs.umich.edu 2447590Sgblack@eecs.umich.edu def emit(self): 2457590Sgblack@eecs.umich.edu # Address computation code 2467590Sgblack@eecs.umich.edu eaCode = "EA = Base" 2477590Sgblack@eecs.umich.edu if not self.post: 2487590Sgblack@eecs.umich.edu eaCode += self.offset 2497590Sgblack@eecs.umich.edu eaCode += ";" 2507644Sali.saidi@arm.com 2517644Sali.saidi@arm.com if self.flavor == "fp": 2527644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 2537644Sali.saidi@arm.com 2547590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 2557590Sgblack@eecs.umich.edu 2567590Sgblack@eecs.umich.edu # Code that actually handles the access 2577590Sgblack@eecs.umich.edu if self.flavor != "fp": 2587590Sgblack@eecs.umich.edu accCode = ''' 2597590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 2607590Sgblack@eecs.umich.edu Dest = cSwap<uint32_t>(Mem.ud, cpsr.e); 2617590Sgblack@eecs.umich.edu Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); 2627590Sgblack@eecs.umich.edu ''' 2637590Sgblack@eecs.umich.edu else: 2647590Sgblack@eecs.umich.edu accCode = ''' 2657590Sgblack@eecs.umich.edu uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e); 2667590Sgblack@eecs.umich.edu FpDest.uw = (uint32_t)swappedMem; 2677590Sgblack@eecs.umich.edu FpDest2.uw = (uint32_t)(swappedMem >> 32); 2687590Sgblack@eecs.umich.edu ''' 2697590Sgblack@eecs.umich.edu 2707590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2717590Sgblack@eecs.umich.edu 2727590Sgblack@eecs.umich.edu # Push it out to the output files 2737590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2747646Sgene.wu@arm.com wbDecl = None 2757646Sgene.wu@arm.com if self.writeback: 2767646Sgene.wu@arm.com wbDecl = self.wbDecl 2777646Sgene.wu@arm.com self.emitHelper(base, wbDecl) 2787119Sgblack@eecs.umich.edu 2797128Sgblack@eecs.umich.edu def loadDoubleImmClassName(post, add, writeback): 2807128Sgblack@eecs.umich.edu return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 2817128Sgblack@eecs.umich.edu 2827590Sgblack@eecs.umich.edu class LoadDoubleImm(LoadImmInst, LoadDouble): 2837590Sgblack@eecs.umich.edu decConstBase = 'LoadStoreDImm' 2847590Sgblack@eecs.umich.edu basePrefix = 'MemoryDImm' 2857590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadDoubleImmClassName) 2867590Sgblack@eecs.umich.edu 2877128Sgblack@eecs.umich.edu def loadDoubleRegClassName(post, add, writeback): 2887128Sgblack@eecs.umich.edu return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 2897128Sgblack@eecs.umich.edu 2907590Sgblack@eecs.umich.edu class LoadDoubleReg(LoadRegInst, LoadDouble): 2917646Sgene.wu@arm.com decConstBase = 'LoadDReg' 2927590Sgblack@eecs.umich.edu basePrefix = 'MemoryDReg' 2937590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadDoubleRegClassName) 2947128Sgblack@eecs.umich.edu 2957119Sgblack@eecs.umich.edu def buildLoads(mnem, size=4, sign=False, user=False): 2967590Sgblack@eecs.umich.edu LoadImm(mnem, True, True, True, size, sign, user).emit() 2977590Sgblack@eecs.umich.edu LoadReg(mnem, True, True, True, size, sign, user).emit() 2987590Sgblack@eecs.umich.edu LoadImm(mnem, True, False, True, size, sign, user).emit() 2997590Sgblack@eecs.umich.edu LoadReg(mnem, True, False, True, size, sign, user).emit() 3007590Sgblack@eecs.umich.edu LoadImm(mnem, False, True, True, size, sign, user).emit() 3017590Sgblack@eecs.umich.edu LoadReg(mnem, False, True, True, size, sign, user).emit() 3027590Sgblack@eecs.umich.edu LoadImm(mnem, False, False, True, size, sign, user).emit() 3037590Sgblack@eecs.umich.edu LoadReg(mnem, False, False, True, size, sign, user).emit() 3047590Sgblack@eecs.umich.edu LoadImm(mnem, False, True, False, size, sign, user).emit() 3057590Sgblack@eecs.umich.edu LoadReg(mnem, False, True, False, size, sign, user).emit() 3067590Sgblack@eecs.umich.edu LoadImm(mnem, False, False, False, size, sign, user).emit() 3077590Sgblack@eecs.umich.edu LoadReg(mnem, False, False, False, size, sign, user).emit() 3087119Sgblack@eecs.umich.edu 3097128Sgblack@eecs.umich.edu def buildDoubleLoads(mnem): 3107590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, True, True, True).emit() 3117590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, True, True, True).emit() 3127590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, True, False, True).emit() 3137590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, True, False, True).emit() 3147590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, True, True).emit() 3157590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, True, True).emit() 3167590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, False, True).emit() 3177590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, False, True).emit() 3187590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, True, False).emit() 3197590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, True, False).emit() 3207590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, False, False).emit() 3217590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, False, False).emit() 3227128Sgblack@eecs.umich.edu 3237292Sgblack@eecs.umich.edu def buildRfeLoads(mnem): 3247590Sgblack@eecs.umich.edu RfeInst(mnem, True, True, True).emit() 3257590Sgblack@eecs.umich.edu RfeInst(mnem, True, True, False).emit() 3267590Sgblack@eecs.umich.edu RfeInst(mnem, True, False, True).emit() 3277590Sgblack@eecs.umich.edu RfeInst(mnem, True, False, False).emit() 3287590Sgblack@eecs.umich.edu RfeInst(mnem, False, True, True).emit() 3297590Sgblack@eecs.umich.edu RfeInst(mnem, False, True, False).emit() 3307590Sgblack@eecs.umich.edu RfeInst(mnem, False, False, True).emit() 3317590Sgblack@eecs.umich.edu RfeInst(mnem, False, False, False).emit() 3327292Sgblack@eecs.umich.edu 3337725SAli.Saidi@ARM.com def buildPrefetches(mnem, type): 3347725SAli.Saidi@ARM.com LoadReg(mnem, False, False, False, size=1, flavor=type).emit() 3357725SAli.Saidi@ARM.com LoadImm(mnem, False, False, False, size=1, flavor=type).emit() 3367725SAli.Saidi@ARM.com LoadReg(mnem, False, True, False, size=1, flavor=type).emit() 3377725SAli.Saidi@ARM.com LoadImm(mnem, False, True, False, size=1, flavor=type).emit() 3387192Sgblack@eecs.umich.edu 3397119Sgblack@eecs.umich.edu buildLoads("ldr") 3407119Sgblack@eecs.umich.edu buildLoads("ldrt", user=True) 3417119Sgblack@eecs.umich.edu buildLoads("ldrb", size=1) 3427119Sgblack@eecs.umich.edu buildLoads("ldrbt", size=1, user=True) 3437119Sgblack@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 3447119Sgblack@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 3457119Sgblack@eecs.umich.edu buildLoads("ldrh", size=2) 3467119Sgblack@eecs.umich.edu buildLoads("ldrht", size=2, user=True) 3477119Sgblack@eecs.umich.edu buildLoads("hdrsh", size=2, sign=True) 3487119Sgblack@eecs.umich.edu buildLoads("ldrsht", size=2, sign=True, user=True) 3497128Sgblack@eecs.umich.edu 3507128Sgblack@eecs.umich.edu buildDoubleLoads("ldrd") 3517192Sgblack@eecs.umich.edu 3527292Sgblack@eecs.umich.edu buildRfeLoads("rfe") 3537292Sgblack@eecs.umich.edu 3547725SAli.Saidi@ARM.com buildPrefetches("pld", "dprefetch") 3557725SAli.Saidi@ARM.com buildPrefetches("pldw", "dprefetch") 3567725SAli.Saidi@ARM.com buildPrefetches("pli", "iprefetch") 3577244Sgblack@eecs.umich.edu 3587590Sgblack@eecs.umich.edu LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() 3597590Sgblack@eecs.umich.edu LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() 3607590Sgblack@eecs.umich.edu LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() 3617590Sgblack@eecs.umich.edu LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() 3627336Sgblack@eecs.umich.edu 3637590Sgblack@eecs.umich.edu LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() 3647590Sgblack@eecs.umich.edu LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() 3657590Sgblack@eecs.umich.edu LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() 3667590Sgblack@eecs.umich.edu LoadDoubleImm("vldr", False, False, False, flavor="fp").emit() 3677119Sgblack@eecs.umich.edu}}; 368