ldr.isa revision 7294
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37119Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47119Sgblack@eecs.umich.edu// All rights reserved 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77119Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87119Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97119Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107119Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117119Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127119Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137119Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147119Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.edulet {{ 417119Sgblack@eecs.umich.edu 427119Sgblack@eecs.umich.edu header_output = "" 437119Sgblack@eecs.umich.edu decoder_output = "" 447119Sgblack@eecs.umich.edu exec_output = "" 457119Sgblack@eecs.umich.edu 467119Sgblack@eecs.umich.edu def loadImmClassName(post, add, writeback, \ 477119Sgblack@eecs.umich.edu size=4, sign=False, user=False): 487119Sgblack@eecs.umich.edu return memClassName("LOAD_IMM", post, add, writeback, 497119Sgblack@eecs.umich.edu size, sign, user) 507119Sgblack@eecs.umich.edu 517119Sgblack@eecs.umich.edu def loadRegClassName(post, add, writeback, \ 527119Sgblack@eecs.umich.edu size=4, sign=False, user=False): 537119Sgblack@eecs.umich.edu return memClassName("LOAD_REG", post, add, writeback, 547119Sgblack@eecs.umich.edu size, sign, user) 557119Sgblack@eecs.umich.edu 567128Sgblack@eecs.umich.edu def loadDoubleImmClassName(post, add, writeback): 577128Sgblack@eecs.umich.edu return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 587128Sgblack@eecs.umich.edu 597128Sgblack@eecs.umich.edu def loadDoubleRegClassName(post, add, writeback): 607128Sgblack@eecs.umich.edu return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 617128Sgblack@eecs.umich.edu 627279Sgblack@eecs.umich.edu def emitLoad(name, Name, imm, eaCode, accCode, \ 637279Sgblack@eecs.umich.edu memFlags, instFlags, base, double=False): 647119Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 657119Sgblack@eecs.umich.edu 667119Sgblack@eecs.umich.edu (newHeader, 677119Sgblack@eecs.umich.edu newDecoder, 687132Sgblack@eecs.umich.edu newExec) = loadStoreBase(name, Name, imm, 697132Sgblack@eecs.umich.edu eaCode, accCode, 707279Sgblack@eecs.umich.edu memFlags, instFlags, double, 717132Sgblack@eecs.umich.edu base, execTemplateBase = 'Load') 727119Sgblack@eecs.umich.edu 737119Sgblack@eecs.umich.edu header_output += newHeader 747119Sgblack@eecs.umich.edu decoder_output += newDecoder 757119Sgblack@eecs.umich.edu exec_output += newExec 767119Sgblack@eecs.umich.edu 777119Sgblack@eecs.umich.edu def buildImmLoad(mnem, post, add, writeback, \ 787244Sgblack@eecs.umich.edu size=4, sign=False, user=False, \ 797244Sgblack@eecs.umich.edu prefetch=False, ldrex=False): 807119Sgblack@eecs.umich.edu name = mnem 817119Sgblack@eecs.umich.edu Name = loadImmClassName(post, add, writeback, \ 827119Sgblack@eecs.umich.edu size, sign, user) 837119Sgblack@eecs.umich.edu 847119Sgblack@eecs.umich.edu if add: 857119Sgblack@eecs.umich.edu op = " +" 867119Sgblack@eecs.umich.edu else: 877119Sgblack@eecs.umich.edu op = " -" 887119Sgblack@eecs.umich.edu 897119Sgblack@eecs.umich.edu offset = op + " imm" 907119Sgblack@eecs.umich.edu eaCode = "EA = Base" 917119Sgblack@eecs.umich.edu if not post: 927119Sgblack@eecs.umich.edu eaCode += offset 937119Sgblack@eecs.umich.edu eaCode += ";" 947119Sgblack@eecs.umich.edu 957294Sgblack@eecs.umich.edu memFlags = ["ArmISA::TLB::MustBeOne", "%d" % (size - 1)] 967192Sgblack@eecs.umich.edu if prefetch: 977192Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 987294Sgblack@eecs.umich.edu memFlags.append("Request::PREFETCH") 997192Sgblack@eecs.umich.edu accCode = ''' 1007192Sgblack@eecs.umich.edu uint64_t temp = Mem%s;\n 1017192Sgblack@eecs.umich.edu temp = temp; 1027192Sgblack@eecs.umich.edu ''' % buildMemSuffix(sign, size) 1037192Sgblack@eecs.umich.edu else: 1047244Sgblack@eecs.umich.edu if ldrex: 1057294Sgblack@eecs.umich.edu memFlags.append("Request::LLSC") 1067244Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 1077192Sgblack@eecs.umich.edu accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 1087294Sgblack@eecs.umich.edu 1097294Sgblack@eecs.umich.edu if not prefetch and not ldrex: 1107294Sgblack@eecs.umich.edu memFlags.append("ArmISA::TLB::AllowUnaligned") 1117294Sgblack@eecs.umich.edu 1127119Sgblack@eecs.umich.edu if writeback: 1137119Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 1147132Sgblack@eecs.umich.edu base = buildMemBase("MemoryImm", post, writeback) 1157119Sgblack@eecs.umich.edu 1167192Sgblack@eecs.umich.edu emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 1177119Sgblack@eecs.umich.edu 1187292Sgblack@eecs.umich.edu def buildRfeLoad(mnem, post, add, writeback): 1197292Sgblack@eecs.umich.edu name = mnem 1207292Sgblack@eecs.umich.edu Name = "RFE_" + loadImmClassName(post, add, writeback, 8) 1217292Sgblack@eecs.umich.edu 1227292Sgblack@eecs.umich.edu offset = 0 1237292Sgblack@eecs.umich.edu if post != add: 1247292Sgblack@eecs.umich.edu offset += 4 1257292Sgblack@eecs.umich.edu if not add: 1267292Sgblack@eecs.umich.edu offset -= 8 1277292Sgblack@eecs.umich.edu 1287292Sgblack@eecs.umich.edu eaCode = "EA = Base + %d;" % offset 1297292Sgblack@eecs.umich.edu 1307292Sgblack@eecs.umich.edu wbDiff = -8 1317292Sgblack@eecs.umich.edu if add: 1327292Sgblack@eecs.umich.edu wbDiff = 8 1337292Sgblack@eecs.umich.edu accCode = ''' 1347292Sgblack@eecs.umich.edu NPC = bits(Mem.ud, 31, 0); 1357292Sgblack@eecs.umich.edu uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, 1367292Sgblack@eecs.umich.edu bits(Mem.ud, 63, 32), 1377292Sgblack@eecs.umich.edu 0xF, true); 1387292Sgblack@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1397292Sgblack@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 1407292Sgblack@eecs.umich.edu ''' 1417292Sgblack@eecs.umich.edu if writeback: 1427292Sgblack@eecs.umich.edu accCode += "Base = Base + %s;\n" % wbDiff 1437292Sgblack@eecs.umich.edu 1447292Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 1457292Sgblack@eecs.umich.edu 1467292Sgblack@eecs.umich.edu (newHeader, 1477292Sgblack@eecs.umich.edu newDecoder, 1487294Sgblack@eecs.umich.edu newExec) = RfeBase(name, Name, eaCode, accCode, 1497294Sgblack@eecs.umich.edu ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], []) 1507292Sgblack@eecs.umich.edu 1517292Sgblack@eecs.umich.edu header_output += newHeader 1527292Sgblack@eecs.umich.edu decoder_output += newDecoder 1537292Sgblack@eecs.umich.edu exec_output += newExec 1547292Sgblack@eecs.umich.edu 1557119Sgblack@eecs.umich.edu def buildRegLoad(mnem, post, add, writeback, \ 1567192Sgblack@eecs.umich.edu size=4, sign=False, user=False, prefetch=False): 1577119Sgblack@eecs.umich.edu name = mnem 1587119Sgblack@eecs.umich.edu Name = loadRegClassName(post, add, writeback, 1597119Sgblack@eecs.umich.edu size, sign, user) 1607119Sgblack@eecs.umich.edu 1617119Sgblack@eecs.umich.edu if add: 1627119Sgblack@eecs.umich.edu op = " +" 1637119Sgblack@eecs.umich.edu else: 1647119Sgblack@eecs.umich.edu op = " -" 1657119Sgblack@eecs.umich.edu 1667119Sgblack@eecs.umich.edu offset = op + " shift_rm_imm(Index, shiftAmt," + \ 1677119Sgblack@eecs.umich.edu " shiftType, CondCodes<29:>)" 1687119Sgblack@eecs.umich.edu eaCode = "EA = Base" 1697119Sgblack@eecs.umich.edu if not post: 1707119Sgblack@eecs.umich.edu eaCode += offset 1717119Sgblack@eecs.umich.edu eaCode += ";" 1727119Sgblack@eecs.umich.edu 1737294Sgblack@eecs.umich.edu memFlags = ["%d" % (size - 1), "ArmISA::TLB::MustBeOne"] 1747192Sgblack@eecs.umich.edu if prefetch: 1757192Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 1767294Sgblack@eecs.umich.edu memFlags.append("Request::PREFETCH") 1777192Sgblack@eecs.umich.edu accCode = ''' 1787192Sgblack@eecs.umich.edu uint64_t temp = Mem%s;\n 1797192Sgblack@eecs.umich.edu temp = temp; 1807192Sgblack@eecs.umich.edu ''' % buildMemSuffix(sign, size) 1817192Sgblack@eecs.umich.edu else: 1827192Sgblack@eecs.umich.edu accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 1837119Sgblack@eecs.umich.edu if writeback: 1847119Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 1857294Sgblack@eecs.umich.edu 1867294Sgblack@eecs.umich.edu if not prefetch: 1877294Sgblack@eecs.umich.edu memFlags.append("ArmISA::TLB::AllowUnaligned") 1887294Sgblack@eecs.umich.edu 1897132Sgblack@eecs.umich.edu base = buildMemBase("MemoryReg", post, writeback) 1907119Sgblack@eecs.umich.edu 1917279Sgblack@eecs.umich.edu emitLoad(name, Name, False, eaCode, accCode, \ 1927279Sgblack@eecs.umich.edu memFlags, [], base) 1937119Sgblack@eecs.umich.edu 1947244Sgblack@eecs.umich.edu def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False): 1957128Sgblack@eecs.umich.edu name = mnem 1967128Sgblack@eecs.umich.edu Name = loadDoubleImmClassName(post, add, writeback) 1977128Sgblack@eecs.umich.edu 1987128Sgblack@eecs.umich.edu if add: 1997128Sgblack@eecs.umich.edu op = " +" 2007128Sgblack@eecs.umich.edu else: 2017128Sgblack@eecs.umich.edu op = " -" 2027128Sgblack@eecs.umich.edu 2037128Sgblack@eecs.umich.edu offset = op + " imm" 2047128Sgblack@eecs.umich.edu eaCode = "EA = Base" 2057128Sgblack@eecs.umich.edu if not post: 2067128Sgblack@eecs.umich.edu eaCode += offset 2077128Sgblack@eecs.umich.edu eaCode += ";" 2087128Sgblack@eecs.umich.edu 2097128Sgblack@eecs.umich.edu accCode = ''' 2107279Sgblack@eecs.umich.edu Dest = bits(Mem.ud, 31, 0); 2117279Sgblack@eecs.umich.edu Dest2 = bits(Mem.ud, 63, 32); 2127128Sgblack@eecs.umich.edu ''' 2137244Sgblack@eecs.umich.edu if ldrex: 2147244Sgblack@eecs.umich.edu memFlags = ["Request::LLSC"] 2157244Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 2167244Sgblack@eecs.umich.edu else: 2177244Sgblack@eecs.umich.edu memFlags = [] 2187128Sgblack@eecs.umich.edu if writeback: 2197128Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 2207279Sgblack@eecs.umich.edu base = buildMemBase("MemoryDImm", post, writeback) 2217128Sgblack@eecs.umich.edu 2227294Sgblack@eecs.umich.edu memFlags.extend(["ArmISA::TLB::MustBeOne", 2237294Sgblack@eecs.umich.edu "ArmISA::TLB::AlignWord"]) 2247294Sgblack@eecs.umich.edu 2257279Sgblack@eecs.umich.edu emitLoad(name, Name, True, eaCode, accCode, \ 2267279Sgblack@eecs.umich.edu memFlags, [], base, double=True) 2277128Sgblack@eecs.umich.edu 2287128Sgblack@eecs.umich.edu def buildDoubleRegLoad(mnem, post, add, writeback): 2297128Sgblack@eecs.umich.edu name = mnem 2307128Sgblack@eecs.umich.edu Name = loadDoubleRegClassName(post, add, writeback) 2317128Sgblack@eecs.umich.edu 2327128Sgblack@eecs.umich.edu if add: 2337128Sgblack@eecs.umich.edu op = " +" 2347128Sgblack@eecs.umich.edu else: 2357128Sgblack@eecs.umich.edu op = " -" 2367128Sgblack@eecs.umich.edu 2377128Sgblack@eecs.umich.edu offset = op + " shift_rm_imm(Index, shiftAmt," + \ 2387128Sgblack@eecs.umich.edu " shiftType, CondCodes<29:>)" 2397128Sgblack@eecs.umich.edu eaCode = "EA = Base" 2407128Sgblack@eecs.umich.edu if not post: 2417128Sgblack@eecs.umich.edu eaCode += offset 2427128Sgblack@eecs.umich.edu eaCode += ";" 2437128Sgblack@eecs.umich.edu 2447128Sgblack@eecs.umich.edu accCode = ''' 2457279Sgblack@eecs.umich.edu Dest = bits(Mem.ud, 31, 0); 2467279Sgblack@eecs.umich.edu Dest2 = bits(Mem.ud, 63, 32); 2477128Sgblack@eecs.umich.edu ''' 2487128Sgblack@eecs.umich.edu if writeback: 2497128Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 2507279Sgblack@eecs.umich.edu base = buildMemBase("MemoryDReg", post, writeback) 2517128Sgblack@eecs.umich.edu 2527279Sgblack@eecs.umich.edu emitLoad(name, Name, False, eaCode, accCode, 2537294Sgblack@eecs.umich.edu ["ArmISA::TLB::MustBeOne", "ArmISA::TLB::AlignWord"], 2547294Sgblack@eecs.umich.edu [], base, double=True) 2557128Sgblack@eecs.umich.edu 2567119Sgblack@eecs.umich.edu def buildLoads(mnem, size=4, sign=False, user=False): 2577119Sgblack@eecs.umich.edu buildImmLoad(mnem, True, True, True, size, sign, user) 2587119Sgblack@eecs.umich.edu buildRegLoad(mnem, True, True, True, size, sign, user) 2597119Sgblack@eecs.umich.edu buildImmLoad(mnem, True, False, True, size, sign, user) 2607119Sgblack@eecs.umich.edu buildRegLoad(mnem, True, False, True, size, sign, user) 2617119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, True, True, size, sign, user) 2627119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, True, True, size, sign, user) 2637119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, False, True, size, sign, user) 2647119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, False, True, size, sign, user) 2657119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, True, False, size, sign, user) 2667119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, True, False, size, sign, user) 2677119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, False, False, size, sign, user) 2687119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, False, False, size, sign, user) 2697119Sgblack@eecs.umich.edu 2707128Sgblack@eecs.umich.edu def buildDoubleLoads(mnem): 2717128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, True, True, True) 2727128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, True, True, True) 2737128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, True, False, True) 2747128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, True, False, True) 2757128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, True, True) 2767128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, True, True) 2777128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, True) 2787128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, False, True) 2797128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, True, False) 2807128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, True, False) 2817128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, False) 2827128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, False, False) 2837128Sgblack@eecs.umich.edu 2847292Sgblack@eecs.umich.edu def buildRfeLoads(mnem): 2857292Sgblack@eecs.umich.edu buildRfeLoad(mnem, True, True, True) 2867292Sgblack@eecs.umich.edu buildRfeLoad(mnem, True, True, False) 2877292Sgblack@eecs.umich.edu buildRfeLoad(mnem, True, False, True) 2887292Sgblack@eecs.umich.edu buildRfeLoad(mnem, True, False, False) 2897292Sgblack@eecs.umich.edu buildRfeLoad(mnem, False, True, True) 2907292Sgblack@eecs.umich.edu buildRfeLoad(mnem, False, True, False) 2917292Sgblack@eecs.umich.edu buildRfeLoad(mnem, False, False, True) 2927292Sgblack@eecs.umich.edu buildRfeLoad(mnem, False, False, False) 2937292Sgblack@eecs.umich.edu 2947192Sgblack@eecs.umich.edu def buildPrefetches(mnem): 2957192Sgblack@eecs.umich.edu buildRegLoad(mnem, False, False, False, size=1, prefetch=True) 2967192Sgblack@eecs.umich.edu buildImmLoad(mnem, False, False, False, size=1, prefetch=True) 2977192Sgblack@eecs.umich.edu buildRegLoad(mnem, False, True, False, size=1, prefetch=True) 2987192Sgblack@eecs.umich.edu buildImmLoad(mnem, False, True, False, size=1, prefetch=True) 2997192Sgblack@eecs.umich.edu 3007119Sgblack@eecs.umich.edu buildLoads("ldr") 3017119Sgblack@eecs.umich.edu buildLoads("ldrt", user=True) 3027119Sgblack@eecs.umich.edu buildLoads("ldrb", size=1) 3037119Sgblack@eecs.umich.edu buildLoads("ldrbt", size=1, user=True) 3047119Sgblack@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 3057119Sgblack@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 3067119Sgblack@eecs.umich.edu buildLoads("ldrh", size=2) 3077119Sgblack@eecs.umich.edu buildLoads("ldrht", size=2, user=True) 3087119Sgblack@eecs.umich.edu buildLoads("hdrsh", size=2, sign=True) 3097119Sgblack@eecs.umich.edu buildLoads("ldrsht", size=2, sign=True, user=True) 3107128Sgblack@eecs.umich.edu 3117128Sgblack@eecs.umich.edu buildDoubleLoads("ldrd") 3127192Sgblack@eecs.umich.edu 3137292Sgblack@eecs.umich.edu buildRfeLoads("rfe") 3147292Sgblack@eecs.umich.edu 3157192Sgblack@eecs.umich.edu buildPrefetches("pld") 3167192Sgblack@eecs.umich.edu buildPrefetches("pldw") 3177192Sgblack@eecs.umich.edu buildPrefetches("pli") 3187244Sgblack@eecs.umich.edu 3197244Sgblack@eecs.umich.edu buildImmLoad("ldrex", False, True, False, size=4, ldrex=True) 3207244Sgblack@eecs.umich.edu buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True) 3217244Sgblack@eecs.umich.edu buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True) 3227244Sgblack@eecs.umich.edu buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True) 3237119Sgblack@eecs.umich.edu}}; 324