ldr.isa revision 7244
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 37119Sgblack@eecs.umich.edu// Copyright (c) 2010 ARM Limited 47119Sgblack@eecs.umich.edu// All rights reserved 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77119Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87119Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97119Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107119Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117119Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127119Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137119Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147119Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.edulet {{ 417119Sgblack@eecs.umich.edu 427119Sgblack@eecs.umich.edu header_output = "" 437119Sgblack@eecs.umich.edu decoder_output = "" 447119Sgblack@eecs.umich.edu exec_output = "" 457119Sgblack@eecs.umich.edu 467119Sgblack@eecs.umich.edu def loadImmClassName(post, add, writeback, \ 477119Sgblack@eecs.umich.edu size=4, sign=False, user=False): 487119Sgblack@eecs.umich.edu return memClassName("LOAD_IMM", post, add, writeback, 497119Sgblack@eecs.umich.edu size, sign, user) 507119Sgblack@eecs.umich.edu 517119Sgblack@eecs.umich.edu def loadRegClassName(post, add, writeback, \ 527119Sgblack@eecs.umich.edu size=4, sign=False, user=False): 537119Sgblack@eecs.umich.edu return memClassName("LOAD_REG", post, add, writeback, 547119Sgblack@eecs.umich.edu size, sign, user) 557119Sgblack@eecs.umich.edu 567128Sgblack@eecs.umich.edu def loadDoubleImmClassName(post, add, writeback): 577128Sgblack@eecs.umich.edu return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 587128Sgblack@eecs.umich.edu 597128Sgblack@eecs.umich.edu def loadDoubleRegClassName(post, add, writeback): 607128Sgblack@eecs.umich.edu return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 617128Sgblack@eecs.umich.edu 627119Sgblack@eecs.umich.edu def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base): 637119Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 647119Sgblack@eecs.umich.edu 657119Sgblack@eecs.umich.edu (newHeader, 667119Sgblack@eecs.umich.edu newDecoder, 677132Sgblack@eecs.umich.edu newExec) = loadStoreBase(name, Name, imm, 687132Sgblack@eecs.umich.edu eaCode, accCode, 697132Sgblack@eecs.umich.edu memFlags, instFlags, 707132Sgblack@eecs.umich.edu base, execTemplateBase = 'Load') 717119Sgblack@eecs.umich.edu 727119Sgblack@eecs.umich.edu header_output += newHeader 737119Sgblack@eecs.umich.edu decoder_output += newDecoder 747119Sgblack@eecs.umich.edu exec_output += newExec 757119Sgblack@eecs.umich.edu 767119Sgblack@eecs.umich.edu def buildImmLoad(mnem, post, add, writeback, \ 777244Sgblack@eecs.umich.edu size=4, sign=False, user=False, \ 787244Sgblack@eecs.umich.edu prefetch=False, ldrex=False): 797119Sgblack@eecs.umich.edu name = mnem 807119Sgblack@eecs.umich.edu Name = loadImmClassName(post, add, writeback, \ 817119Sgblack@eecs.umich.edu size, sign, user) 827119Sgblack@eecs.umich.edu 837119Sgblack@eecs.umich.edu if add: 847119Sgblack@eecs.umich.edu op = " +" 857119Sgblack@eecs.umich.edu else: 867119Sgblack@eecs.umich.edu op = " -" 877119Sgblack@eecs.umich.edu 887119Sgblack@eecs.umich.edu offset = op + " imm" 897119Sgblack@eecs.umich.edu eaCode = "EA = Base" 907119Sgblack@eecs.umich.edu if not post: 917119Sgblack@eecs.umich.edu eaCode += offset 927119Sgblack@eecs.umich.edu eaCode += ";" 937119Sgblack@eecs.umich.edu 947192Sgblack@eecs.umich.edu if prefetch: 957192Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 967192Sgblack@eecs.umich.edu memFlags = ["Request::PREFETCH"] 977192Sgblack@eecs.umich.edu accCode = ''' 987192Sgblack@eecs.umich.edu uint64_t temp = Mem%s;\n 997192Sgblack@eecs.umich.edu temp = temp; 1007192Sgblack@eecs.umich.edu ''' % buildMemSuffix(sign, size) 1017192Sgblack@eecs.umich.edu else: 1027244Sgblack@eecs.umich.edu if ldrex: 1037244Sgblack@eecs.umich.edu memFlags = ["Request::LLSC"] 1047244Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 1057244Sgblack@eecs.umich.edu else: 1067244Sgblack@eecs.umich.edu memFlags = [] 1077192Sgblack@eecs.umich.edu accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 1087119Sgblack@eecs.umich.edu if writeback: 1097119Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 1107132Sgblack@eecs.umich.edu base = buildMemBase("MemoryImm", post, writeback) 1117119Sgblack@eecs.umich.edu 1127192Sgblack@eecs.umich.edu emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 1137119Sgblack@eecs.umich.edu 1147119Sgblack@eecs.umich.edu def buildRegLoad(mnem, post, add, writeback, \ 1157192Sgblack@eecs.umich.edu size=4, sign=False, user=False, prefetch=False): 1167119Sgblack@eecs.umich.edu name = mnem 1177119Sgblack@eecs.umich.edu Name = loadRegClassName(post, add, writeback, 1187119Sgblack@eecs.umich.edu size, sign, user) 1197119Sgblack@eecs.umich.edu 1207119Sgblack@eecs.umich.edu if add: 1217119Sgblack@eecs.umich.edu op = " +" 1227119Sgblack@eecs.umich.edu else: 1237119Sgblack@eecs.umich.edu op = " -" 1247119Sgblack@eecs.umich.edu 1257119Sgblack@eecs.umich.edu offset = op + " shift_rm_imm(Index, shiftAmt," + \ 1267119Sgblack@eecs.umich.edu " shiftType, CondCodes<29:>)" 1277119Sgblack@eecs.umich.edu eaCode = "EA = Base" 1287119Sgblack@eecs.umich.edu if not post: 1297119Sgblack@eecs.umich.edu eaCode += offset 1307119Sgblack@eecs.umich.edu eaCode += ";" 1317119Sgblack@eecs.umich.edu 1327192Sgblack@eecs.umich.edu if prefetch: 1337192Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 1347192Sgblack@eecs.umich.edu memFlags = ["Request::PREFETCH"] 1357192Sgblack@eecs.umich.edu accCode = ''' 1367192Sgblack@eecs.umich.edu uint64_t temp = Mem%s;\n 1377192Sgblack@eecs.umich.edu temp = temp; 1387192Sgblack@eecs.umich.edu ''' % buildMemSuffix(sign, size) 1397192Sgblack@eecs.umich.edu else: 1407192Sgblack@eecs.umich.edu memFlags = [] 1417192Sgblack@eecs.umich.edu accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size) 1427119Sgblack@eecs.umich.edu if writeback: 1437119Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 1447132Sgblack@eecs.umich.edu base = buildMemBase("MemoryReg", post, writeback) 1457119Sgblack@eecs.umich.edu 1467192Sgblack@eecs.umich.edu emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base) 1477119Sgblack@eecs.umich.edu 1487244Sgblack@eecs.umich.edu def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False): 1497128Sgblack@eecs.umich.edu name = mnem 1507128Sgblack@eecs.umich.edu Name = loadDoubleImmClassName(post, add, writeback) 1517128Sgblack@eecs.umich.edu 1527128Sgblack@eecs.umich.edu if add: 1537128Sgblack@eecs.umich.edu op = " +" 1547128Sgblack@eecs.umich.edu else: 1557128Sgblack@eecs.umich.edu op = " -" 1567128Sgblack@eecs.umich.edu 1577128Sgblack@eecs.umich.edu offset = op + " imm" 1587128Sgblack@eecs.umich.edu eaCode = "EA = Base" 1597128Sgblack@eecs.umich.edu if not post: 1607128Sgblack@eecs.umich.edu eaCode += offset 1617128Sgblack@eecs.umich.edu eaCode += ";" 1627128Sgblack@eecs.umich.edu 1637128Sgblack@eecs.umich.edu accCode = ''' 1647128Sgblack@eecs.umich.edu Rdo = bits(Mem.ud, 31, 0); 1657128Sgblack@eecs.umich.edu Rde = bits(Mem.ud, 63, 32); 1667128Sgblack@eecs.umich.edu ''' 1677244Sgblack@eecs.umich.edu if ldrex: 1687244Sgblack@eecs.umich.edu memFlags = ["Request::LLSC"] 1697244Sgblack@eecs.umich.edu Name = "%s_%s" % (mnem.upper(), Name) 1707244Sgblack@eecs.umich.edu else: 1717244Sgblack@eecs.umich.edu memFlags = [] 1727128Sgblack@eecs.umich.edu if writeback: 1737128Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 1747132Sgblack@eecs.umich.edu base = buildMemBase("MemoryImm", post, writeback) 1757128Sgblack@eecs.umich.edu 1767244Sgblack@eecs.umich.edu emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) 1777128Sgblack@eecs.umich.edu 1787128Sgblack@eecs.umich.edu def buildDoubleRegLoad(mnem, post, add, writeback): 1797128Sgblack@eecs.umich.edu name = mnem 1807128Sgblack@eecs.umich.edu Name = loadDoubleRegClassName(post, add, writeback) 1817128Sgblack@eecs.umich.edu 1827128Sgblack@eecs.umich.edu if add: 1837128Sgblack@eecs.umich.edu op = " +" 1847128Sgblack@eecs.umich.edu else: 1857128Sgblack@eecs.umich.edu op = " -" 1867128Sgblack@eecs.umich.edu 1877128Sgblack@eecs.umich.edu offset = op + " shift_rm_imm(Index, shiftAmt," + \ 1887128Sgblack@eecs.umich.edu " shiftType, CondCodes<29:>)" 1897128Sgblack@eecs.umich.edu eaCode = "EA = Base" 1907128Sgblack@eecs.umich.edu if not post: 1917128Sgblack@eecs.umich.edu eaCode += offset 1927128Sgblack@eecs.umich.edu eaCode += ";" 1937128Sgblack@eecs.umich.edu 1947128Sgblack@eecs.umich.edu accCode = ''' 1957128Sgblack@eecs.umich.edu Rdo = bits(Mem.ud, 31, 0); 1967128Sgblack@eecs.umich.edu Rde = bits(Mem.ud, 63, 32); 1977128Sgblack@eecs.umich.edu ''' 1987128Sgblack@eecs.umich.edu if writeback: 1997128Sgblack@eecs.umich.edu accCode += "Base = Base %s;\n" % offset 2007132Sgblack@eecs.umich.edu base = buildMemBase("MemoryReg", post, writeback) 2017128Sgblack@eecs.umich.edu 2027128Sgblack@eecs.umich.edu emitLoad(name, Name, False, eaCode, accCode, [], [], base) 2037128Sgblack@eecs.umich.edu 2047119Sgblack@eecs.umich.edu def buildLoads(mnem, size=4, sign=False, user=False): 2057119Sgblack@eecs.umich.edu buildImmLoad(mnem, True, True, True, size, sign, user) 2067119Sgblack@eecs.umich.edu buildRegLoad(mnem, True, True, True, size, sign, user) 2077119Sgblack@eecs.umich.edu buildImmLoad(mnem, True, False, True, size, sign, user) 2087119Sgblack@eecs.umich.edu buildRegLoad(mnem, True, False, True, size, sign, user) 2097119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, True, True, size, sign, user) 2107119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, True, True, size, sign, user) 2117119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, False, True, size, sign, user) 2127119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, False, True, size, sign, user) 2137119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, True, False, size, sign, user) 2147119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, True, False, size, sign, user) 2157119Sgblack@eecs.umich.edu buildImmLoad(mnem, False, False, False, size, sign, user) 2167119Sgblack@eecs.umich.edu buildRegLoad(mnem, False, False, False, size, sign, user) 2177119Sgblack@eecs.umich.edu 2187128Sgblack@eecs.umich.edu def buildDoubleLoads(mnem): 2197128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, True, True, True) 2207128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, True, True, True) 2217128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, True, False, True) 2227128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, True, False, True) 2237128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, True, True) 2247128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, True, True) 2257128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, True) 2267128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, False, True) 2277128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, True, False) 2287128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, True, False) 2297128Sgblack@eecs.umich.edu buildDoubleImmLoad(mnem, False, False, False) 2307128Sgblack@eecs.umich.edu buildDoubleRegLoad(mnem, False, False, False) 2317128Sgblack@eecs.umich.edu 2327192Sgblack@eecs.umich.edu def buildPrefetches(mnem): 2337192Sgblack@eecs.umich.edu buildRegLoad(mnem, False, False, False, size=1, prefetch=True) 2347192Sgblack@eecs.umich.edu buildImmLoad(mnem, False, False, False, size=1, prefetch=True) 2357192Sgblack@eecs.umich.edu buildRegLoad(mnem, False, True, False, size=1, prefetch=True) 2367192Sgblack@eecs.umich.edu buildImmLoad(mnem, False, True, False, size=1, prefetch=True) 2377192Sgblack@eecs.umich.edu 2387119Sgblack@eecs.umich.edu buildLoads("ldr") 2397119Sgblack@eecs.umich.edu buildLoads("ldrt", user=True) 2407119Sgblack@eecs.umich.edu buildLoads("ldrb", size=1) 2417119Sgblack@eecs.umich.edu buildLoads("ldrbt", size=1, user=True) 2427119Sgblack@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 2437119Sgblack@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 2447119Sgblack@eecs.umich.edu buildLoads("ldrh", size=2) 2457119Sgblack@eecs.umich.edu buildLoads("ldrht", size=2, user=True) 2467119Sgblack@eecs.umich.edu buildLoads("hdrsh", size=2, sign=True) 2477119Sgblack@eecs.umich.edu buildLoads("ldrsht", size=2, sign=True, user=True) 2487128Sgblack@eecs.umich.edu 2497128Sgblack@eecs.umich.edu buildDoubleLoads("ldrd") 2507192Sgblack@eecs.umich.edu 2517192Sgblack@eecs.umich.edu buildPrefetches("pld") 2527192Sgblack@eecs.umich.edu buildPrefetches("pldw") 2537192Sgblack@eecs.umich.edu buildPrefetches("pli") 2547244Sgblack@eecs.umich.edu 2557244Sgblack@eecs.umich.edu buildImmLoad("ldrex", False, True, False, size=4, ldrex=True) 2567244Sgblack@eecs.umich.edu buildImmLoad("ldrexh", False, True, False, size=2, ldrex=True) 2577244Sgblack@eecs.umich.edu buildImmLoad("ldrexb", False, True, False, size=1, ldrex=True) 2587244Sgblack@eecs.umich.edu buildDoubleImmLoad("ldrexd", False, True, False, ldrex=True) 2597119Sgblack@eecs.umich.edu}}; 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