ldr.isa revision 10037
17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 310037SARM gem5 Developers// Copyright (c) 2010-2011 ARM Limited 47119Sgblack@eecs.umich.edu// All rights reserved 57119Sgblack@eecs.umich.edu// 67119Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77119Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87119Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97119Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107119Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117119Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127119Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137119Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147119Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247119Sgblack@eecs.umich.edu// this software without specific prior written permission. 257119Sgblack@eecs.umich.edu// 267119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377119Sgblack@eecs.umich.edu// 387119Sgblack@eecs.umich.edu// Authors: Gabe Black 397119Sgblack@eecs.umich.edu 407119Sgblack@eecs.umich.edulet {{ 4110037SARM gem5 Developers import math 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu header_output = "" 447119Sgblack@eecs.umich.edu decoder_output = "" 457119Sgblack@eecs.umich.edu exec_output = "" 467119Sgblack@eecs.umich.edu 477590Sgblack@eecs.umich.edu class LoadInst(LoadStoreInst): 487590Sgblack@eecs.umich.edu execBase = 'Load' 497119Sgblack@eecs.umich.edu 507590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback, 517590Sgblack@eecs.umich.edu size=4, sign=False, user=False, flavor="normal"): 527590Sgblack@eecs.umich.edu super(LoadInst, self).__init__() 537590Sgblack@eecs.umich.edu 547590Sgblack@eecs.umich.edu self.name = mnem 557590Sgblack@eecs.umich.edu self.post = post 567590Sgblack@eecs.umich.edu self.add = add 577590Sgblack@eecs.umich.edu self.writeback = writeback 587590Sgblack@eecs.umich.edu self.size = size 597590Sgblack@eecs.umich.edu self.sign = sign 607590Sgblack@eecs.umich.edu self.user = user 617590Sgblack@eecs.umich.edu self.flavor = flavor 628203SAli.Saidi@ARM.com self.rasPop = False 637590Sgblack@eecs.umich.edu 647590Sgblack@eecs.umich.edu if self.add: 657590Sgblack@eecs.umich.edu self.op = " +" 667590Sgblack@eecs.umich.edu else: 677590Sgblack@eecs.umich.edu self.op = " -" 687590Sgblack@eecs.umich.edu 697590Sgblack@eecs.umich.edu self.memFlags = ["ArmISA::TLB::MustBeOne"] 707590Sgblack@eecs.umich.edu self.codeBlobs = {"postacc_code" : ""} 717590Sgblack@eecs.umich.edu 728140SMatt.Horsnell@arm.com def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None): 737590Sgblack@eecs.umich.edu 747590Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 757590Sgblack@eecs.umich.edu 767590Sgblack@eecs.umich.edu codeBlobs = self.codeBlobs 777590Sgblack@eecs.umich.edu codeBlobs["predicate_test"] = pickPredicate(codeBlobs) 787590Sgblack@eecs.umich.edu (newHeader, 797590Sgblack@eecs.umich.edu newDecoder, 807590Sgblack@eecs.umich.edu newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, 818140SMatt.Horsnell@arm.com self.memFlags, instFlags, base, 8210037SARM gem5 Developers wbDecl, pcDecl, self.rasPop, 8310037SARM gem5 Developers self.size, self.sign) 847590Sgblack@eecs.umich.edu 857590Sgblack@eecs.umich.edu header_output += newHeader 867590Sgblack@eecs.umich.edu decoder_output += newDecoder 877590Sgblack@eecs.umich.edu exec_output += newExec 887590Sgblack@eecs.umich.edu 897590Sgblack@eecs.umich.edu class RfeInst(LoadInst): 907590Sgblack@eecs.umich.edu decConstBase = 'Rfe' 917590Sgblack@eecs.umich.edu 927590Sgblack@eecs.umich.edu def __init__(self, mnem, post, add, writeback): 937590Sgblack@eecs.umich.edu super(RfeInst, self).__init__(mnem, post, add, writeback) 947590Sgblack@eecs.umich.edu self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8) 957590Sgblack@eecs.umich.edu 967590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AlignWord") 977590Sgblack@eecs.umich.edu 987590Sgblack@eecs.umich.edu def emit(self): 997590Sgblack@eecs.umich.edu offset = 0 1007590Sgblack@eecs.umich.edu if self.post != self.add: 1017590Sgblack@eecs.umich.edu offset += 4 1027590Sgblack@eecs.umich.edu if not self.add: 1037590Sgblack@eecs.umich.edu offset -= 8 1047590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset 1057590Sgblack@eecs.umich.edu 1067590Sgblack@eecs.umich.edu wbDiff = -8 1077590Sgblack@eecs.umich.edu if self.add: 1087590Sgblack@eecs.umich.edu wbDiff = 8 1097590Sgblack@eecs.umich.edu accCode = ''' 1107590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 1118303SAli.Saidi@ARM.com cpsr.nz = CondCodesNZ; 1128303SAli.Saidi@ARM.com cpsr.c = CondCodesC; 1138303SAli.Saidi@ARM.com cpsr.v = CondCodesV; 1148303SAli.Saidi@ARM.com cpsr.ge = CondCodesGE; 1158303SAli.Saidi@ARM.com URc = cpsr; 1168588Sgblack@eecs.umich.edu URa = cSwap<uint32_t>(Mem_ud, cpsr.e); 1178588Sgblack@eecs.umich.edu URb = cSwap<uint32_t>(Mem_ud >> 32, cpsr.e); 1187590Sgblack@eecs.umich.edu ''' 1197590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 1207590Sgblack@eecs.umich.edu 1217646Sgene.wu@arm.com wbDecl = None 1228140SMatt.Horsnell@arm.com pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);" 1238140SMatt.Horsnell@arm.com 1247646Sgene.wu@arm.com if self.writeback: 1257646Sgene.wu@arm.com wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff 1268140SMatt.Horsnell@arm.com self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"], pcDecl) 1277590Sgblack@eecs.umich.edu 1287590Sgblack@eecs.umich.edu class LoadImmInst(LoadInst): 1297590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1307590Sgblack@eecs.umich.edu super(LoadImmInst, self).__init__(*args, **kargs) 1317590Sgblack@eecs.umich.edu self.offset = self.op + " imm" 1327590Sgblack@eecs.umich.edu 1337646Sgene.wu@arm.com if self.add: 1347646Sgene.wu@arm.com self.wbDecl = "MicroAddiUop(machInst, base, base, imm);" 1357646Sgene.wu@arm.com else: 1367646Sgene.wu@arm.com self.wbDecl = "MicroSubiUop(machInst, base, base, imm);" 1377646Sgene.wu@arm.com 1388203SAli.Saidi@ARM.com if self.add and self.post and self.writeback and not self.sign and \ 1398203SAli.Saidi@ARM.com not self.user and self.size == 4: 1408203SAli.Saidi@ARM.com self.rasPop = True 1418203SAli.Saidi@ARM.com 1427590Sgblack@eecs.umich.edu class LoadRegInst(LoadInst): 1437590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1447590Sgblack@eecs.umich.edu super(LoadRegInst, self).__init__(*args, **kargs) 1457590Sgblack@eecs.umich.edu self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ 1468304SAli.Saidi@ARM.com " shiftType, OptShiftRmCondCodesC)" 1477646Sgene.wu@arm.com if self.add: 1487646Sgene.wu@arm.com self.wbDecl = ''' 1497646Sgene.wu@arm.com MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 1507646Sgene.wu@arm.com ''' 1517646Sgene.wu@arm.com else: 1527646Sgene.wu@arm.com self.wbDecl = ''' 1537646Sgene.wu@arm.com MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); 1547646Sgene.wu@arm.com ''' 1557590Sgblack@eecs.umich.edu 1567590Sgblack@eecs.umich.edu class LoadSingle(LoadInst): 1577590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 1587590Sgblack@eecs.umich.edu super(LoadSingle, self).__init__(*args, **kargs) 1597590Sgblack@eecs.umich.edu 1607590Sgblack@eecs.umich.edu # Build the default class name 1617590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback, 1627590Sgblack@eecs.umich.edu self.size, self.sign, self.user) 1637590Sgblack@eecs.umich.edu 1647590Sgblack@eecs.umich.edu # Add memory request flags where necessary 16510037SARM gem5 Developers self.memFlags.append("%d" % int(math.log(self.size, 2))) 1667590Sgblack@eecs.umich.edu if self.user: 1677590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::UserMode") 1687590Sgblack@eecs.umich.edu 1697725SAli.Saidi@ARM.com self.instFlags = [] 1707725SAli.Saidi@ARM.com if self.flavor == "dprefetch": 1717590Sgblack@eecs.umich.edu self.memFlags.append("Request::PREFETCH") 1727725SAli.Saidi@ARM.com self.instFlags = ['IsDataPrefetch'] 1737725SAli.Saidi@ARM.com elif self.flavor == "iprefetch": 1747725SAli.Saidi@ARM.com self.memFlags.append("Request::PREFETCH") 1757725SAli.Saidi@ARM.com self.instFlags = ['IsInstPrefetch'] 1767590Sgblack@eecs.umich.edu elif self.flavor == "exclusive": 1777590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 1787590Sgblack@eecs.umich.edu elif self.flavor == "normal": 1797590Sgblack@eecs.umich.edu self.memFlags.append("ArmISA::TLB::AllowUnaligned") 1807590Sgblack@eecs.umich.edu 1817590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of loads 1827590Sgblack@eecs.umich.edu if self.flavor != "normal": 1837590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 1847590Sgblack@eecs.umich.edu 1857590Sgblack@eecs.umich.edu def emit(self): 1867590Sgblack@eecs.umich.edu # Address compuation code 1877590Sgblack@eecs.umich.edu eaCode = "EA = Base" 1887590Sgblack@eecs.umich.edu if not self.post: 1897590Sgblack@eecs.umich.edu eaCode += self.offset 1907590Sgblack@eecs.umich.edu eaCode += ";" 1917644Sali.saidi@arm.com 1927644Sali.saidi@arm.com if self.flavor == "fp": 1937644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 1947644Sali.saidi@arm.com 1957590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 1967590Sgblack@eecs.umich.edu 1977590Sgblack@eecs.umich.edu # Code that actually handles the access 1987725SAli.Saidi@ARM.com if self.flavor == "dprefetch" or self.flavor == "iprefetch": 1997590Sgblack@eecs.umich.edu accCode = 'uint64_t temp = Mem%s; temp = temp;' 2007590Sgblack@eecs.umich.edu elif self.flavor == "fp": 2018588Sgblack@eecs.umich.edu accCode = "FpDest_uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" 2027590Sgblack@eecs.umich.edu else: 2037590Sgblack@eecs.umich.edu accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" 2047590Sgblack@eecs.umich.edu accCode = accCode % buildMemSuffix(self.sign, self.size) 2057590Sgblack@eecs.umich.edu 2067590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2077590Sgblack@eecs.umich.edu 2087590Sgblack@eecs.umich.edu # Push it out to the output files 2097590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2107646Sgene.wu@arm.com wbDecl = None 2117646Sgene.wu@arm.com if self.writeback: 2127646Sgene.wu@arm.com wbDecl = self.wbDecl 2137725SAli.Saidi@ARM.com self.emitHelper(base, wbDecl, self.instFlags) 2147590Sgblack@eecs.umich.edu 2157590Sgblack@eecs.umich.edu def loadImmClassName(post, add, writeback, size=4, sign=False, user=False): 2167590Sgblack@eecs.umich.edu return memClassName("LOAD_IMM", post, add, writeback, size, sign, user) 2177590Sgblack@eecs.umich.edu 2187590Sgblack@eecs.umich.edu class LoadImm(LoadImmInst, LoadSingle): 2197646Sgene.wu@arm.com decConstBase = 'LoadImm' 2207590Sgblack@eecs.umich.edu basePrefix = 'MemoryImm' 2217590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadImmClassName) 2227590Sgblack@eecs.umich.edu 2237590Sgblack@eecs.umich.edu def loadRegClassName(post, add, writeback, size=4, sign=False, user=False): 2247590Sgblack@eecs.umich.edu return memClassName("LOAD_REG", post, add, writeback, size, sign, user) 2257590Sgblack@eecs.umich.edu 2267590Sgblack@eecs.umich.edu class LoadReg(LoadRegInst, LoadSingle): 2277646Sgene.wu@arm.com decConstBase = 'LoadReg' 2287590Sgblack@eecs.umich.edu basePrefix = 'MemoryReg' 2297590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadRegClassName) 2307590Sgblack@eecs.umich.edu 2317590Sgblack@eecs.umich.edu class LoadDouble(LoadInst): 2327590Sgblack@eecs.umich.edu def __init__(self, *args, **kargs): 2337590Sgblack@eecs.umich.edu super(LoadDouble, self).__init__(*args, **kargs) 2347590Sgblack@eecs.umich.edu 2357590Sgblack@eecs.umich.edu # Build the default class name 2367590Sgblack@eecs.umich.edu self.Name = self.nameFunc(self.post, self.add, self.writeback) 2377590Sgblack@eecs.umich.edu 2387590Sgblack@eecs.umich.edu # Add memory request flags where necessary 2397590Sgblack@eecs.umich.edu if self.flavor == "exclusive": 2407590Sgblack@eecs.umich.edu self.memFlags.append("Request::LLSC") 2417593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignDoubleWord") 2427593SAli.Saidi@arm.com else: 2437593SAli.Saidi@arm.com self.memFlags.append("ArmISA::TLB::AlignWord") 2447590Sgblack@eecs.umich.edu 2457590Sgblack@eecs.umich.edu # Disambiguate the class name for different flavors of loads 2467590Sgblack@eecs.umich.edu if self.flavor != "normal": 2477590Sgblack@eecs.umich.edu self.Name = "%s_%s" % (self.name.upper(), self.Name) 2487590Sgblack@eecs.umich.edu 2497590Sgblack@eecs.umich.edu def emit(self): 2507590Sgblack@eecs.umich.edu # Address computation code 2517590Sgblack@eecs.umich.edu eaCode = "EA = Base" 2527590Sgblack@eecs.umich.edu if not self.post: 2537590Sgblack@eecs.umich.edu eaCode += self.offset 2547590Sgblack@eecs.umich.edu eaCode += ";" 2557644Sali.saidi@arm.com 2567644Sali.saidi@arm.com if self.flavor == "fp": 2577644Sali.saidi@arm.com eaCode += vfpEnabledCheckCode 2587644Sali.saidi@arm.com 2597590Sgblack@eecs.umich.edu self.codeBlobs["ea_code"] = eaCode 2607590Sgblack@eecs.umich.edu 2617590Sgblack@eecs.umich.edu # Code that actually handles the access 2627590Sgblack@eecs.umich.edu if self.flavor != "fp": 2637590Sgblack@eecs.umich.edu accCode = ''' 2647590Sgblack@eecs.umich.edu CPSR cpsr = Cpsr; 2658588Sgblack@eecs.umich.edu Dest = cSwap<uint32_t>(Mem_ud, cpsr.e); 2668588Sgblack@eecs.umich.edu Dest2 = cSwap<uint32_t>(Mem_ud >> 32, cpsr.e); 2677590Sgblack@eecs.umich.edu ''' 2687590Sgblack@eecs.umich.edu else: 2697590Sgblack@eecs.umich.edu accCode = ''' 2708588Sgblack@eecs.umich.edu uint64_t swappedMem = cSwap(Mem_ud, ((CPSR)Cpsr).e); 2718588Sgblack@eecs.umich.edu FpDest_uw = (uint32_t)swappedMem; 2728588Sgblack@eecs.umich.edu FpDest2_uw = (uint32_t)(swappedMem >> 32); 2737590Sgblack@eecs.umich.edu ''' 2747590Sgblack@eecs.umich.edu 2757590Sgblack@eecs.umich.edu self.codeBlobs["memacc_code"] = accCode 2767590Sgblack@eecs.umich.edu 2777590Sgblack@eecs.umich.edu # Push it out to the output files 2787590Sgblack@eecs.umich.edu base = buildMemBase(self.basePrefix, self.post, self.writeback) 2797646Sgene.wu@arm.com wbDecl = None 2807646Sgene.wu@arm.com if self.writeback: 2817646Sgene.wu@arm.com wbDecl = self.wbDecl 2827646Sgene.wu@arm.com self.emitHelper(base, wbDecl) 2837119Sgblack@eecs.umich.edu 2847128Sgblack@eecs.umich.edu def loadDoubleImmClassName(post, add, writeback): 2857128Sgblack@eecs.umich.edu return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False) 2867128Sgblack@eecs.umich.edu 2877590Sgblack@eecs.umich.edu class LoadDoubleImm(LoadImmInst, LoadDouble): 2887590Sgblack@eecs.umich.edu decConstBase = 'LoadStoreDImm' 2897590Sgblack@eecs.umich.edu basePrefix = 'MemoryDImm' 2907590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadDoubleImmClassName) 2917590Sgblack@eecs.umich.edu 2927128Sgblack@eecs.umich.edu def loadDoubleRegClassName(post, add, writeback): 2937128Sgblack@eecs.umich.edu return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) 2947128Sgblack@eecs.umich.edu 2957590Sgblack@eecs.umich.edu class LoadDoubleReg(LoadRegInst, LoadDouble): 2967646Sgene.wu@arm.com decConstBase = 'LoadDReg' 2977590Sgblack@eecs.umich.edu basePrefix = 'MemoryDReg' 2987590Sgblack@eecs.umich.edu nameFunc = staticmethod(loadDoubleRegClassName) 2997128Sgblack@eecs.umich.edu 3007119Sgblack@eecs.umich.edu def buildLoads(mnem, size=4, sign=False, user=False): 3017590Sgblack@eecs.umich.edu LoadImm(mnem, True, True, True, size, sign, user).emit() 3027590Sgblack@eecs.umich.edu LoadReg(mnem, True, True, True, size, sign, user).emit() 3037590Sgblack@eecs.umich.edu LoadImm(mnem, True, False, True, size, sign, user).emit() 3047590Sgblack@eecs.umich.edu LoadReg(mnem, True, False, True, size, sign, user).emit() 3057590Sgblack@eecs.umich.edu LoadImm(mnem, False, True, True, size, sign, user).emit() 3067590Sgblack@eecs.umich.edu LoadReg(mnem, False, True, True, size, sign, user).emit() 3077590Sgblack@eecs.umich.edu LoadImm(mnem, False, False, True, size, sign, user).emit() 3087590Sgblack@eecs.umich.edu LoadReg(mnem, False, False, True, size, sign, user).emit() 3097590Sgblack@eecs.umich.edu LoadImm(mnem, False, True, False, size, sign, user).emit() 3107590Sgblack@eecs.umich.edu LoadReg(mnem, False, True, False, size, sign, user).emit() 3117590Sgblack@eecs.umich.edu LoadImm(mnem, False, False, False, size, sign, user).emit() 3127590Sgblack@eecs.umich.edu LoadReg(mnem, False, False, False, size, sign, user).emit() 3137119Sgblack@eecs.umich.edu 3147128Sgblack@eecs.umich.edu def buildDoubleLoads(mnem): 3157590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, True, True, True).emit() 3167590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, True, True, True).emit() 3177590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, True, False, True).emit() 3187590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, True, False, True).emit() 3197590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, True, True).emit() 3207590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, True, True).emit() 3217590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, False, True).emit() 3227590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, False, True).emit() 3237590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, True, False).emit() 3247590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, True, False).emit() 3257590Sgblack@eecs.umich.edu LoadDoubleImm(mnem, False, False, False).emit() 3267590Sgblack@eecs.umich.edu LoadDoubleReg(mnem, False, False, False).emit() 3277128Sgblack@eecs.umich.edu 3287292Sgblack@eecs.umich.edu def buildRfeLoads(mnem): 3297590Sgblack@eecs.umich.edu RfeInst(mnem, True, True, True).emit() 3307590Sgblack@eecs.umich.edu RfeInst(mnem, True, True, False).emit() 3317590Sgblack@eecs.umich.edu RfeInst(mnem, True, False, True).emit() 3327590Sgblack@eecs.umich.edu RfeInst(mnem, True, False, False).emit() 3337590Sgblack@eecs.umich.edu RfeInst(mnem, False, True, True).emit() 3347590Sgblack@eecs.umich.edu RfeInst(mnem, False, True, False).emit() 3357590Sgblack@eecs.umich.edu RfeInst(mnem, False, False, True).emit() 3367590Sgblack@eecs.umich.edu RfeInst(mnem, False, False, False).emit() 3377292Sgblack@eecs.umich.edu 3387725SAli.Saidi@ARM.com def buildPrefetches(mnem, type): 3397725SAli.Saidi@ARM.com LoadReg(mnem, False, False, False, size=1, flavor=type).emit() 3407725SAli.Saidi@ARM.com LoadImm(mnem, False, False, False, size=1, flavor=type).emit() 3417725SAli.Saidi@ARM.com LoadReg(mnem, False, True, False, size=1, flavor=type).emit() 3427725SAli.Saidi@ARM.com LoadImm(mnem, False, True, False, size=1, flavor=type).emit() 3437192Sgblack@eecs.umich.edu 3447119Sgblack@eecs.umich.edu buildLoads("ldr") 3457119Sgblack@eecs.umich.edu buildLoads("ldrt", user=True) 3467119Sgblack@eecs.umich.edu buildLoads("ldrb", size=1) 3477119Sgblack@eecs.umich.edu buildLoads("ldrbt", size=1, user=True) 3487119Sgblack@eecs.umich.edu buildLoads("ldrsb", size=1, sign=True) 3497119Sgblack@eecs.umich.edu buildLoads("ldrsbt", size=1, sign=True, user=True) 3507119Sgblack@eecs.umich.edu buildLoads("ldrh", size=2) 3517119Sgblack@eecs.umich.edu buildLoads("ldrht", size=2, user=True) 3527119Sgblack@eecs.umich.edu buildLoads("hdrsh", size=2, sign=True) 3537119Sgblack@eecs.umich.edu buildLoads("ldrsht", size=2, sign=True, user=True) 3547128Sgblack@eecs.umich.edu 3557128Sgblack@eecs.umich.edu buildDoubleLoads("ldrd") 3567192Sgblack@eecs.umich.edu 3577292Sgblack@eecs.umich.edu buildRfeLoads("rfe") 3587292Sgblack@eecs.umich.edu 3597725SAli.Saidi@ARM.com buildPrefetches("pld", "dprefetch") 3607725SAli.Saidi@ARM.com buildPrefetches("pldw", "dprefetch") 3617725SAli.Saidi@ARM.com buildPrefetches("pli", "iprefetch") 3627244Sgblack@eecs.umich.edu 3637590Sgblack@eecs.umich.edu LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() 3647590Sgblack@eecs.umich.edu LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() 3657590Sgblack@eecs.umich.edu LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit() 3667590Sgblack@eecs.umich.edu LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit() 3677336Sgblack@eecs.umich.edu 3687590Sgblack@eecs.umich.edu LoadImm("vldr", False, True, False, size=4, flavor="fp").emit() 3697590Sgblack@eecs.umich.edu LoadImm("vldr", False, False, False, size=4, flavor="fp").emit() 3707590Sgblack@eecs.umich.edu LoadDoubleImm("vldr", False, True, False, flavor="fp").emit() 3717590Sgblack@eecs.umich.edu LoadDoubleImm("vldr", False, False, False, flavor="fp").emit() 3727119Sgblack@eecs.umich.edu}}; 373