fp.isa revision 7380:baee640ca6a4
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40output header {{ 41 42template <class Micro> 43class VfpMacroRegRegOp : public VfpMacroOp 44{ 45 public: 46 VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 47 IntRegIndex _op1, bool _wide) : 48 VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide) 49 { 50 numMicroops = machInst.fpscrLen + 1; 51 assert(numMicroops > 1); 52 microOps = new StaticInstPtr[numMicroops]; 53 for (unsigned i = 0; i < numMicroops; i++) { 54 VfpMicroMode mode = VfpMicroop; 55 if (i == 0) 56 mode = VfpFirstMicroop; 57 else if (i == numMicroops - 1) 58 mode = VfpLastMicroop; 59 microOps[i] = new Micro(_machInst, _dest, _op1, mode); 60 nextIdxs(_dest, _op1); 61 } 62 } 63 64 %(BasicExecPanic)s 65}; 66 67template <class VfpOp> 68static StaticInstPtr 69decodeVfpRegRegOp(ExtMachInst machInst, 70 IntRegIndex dest, IntRegIndex op1, bool wide) 71{ 72 if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 73 return new VfpOp(machInst, dest, op1); 74 } else { 75 return new VfpMacroRegRegOp<VfpOp>(machInst, dest, op1, wide); 76 } 77} 78 79template <class Micro> 80class VfpMacroRegImmOp : public VfpMacroOp 81{ 82 public: 83 VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm, 84 bool _wide) : 85 VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide) 86 { 87 numMicroops = machInst.fpscrLen + 1; 88 microOps = new StaticInstPtr[numMicroops]; 89 for (unsigned i = 0; i < numMicroops; i++) { 90 VfpMicroMode mode = VfpMicroop; 91 if (i == 0) 92 mode = VfpFirstMicroop; 93 else if (i == numMicroops - 1) 94 mode = VfpLastMicroop; 95 microOps[i] = new Micro(_machInst, _dest, _imm, mode); 96 nextIdxs(_dest); 97 } 98 } 99 100 %(BasicExecPanic)s 101}; 102 103template <class VfpOp> 104static StaticInstPtr 105decodeVfpRegImmOp(ExtMachInst machInst, 106 IntRegIndex dest, uint64_t imm, bool wide) 107{ 108 if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 109 return new VfpOp(machInst, dest, imm); 110 } else { 111 return new VfpMacroRegImmOp<VfpOp>(machInst, dest, imm, wide); 112 } 113} 114 115template <class Micro> 116class VfpMacroRegRegImmOp : public VfpMacroOp 117{ 118 public: 119 VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, 120 IntRegIndex _op1, uint64_t _imm, bool _wide) : 121 VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide) 122 { 123 numMicroops = machInst.fpscrLen + 1; 124 microOps = new StaticInstPtr[numMicroops]; 125 for (unsigned i = 0; i < numMicroops; i++) { 126 VfpMicroMode mode = VfpMicroop; 127 if (i == 0) 128 mode = VfpFirstMicroop; 129 else if (i == numMicroops - 1) 130 mode = VfpLastMicroop; 131 microOps[i] = new Micro(_machInst, _dest, _op1, _imm, mode); 132 nextIdxs(_dest, _op1); 133 } 134 } 135 136 %(BasicExecPanic)s 137}; 138 139template <class VfpOp> 140static StaticInstPtr 141decodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest, 142 IntRegIndex op1, uint64_t imm, bool wide) 143{ 144 if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 145 return new VfpOp(machInst, dest, op1, imm); 146 } else { 147 return new VfpMacroRegRegImmOp<VfpOp>(machInst, dest, op1, imm, wide); 148 } 149} 150 151template <class Micro> 152class VfpMacroRegRegRegOp : public VfpMacroOp 153{ 154 public: 155 VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest, 156 IntRegIndex _op1, IntRegIndex _op2, bool _wide) : 157 VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide) 158 { 159 numMicroops = machInst.fpscrLen + 1; 160 microOps = new StaticInstPtr[numMicroops]; 161 for (unsigned i = 0; i < numMicroops; i++) { 162 VfpMicroMode mode = VfpMicroop; 163 if (i == 0) 164 mode = VfpFirstMicroop; 165 else if (i == numMicroops - 1) 166 mode = VfpLastMicroop; 167 microOps[i] = new Micro(_machInst, _dest, _op1, _op2, mode); 168 nextIdxs(_dest, _op1, _op2); 169 } 170 } 171 172 %(BasicExecPanic)s 173}; 174 175template <class VfpOp> 176static StaticInstPtr 177decodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest, 178 IntRegIndex op1, IntRegIndex op2, bool wide) 179{ 180 if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) { 181 return new VfpOp(machInst, dest, op1, op2); 182 } else { 183 return new VfpMacroRegRegRegOp<VfpOp>(machInst, dest, op1, op2, wide); 184 } 185} 186}}; 187 188let {{ 189 190 header_output = "" 191 decoder_output = "" 192 exec_output = "" 193 194 vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp", 195 { "code": "MiscDest = Op1;", 196 "predicate_test": predicateTest }, []) 197 header_output += VfpRegRegOpDeclare.subst(vmsrIop); 198 decoder_output += VfpRegRegOpConstructor.subst(vmsrIop); 199 exec_output += PredOpExecute.subst(vmsrIop); 200 201 vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp", 202 { "code": "Dest = MiscOp1;", 203 "predicate_test": predicateTest }, []) 204 header_output += VfpRegRegOpDeclare.subst(vmrsIop); 205 decoder_output += VfpRegRegOpConstructor.subst(vmrsIop); 206 exec_output += PredOpExecute.subst(vmrsIop); 207 208 vmovImmSCode = ''' 209 FpDest.uw = bits(imm, 31, 0); 210 ''' 211 vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp", 212 { "code": vmovImmSCode, 213 "predicate_test": predicateTest }, []) 214 header_output += VfpRegImmOpDeclare.subst(vmovImmSIop); 215 decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop); 216 exec_output += PredOpExecute.subst(vmovImmSIop); 217 218 vmovImmDCode = ''' 219 FpDestP0.uw = bits(imm, 31, 0); 220 FpDestP1.uw = bits(imm, 63, 32); 221 ''' 222 vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp", 223 { "code": vmovImmDCode, 224 "predicate_test": predicateTest }, []) 225 header_output += VfpRegImmOpDeclare.subst(vmovImmDIop); 226 decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop); 227 exec_output += PredOpExecute.subst(vmovImmDIop); 228 229 vmovImmQCode = ''' 230 FpDestP0.uw = bits(imm, 31, 0); 231 FpDestP1.uw = bits(imm, 63, 32); 232 FpDestP2.uw = bits(imm, 31, 0); 233 FpDestP3.uw = bits(imm, 63, 32); 234 ''' 235 vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp", 236 { "code": vmovImmQCode, 237 "predicate_test": predicateTest }, []) 238 header_output += VfpRegImmOpDeclare.subst(vmovImmQIop); 239 decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop); 240 exec_output += PredOpExecute.subst(vmovImmQIop); 241 242 vmovRegSCode = ''' 243 FpDest.uw = FpOp1.uw; 244 ''' 245 vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp", 246 { "code": vmovRegSCode, 247 "predicate_test": predicateTest }, []) 248 header_output += VfpRegRegOpDeclare.subst(vmovRegSIop); 249 decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop); 250 exec_output += PredOpExecute.subst(vmovRegSIop); 251 252 vmovRegDCode = ''' 253 FpDestP0.uw = FpOp1P0.uw; 254 FpDestP1.uw = FpOp1P1.uw; 255 ''' 256 vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp", 257 { "code": vmovRegDCode, 258 "predicate_test": predicateTest }, []) 259 header_output += VfpRegRegOpDeclare.subst(vmovRegDIop); 260 decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop); 261 exec_output += PredOpExecute.subst(vmovRegDIop); 262 263 vmovRegQCode = ''' 264 FpDestP0.uw = FpOp1P0.uw; 265 FpDestP1.uw = FpOp1P1.uw; 266 FpDestP2.uw = FpOp1P2.uw; 267 FpDestP3.uw = FpOp1P3.uw; 268 ''' 269 vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp", 270 { "code": vmovRegQCode, 271 "predicate_test": predicateTest }, []) 272 header_output += VfpRegRegOpDeclare.subst(vmovRegQIop); 273 decoder_output += VfpRegRegOpConstructor.subst(vmovRegQIop); 274 exec_output += PredOpExecute.subst(vmovRegQIop); 275 276 vmovCoreRegBCode = ''' 277 FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub); 278 ''' 279 vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp", 280 { "code": vmovCoreRegBCode, 281 "predicate_test": predicateTest }, []) 282 header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop); 283 decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop); 284 exec_output += PredOpExecute.subst(vmovCoreRegBIop); 285 286 vmovCoreRegHCode = ''' 287 FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh); 288 ''' 289 vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp", 290 { "code": vmovCoreRegHCode, 291 "predicate_test": predicateTest }, []) 292 header_output += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop); 293 decoder_output += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop); 294 exec_output += PredOpExecute.subst(vmovCoreRegHIop); 295 296 vmovCoreRegWCode = ''' 297 FpDest.uw = Op1.uw; 298 ''' 299 vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp", 300 { "code": vmovCoreRegWCode, 301 "predicate_test": predicateTest }, []) 302 header_output += VfpRegRegOpDeclare.subst(vmovCoreRegWIop); 303 decoder_output += VfpRegRegOpConstructor.subst(vmovCoreRegWIop); 304 exec_output += PredOpExecute.subst(vmovCoreRegWIop); 305 306 vmovRegCoreUBCode = ''' 307 Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7); 308 ''' 309 vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp", 310 { "code": vmovRegCoreUBCode, 311 "predicate_test": predicateTest }, []) 312 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop); 313 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop); 314 exec_output += PredOpExecute.subst(vmovRegCoreUBIop); 315 316 vmovRegCoreUHCode = ''' 317 Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15); 318 ''' 319 vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp", 320 { "code": vmovRegCoreUHCode, 321 "predicate_test": predicateTest }, []) 322 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop); 323 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop); 324 exec_output += PredOpExecute.subst(vmovRegCoreUHIop); 325 326 vmovRegCoreSBCode = ''' 327 Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7)); 328 ''' 329 vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp", 330 { "code": vmovRegCoreSBCode, 331 "predicate_test": predicateTest }, []) 332 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop); 333 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop); 334 exec_output += PredOpExecute.subst(vmovRegCoreSBIop); 335 336 vmovRegCoreSHCode = ''' 337 Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15)); 338 ''' 339 vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp", 340 { "code": vmovRegCoreSHCode, 341 "predicate_test": predicateTest }, []) 342 header_output += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop); 343 decoder_output += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop); 344 exec_output += PredOpExecute.subst(vmovRegCoreSHIop); 345 346 vmovRegCoreWCode = ''' 347 Dest = FpOp1.uw; 348 ''' 349 vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp", 350 { "code": vmovRegCoreWCode, 351 "predicate_test": predicateTest }, []) 352 header_output += VfpRegRegOpDeclare.subst(vmovRegCoreWIop); 353 decoder_output += VfpRegRegOpConstructor.subst(vmovRegCoreWIop); 354 exec_output += PredOpExecute.subst(vmovRegCoreWIop); 355 356 vmov2Reg2CoreCode = ''' 357 FpDestP0.uw = Op1.uw; 358 FpDestP1.uw = Op2.uw; 359 ''' 360 vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp", 361 { "code": vmov2Reg2CoreCode, 362 "predicate_test": predicateTest }, []) 363 header_output += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop); 364 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop); 365 exec_output += PredOpExecute.subst(vmov2Reg2CoreIop); 366 367 vmov2Core2RegCode = ''' 368 Dest.uw = FpOp2P0.uw; 369 Op1.uw = FpOp2P1.uw; 370 ''' 371 vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp", 372 { "code": vmov2Core2RegCode, 373 "predicate_test": predicateTest }, []) 374 header_output += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop); 375 decoder_output += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop); 376 exec_output += PredOpExecute.subst(vmov2Core2RegIop); 377 378 vmulSCode = ''' 379 VfpSavedState state = prepVfpFpscr(Fpscr); 380 FpDest = FpOp1 * FpOp2; 381 Fpscr = setVfpFpscr(Fpscr, state); 382 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 383 FpDest = NAN; 384 } 385 ''' 386 vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp", 387 { "code": vmulSCode, 388 "predicate_test": predicateTest }, []) 389 header_output += VfpRegRegRegOpDeclare.subst(vmulSIop); 390 decoder_output += VfpRegRegRegOpConstructor.subst(vmulSIop); 391 exec_output += PredOpExecute.subst(vmulSIop); 392 393 vmulDCode = ''' 394 IntDoubleUnion cOp1, cOp2, cDest; 395 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 396 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 397 VfpSavedState state = prepVfpFpscr(Fpscr); 398 cDest.fp = cOp1.fp * cOp2.fp; 399 Fpscr = setVfpFpscr(Fpscr, state); 400 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 401 (isinf(cOp2.fp) && cOp1.fp == 0)) { 402 cDest.fp = NAN; 403 } 404 FpDestP0.uw = cDest.bits; 405 FpDestP1.uw = cDest.bits >> 32; 406 ''' 407 vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp", 408 { "code": vmulDCode, 409 "predicate_test": predicateTest }, []) 410 header_output += VfpRegRegRegOpDeclare.subst(vmulDIop); 411 decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop); 412 exec_output += PredOpExecute.subst(vmulDIop); 413 414 vnegSCode = ''' 415 FpDest = -FpOp1; 416 ''' 417 vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp", 418 { "code": vnegSCode, 419 "predicate_test": predicateTest }, []) 420 header_output += VfpRegRegOpDeclare.subst(vnegSIop); 421 decoder_output += VfpRegRegOpConstructor.subst(vnegSIop); 422 exec_output += PredOpExecute.subst(vnegSIop); 423 424 vnegDCode = ''' 425 IntDoubleUnion cOp1, cDest; 426 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 427 cDest.fp = -cOp1.fp; 428 FpDestP0.uw = cDest.bits; 429 FpDestP1.uw = cDest.bits >> 32; 430 ''' 431 vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp", 432 { "code": vnegDCode, 433 "predicate_test": predicateTest }, []) 434 header_output += VfpRegRegOpDeclare.subst(vnegDIop); 435 decoder_output += VfpRegRegOpConstructor.subst(vnegDIop); 436 exec_output += PredOpExecute.subst(vnegDIop); 437 438 vabsSCode = ''' 439 FpDest = fabsf(FpOp1); 440 ''' 441 vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp", 442 { "code": vabsSCode, 443 "predicate_test": predicateTest }, []) 444 header_output += VfpRegRegOpDeclare.subst(vabsSIop); 445 decoder_output += VfpRegRegOpConstructor.subst(vabsSIop); 446 exec_output += PredOpExecute.subst(vabsSIop); 447 448 vabsDCode = ''' 449 IntDoubleUnion cOp1, cDest; 450 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 451 cDest.fp = fabs(cOp1.fp); 452 FpDestP0.uw = cDest.bits; 453 FpDestP1.uw = cDest.bits >> 32; 454 ''' 455 vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp", 456 { "code": vabsDCode, 457 "predicate_test": predicateTest }, []) 458 header_output += VfpRegRegOpDeclare.subst(vabsDIop); 459 decoder_output += VfpRegRegOpConstructor.subst(vabsDIop); 460 exec_output += PredOpExecute.subst(vabsDIop); 461 462 vaddSCode = ''' 463 VfpSavedState state = prepVfpFpscr(Fpscr); 464 FpDest = FpOp1 + FpOp2; 465 Fpscr = setVfpFpscr(Fpscr, state); 466 ''' 467 vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp", 468 { "code": vaddSCode, 469 "predicate_test": predicateTest }, []) 470 header_output += VfpRegRegRegOpDeclare.subst(vaddSIop); 471 decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop); 472 exec_output += PredOpExecute.subst(vaddSIop); 473 474 vaddDCode = ''' 475 IntDoubleUnion cOp1, cOp2, cDest; 476 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 477 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 478 VfpSavedState state = prepVfpFpscr(Fpscr); 479 cDest.fp = cOp1.fp + cOp2.fp; 480 Fpscr = setVfpFpscr(Fpscr, state); 481 FpDestP0.uw = cDest.bits; 482 FpDestP1.uw = cDest.bits >> 32; 483 ''' 484 vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp", 485 { "code": vaddDCode, 486 "predicate_test": predicateTest }, []) 487 header_output += VfpRegRegRegOpDeclare.subst(vaddDIop); 488 decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop); 489 exec_output += PredOpExecute.subst(vaddDIop); 490 491 vsubSCode = ''' 492 VfpSavedState state = prepVfpFpscr(Fpscr); 493 FpDest = FpOp1 - FpOp2; 494 Fpscr = setVfpFpscr(Fpscr, state) 495 ''' 496 vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp", 497 { "code": vsubSCode, 498 "predicate_test": predicateTest }, []) 499 header_output += VfpRegRegRegOpDeclare.subst(vsubSIop); 500 decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop); 501 exec_output += PredOpExecute.subst(vsubSIop); 502 503 vsubDCode = ''' 504 IntDoubleUnion cOp1, cOp2, cDest; 505 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 506 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 507 VfpSavedState state = prepVfpFpscr(Fpscr); 508 cDest.fp = cOp1.fp - cOp2.fp; 509 Fpscr = setVfpFpscr(Fpscr, state); 510 FpDestP0.uw = cDest.bits; 511 FpDestP1.uw = cDest.bits >> 32; 512 ''' 513 vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp", 514 { "code": vsubDCode, 515 "predicate_test": predicateTest }, []) 516 header_output += VfpRegRegRegOpDeclare.subst(vsubDIop); 517 decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop); 518 exec_output += PredOpExecute.subst(vsubDIop); 519 520 vdivSCode = ''' 521 VfpSavedState state = prepVfpFpscr(Fpscr); 522 FpDest = FpOp1 / FpOp2; 523 Fpscr = setVfpFpscr(Fpscr, state); 524 ''' 525 vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp", 526 { "code": vdivSCode, 527 "predicate_test": predicateTest }, []) 528 header_output += VfpRegRegRegOpDeclare.subst(vdivSIop); 529 decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop); 530 exec_output += PredOpExecute.subst(vdivSIop); 531 532 vdivDCode = ''' 533 IntDoubleUnion cOp1, cOp2, cDest; 534 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 535 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 536 VfpSavedState state = prepVfpFpscr(Fpscr); 537 cDest.fp = cOp1.fp / cOp2.fp; 538 Fpscr = setVfpFpscr(Fpscr, state); 539 FpDestP0.uw = cDest.bits; 540 FpDestP1.uw = cDest.bits >> 32; 541 ''' 542 vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp", 543 { "code": vdivDCode, 544 "predicate_test": predicateTest }, []) 545 header_output += VfpRegRegRegOpDeclare.subst(vdivDIop); 546 decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop); 547 exec_output += PredOpExecute.subst(vdivDIop); 548 549 vsqrtSCode = ''' 550 VfpSavedState state = prepVfpFpscr(Fpscr); 551 FpDest = sqrtf(FpOp1); 552 Fpscr = setVfpFpscr(Fpscr, state); 553 if (FpOp1 < 0) { 554 FpDest = NAN; 555 } 556 ''' 557 vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp", 558 { "code": vsqrtSCode, 559 "predicate_test": predicateTest }, []) 560 header_output += VfpRegRegOpDeclare.subst(vsqrtSIop); 561 decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop); 562 exec_output += PredOpExecute.subst(vsqrtSIop); 563 564 vsqrtDCode = ''' 565 IntDoubleUnion cOp1, cDest; 566 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 567 VfpSavedState state = prepVfpFpscr(Fpscr); 568 cDest.fp = sqrt(cOp1.fp); 569 Fpscr = setVfpFpscr(Fpscr, state); 570 if (cOp1.fp < 0) { 571 cDest.fp = NAN; 572 } 573 FpDestP0.uw = cDest.bits; 574 FpDestP1.uw = cDest.bits >> 32; 575 ''' 576 vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp", 577 { "code": vsqrtDCode, 578 "predicate_test": predicateTest }, []) 579 header_output += VfpRegRegOpDeclare.subst(vsqrtDIop); 580 decoder_output += VfpRegRegOpConstructor.subst(vsqrtDIop); 581 exec_output += PredOpExecute.subst(vsqrtDIop); 582 583 vmlaSCode = ''' 584 VfpSavedState state = prepVfpFpscr(Fpscr); 585 float mid = FpOp1 * FpOp2; 586 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 587 mid = NAN; 588 } 589 FpDest = FpDest + mid; 590 Fpscr = setVfpFpscr(Fpscr, state); 591 ''' 592 vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp", 593 { "code": vmlaSCode, 594 "predicate_test": predicateTest }, []) 595 header_output += VfpRegRegRegOpDeclare.subst(vmlaSIop); 596 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaSIop); 597 exec_output += PredOpExecute.subst(vmlaSIop); 598 599 vmlaDCode = ''' 600 IntDoubleUnion cOp1, cOp2, cDest; 601 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 602 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 603 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 604 VfpSavedState state = prepVfpFpscr(Fpscr); 605 double mid = cOp1.fp * cOp2.fp; 606 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 607 (isinf(cOp2.fp) && cOp1.fp == 0)) { 608 mid = NAN; 609 } 610 cDest.fp = cDest.fp + mid; 611 Fpscr = setVfpFpscr(Fpscr, state); 612 FpDestP0.uw = cDest.bits; 613 FpDestP1.uw = cDest.bits >> 32; 614 ''' 615 vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp", 616 { "code": vmlaDCode, 617 "predicate_test": predicateTest }, []) 618 header_output += VfpRegRegRegOpDeclare.subst(vmlaDIop); 619 decoder_output += VfpRegRegRegOpConstructor.subst(vmlaDIop); 620 exec_output += PredOpExecute.subst(vmlaDIop); 621 622 vmlsSCode = ''' 623 VfpSavedState state = prepVfpFpscr(Fpscr); 624 float mid = FpOp1 * FpOp2; 625 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 626 mid = NAN; 627 } 628 FpDest = FpDest - mid; 629 Fpscr = setVfpFpscr(Fpscr, state); 630 ''' 631 vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp", 632 { "code": vmlsSCode, 633 "predicate_test": predicateTest }, []) 634 header_output += VfpRegRegRegOpDeclare.subst(vmlsSIop); 635 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsSIop); 636 exec_output += PredOpExecute.subst(vmlsSIop); 637 638 vmlsDCode = ''' 639 IntDoubleUnion cOp1, cOp2, cDest; 640 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 641 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 642 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 643 VfpSavedState state = prepVfpFpscr(Fpscr); 644 double mid = cOp1.fp * cOp2.fp; 645 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 646 (isinf(cOp2.fp) && cOp1.fp == 0)) { 647 mid = NAN; 648 } 649 cDest.fp = cDest.fp - mid; 650 Fpscr = setVfpFpscr(Fpscr, state); 651 FpDestP0.uw = cDest.bits; 652 FpDestP1.uw = cDest.bits >> 32; 653 ''' 654 vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp", 655 { "code": vmlsDCode, 656 "predicate_test": predicateTest }, []) 657 header_output += VfpRegRegRegOpDeclare.subst(vmlsDIop); 658 decoder_output += VfpRegRegRegOpConstructor.subst(vmlsDIop); 659 exec_output += PredOpExecute.subst(vmlsDIop); 660 661 vnmlaSCode = ''' 662 VfpSavedState state = prepVfpFpscr(Fpscr); 663 float mid = FpOp1 * FpOp2; 664 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 665 mid = NAN; 666 } 667 FpDest = -FpDest - mid; 668 Fpscr = setVfpFpscr(Fpscr, state); 669 ''' 670 vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp", 671 { "code": vnmlaSCode, 672 "predicate_test": predicateTest }, []) 673 header_output += VfpRegRegRegOpDeclare.subst(vnmlaSIop); 674 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaSIop); 675 exec_output += PredOpExecute.subst(vnmlaSIop); 676 677 vnmlaDCode = ''' 678 IntDoubleUnion cOp1, cOp2, cDest; 679 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 680 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 681 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 682 VfpSavedState state = prepVfpFpscr(Fpscr); 683 double mid = cOp1.fp * cOp2.fp; 684 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 685 (isinf(cOp2.fp) && cOp1.fp == 0)) { 686 mid = NAN; 687 } 688 cDest.fp = -cDest.fp - mid; 689 Fpscr = setVfpFpscr(Fpscr, state); 690 FpDestP0.uw = cDest.bits; 691 FpDestP1.uw = cDest.bits >> 32; 692 ''' 693 vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp", 694 { "code": vnmlaDCode, 695 "predicate_test": predicateTest }, []) 696 header_output += VfpRegRegRegOpDeclare.subst(vnmlaDIop); 697 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlaDIop); 698 exec_output += PredOpExecute.subst(vnmlaDIop); 699 700 vnmlsSCode = ''' 701 VfpSavedState state = prepVfpFpscr(Fpscr); 702 float mid = FpOp1 * FpOp2; 703 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 704 mid = NAN; 705 } 706 FpDest = -FpDest + mid; 707 Fpscr = setVfpFpscr(Fpscr, state); 708 ''' 709 vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp", 710 { "code": vnmlsSCode, 711 "predicate_test": predicateTest }, []) 712 header_output += VfpRegRegRegOpDeclare.subst(vnmlsSIop); 713 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsSIop); 714 exec_output += PredOpExecute.subst(vnmlsSIop); 715 716 vnmlsDCode = ''' 717 IntDoubleUnion cOp1, cOp2, cDest; 718 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 719 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 720 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 721 VfpSavedState state = prepVfpFpscr(Fpscr); 722 double mid = cOp1.fp * cOp2.fp; 723 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 724 (isinf(cOp2.fp) && cOp1.fp == 0)) { 725 mid = NAN; 726 } 727 cDest.fp = -cDest.fp + mid; 728 Fpscr = setVfpFpscr(Fpscr, state); 729 FpDestP0.uw = cDest.bits; 730 FpDestP1.uw = cDest.bits >> 32; 731 ''' 732 vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp", 733 { "code": vnmlsDCode, 734 "predicate_test": predicateTest }, []) 735 header_output += VfpRegRegRegOpDeclare.subst(vnmlsDIop); 736 decoder_output += VfpRegRegRegOpConstructor.subst(vnmlsDIop); 737 exec_output += PredOpExecute.subst(vnmlsDIop); 738 739 vnmulSCode = ''' 740 VfpSavedState state = prepVfpFpscr(Fpscr); 741 float mid = FpOp1 * FpOp2; 742 if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) { 743 mid = NAN; 744 } 745 FpDest = -mid; 746 Fpscr = setVfpFpscr(Fpscr, state); 747 ''' 748 vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp", 749 { "code": vnmulSCode, 750 "predicate_test": predicateTest }, []) 751 header_output += VfpRegRegRegOpDeclare.subst(vnmulSIop); 752 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulSIop); 753 exec_output += PredOpExecute.subst(vnmulSIop); 754 755 vnmulDCode = ''' 756 IntDoubleUnion cOp1, cOp2, cDest; 757 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 758 cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32)); 759 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 760 VfpSavedState state = prepVfpFpscr(Fpscr); 761 double mid = cOp1.fp * cOp2.fp; 762 if ((isinf(cOp1.fp) && cOp2.fp == 0) || 763 (isinf(cOp2.fp) && cOp1.fp == 0)) { 764 mid = NAN; 765 } 766 cDest.fp = -mid; 767 Fpscr = setVfpFpscr(Fpscr, state); 768 FpDestP0.uw = cDest.bits; 769 FpDestP1.uw = cDest.bits >> 32; 770 ''' 771 vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp", 772 { "code": vnmulDCode, 773 "predicate_test": predicateTest }, []) 774 header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop); 775 decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop); 776 exec_output += PredOpExecute.subst(vnmulDIop); 777 778 vcvtUIntFpSCode = ''' 779 VfpSavedState state = prepVfpFpscr(Fpscr); 780 FpDest = FpOp1.uw; 781 Fpscr = setVfpFpscr(Fpscr, state); 782 ''' 783 vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp", 784 { "code": vcvtUIntFpSCode, 785 "predicate_test": predicateTest }, []) 786 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop); 787 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop); 788 exec_output += PredOpExecute.subst(vcvtUIntFpSIop); 789 790 vcvtUIntFpDCode = ''' 791 IntDoubleUnion cDest; 792 VfpSavedState state = prepVfpFpscr(Fpscr); 793 cDest.fp = (uint64_t)FpOp1P0.uw; 794 Fpscr = setVfpFpscr(Fpscr, state); 795 FpDestP0.uw = cDest.bits; 796 FpDestP1.uw = cDest.bits >> 32; 797 ''' 798 vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp", 799 { "code": vcvtUIntFpDCode, 800 "predicate_test": predicateTest }, []) 801 header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop); 802 decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop); 803 exec_output += PredOpExecute.subst(vcvtUIntFpDIop); 804 805 vcvtSIntFpSCode = ''' 806 VfpSavedState state = prepVfpFpscr(Fpscr); 807 FpDest = FpOp1.sw; 808 Fpscr = setVfpFpscr(Fpscr, state); 809 ''' 810 vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp", 811 { "code": vcvtSIntFpSCode, 812 "predicate_test": predicateTest }, []) 813 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop); 814 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop); 815 exec_output += PredOpExecute.subst(vcvtSIntFpSIop); 816 817 vcvtSIntFpDCode = ''' 818 IntDoubleUnion cDest; 819 VfpSavedState state = prepVfpFpscr(Fpscr); 820 cDest.fp = FpOp1P0.sw; 821 Fpscr = setVfpFpscr(Fpscr, state); 822 FpDestP0.uw = cDest.bits; 823 FpDestP1.uw = cDest.bits >> 32; 824 ''' 825 vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp", 826 { "code": vcvtSIntFpDCode, 827 "predicate_test": predicateTest }, []) 828 header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop); 829 decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop); 830 exec_output += PredOpExecute.subst(vcvtSIntFpDIop); 831 832 vcvtFpUIntSRCode = ''' 833 VfpSavedState state = prepVfpFpscr(Fpscr); 834 FpDest.uw = FpOp1; 835 Fpscr = setVfpFpscr(Fpscr, state); 836 ''' 837 vcvtFpUIntSRIop = InstObjParams("vcvt", "VcvtFpUIntSR", "VfpRegRegOp", 838 { "code": vcvtFpUIntSRCode, 839 "predicate_test": predicateTest }, []) 840 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSRIop); 841 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSRIop); 842 exec_output += PredOpExecute.subst(vcvtFpUIntSRIop); 843 844 vcvtFpUIntDRCode = ''' 845 IntDoubleUnion cOp1; 846 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 847 VfpSavedState state = prepVfpFpscr(Fpscr); 848 uint64_t result = cOp1.fp; 849 Fpscr = setVfpFpscr(Fpscr, state); 850 FpDestP0.uw = result; 851 ''' 852 vcvtFpUIntDRIop = InstObjParams("vcvtr", "VcvtFpUIntDR", "VfpRegRegOp", 853 { "code": vcvtFpUIntDRCode, 854 "predicate_test": predicateTest }, []) 855 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDRIop); 856 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDRIop); 857 exec_output += PredOpExecute.subst(vcvtFpUIntDRIop); 858 859 vcvtFpSIntSRCode = ''' 860 VfpSavedState state = prepVfpFpscr(Fpscr); 861 FpDest.sw = FpOp1; 862 Fpscr = setVfpFpscr(Fpscr, state); 863 ''' 864 vcvtFpSIntSRIop = InstObjParams("vcvtr", "VcvtFpSIntSR", "VfpRegRegOp", 865 { "code": vcvtFpSIntSRCode, 866 "predicate_test": predicateTest }, []) 867 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSRIop); 868 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSRIop); 869 exec_output += PredOpExecute.subst(vcvtFpSIntSRIop); 870 871 vcvtFpSIntDRCode = ''' 872 IntDoubleUnion cOp1; 873 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 874 VfpSavedState state = prepVfpFpscr(Fpscr); 875 int64_t result = cOp1.fp; 876 Fpscr = setVfpFpscr(Fpscr, state); 877 FpDestP0.uw = result; 878 ''' 879 vcvtFpSIntDRIop = InstObjParams("vcvtr", "VcvtFpSIntDR", "VfpRegRegOp", 880 { "code": vcvtFpSIntDRCode, 881 "predicate_test": predicateTest }, []) 882 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDRIop); 883 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDRIop); 884 exec_output += PredOpExecute.subst(vcvtFpSIntDRIop); 885 886 vcvtFpUIntSCode = ''' 887 VfpSavedState state = prepVfpFpscr(Fpscr); 888 fesetround(FeRoundZero); 889 FpDest.uw = FpOp1; 890 Fpscr = setVfpFpscr(Fpscr, state); 891 ''' 892 vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp", 893 { "code": vcvtFpUIntSCode, 894 "predicate_test": predicateTest }, []) 895 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop); 896 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop); 897 exec_output += PredOpExecute.subst(vcvtFpUIntSIop); 898 899 vcvtFpUIntDCode = ''' 900 IntDoubleUnion cOp1; 901 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 902 VfpSavedState state = prepVfpFpscr(Fpscr); 903 fesetround(FeRoundZero); 904 uint64_t result = cOp1.fp; 905 Fpscr = setVfpFpscr(Fpscr, state); 906 FpDestP0.uw = result; 907 ''' 908 vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp", 909 { "code": vcvtFpUIntDCode, 910 "predicate_test": predicateTest }, []) 911 header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop); 912 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop); 913 exec_output += PredOpExecute.subst(vcvtFpUIntDIop); 914 915 vcvtFpSIntSCode = ''' 916 VfpSavedState state = prepVfpFpscr(Fpscr); 917 fesetround(FeRoundZero); 918 FpDest.sw = FpOp1; 919 Fpscr = setVfpFpscr(Fpscr, state); 920 ''' 921 vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp", 922 { "code": vcvtFpSIntSCode, 923 "predicate_test": predicateTest }, []) 924 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop); 925 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop); 926 exec_output += PredOpExecute.subst(vcvtFpSIntSIop); 927 928 vcvtFpSIntDCode = ''' 929 IntDoubleUnion cOp1; 930 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 931 VfpSavedState state = prepVfpFpscr(Fpscr); 932 fesetround(FeRoundZero); 933 int64_t result = cOp1.fp; 934 Fpscr = setVfpFpscr(Fpscr, state); 935 FpDestP0.uw = result; 936 ''' 937 vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp", 938 { "code": vcvtFpSIntDCode, 939 "predicate_test": predicateTest }, []) 940 header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop); 941 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop); 942 exec_output += PredOpExecute.subst(vcvtFpSIntDIop); 943 944 vcvtFpSFpDCode = ''' 945 IntDoubleUnion cDest; 946 VfpSavedState state = prepVfpFpscr(Fpscr); 947 cDest.fp = FpOp1; 948 Fpscr = setVfpFpscr(Fpscr, state); 949 FpDestP0.uw = cDest.bits; 950 FpDestP1.uw = cDest.bits >> 32; 951 ''' 952 vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp", 953 { "code": vcvtFpSFpDCode, 954 "predicate_test": predicateTest }, []) 955 header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop); 956 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop); 957 exec_output += PredOpExecute.subst(vcvtFpSFpDIop); 958 959 vcvtFpDFpSCode = ''' 960 IntDoubleUnion cOp1; 961 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 962 VfpSavedState state = prepVfpFpscr(Fpscr); 963 FpDest = cOp1.fp; 964 Fpscr = setVfpFpscr(Fpscr, state); 965 ''' 966 vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp", 967 { "code": vcvtFpDFpSCode, 968 "predicate_test": predicateTest }, []) 969 header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop); 970 decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop); 971 exec_output += PredOpExecute.subst(vcvtFpDFpSIop); 972 973 vcmpSCode = ''' 974 FPSCR fpscr = Fpscr; 975 if (FpDest == FpOp1) { 976 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 977 } else if (FpDest < FpOp1) { 978 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 979 } else if (FpDest > FpOp1) { 980 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 981 } else { 982 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 983 } 984 Fpscr = fpscr; 985 ''' 986 vcmpSIop = InstObjParams("vcmps", "VcmpS", "VfpRegRegOp", 987 { "code": vcmpSCode, 988 "predicate_test": predicateTest }, []) 989 header_output += VfpRegRegOpDeclare.subst(vcmpSIop); 990 decoder_output += VfpRegRegOpConstructor.subst(vcmpSIop); 991 exec_output += PredOpExecute.subst(vcmpSIop); 992 993 vcmpDCode = ''' 994 IntDoubleUnion cOp1, cDest; 995 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 996 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 997 FPSCR fpscr = Fpscr; 998 if (cDest.fp == cOp1.fp) { 999 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1000 } else if (cDest.fp < cOp1.fp) { 1001 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1002 } else if (cDest.fp > cOp1.fp) { 1003 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1004 } else { 1005 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1006 } 1007 Fpscr = fpscr; 1008 ''' 1009 vcmpDIop = InstObjParams("vcmpd", "VcmpD", "VfpRegRegOp", 1010 { "code": vcmpDCode, 1011 "predicate_test": predicateTest }, []) 1012 header_output += VfpRegRegOpDeclare.subst(vcmpDIop); 1013 decoder_output += VfpRegRegOpConstructor.subst(vcmpDIop); 1014 exec_output += PredOpExecute.subst(vcmpDIop); 1015 1016 vcmpZeroSCode = ''' 1017 FPSCR fpscr = Fpscr; 1018 if (FpDest == imm) { 1019 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1020 } else if (FpDest < imm) { 1021 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1022 } else if (FpDest > imm) { 1023 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1024 } else { 1025 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1026 } 1027 Fpscr = fpscr; 1028 ''' 1029 vcmpZeroSIop = InstObjParams("vcmpZeros", "VcmpZeroS", "VfpRegImmOp", 1030 { "code": vcmpZeroSCode, 1031 "predicate_test": predicateTest }, []) 1032 header_output += VfpRegImmOpDeclare.subst(vcmpZeroSIop); 1033 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroSIop); 1034 exec_output += PredOpExecute.subst(vcmpZeroSIop); 1035 1036 vcmpZeroDCode = ''' 1037 IntDoubleUnion cDest; 1038 cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32)); 1039 FPSCR fpscr = Fpscr; 1040 if (cDest.fp == imm) { 1041 fpscr.n = 0; fpscr.z = 1; fpscr.c = 1; fpscr.v = 0; 1042 } else if (cDest.fp < imm) { 1043 fpscr.n = 1; fpscr.z = 0; fpscr.c = 0; fpscr.v = 0; 1044 } else if (cDest.fp > imm) { 1045 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 0; 1046 } else { 1047 fpscr.n = 0; fpscr.z = 0; fpscr.c = 1; fpscr.v = 1; 1048 } 1049 Fpscr = fpscr; 1050 ''' 1051 vcmpZeroDIop = InstObjParams("vcmpZerod", "VcmpZeroD", "VfpRegImmOp", 1052 { "code": vcmpZeroDCode, 1053 "predicate_test": predicateTest }, []) 1054 header_output += VfpRegImmOpDeclare.subst(vcmpZeroDIop); 1055 decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop); 1056 exec_output += PredOpExecute.subst(vcmpZeroDIop); 1057}}; 1058 1059let {{ 1060 1061 header_output = "" 1062 decoder_output = "" 1063 exec_output = "" 1064 1065 vcvtFpSFixedSCode = ''' 1066 VfpSavedState state = prepVfpFpscr(Fpscr); 1067 FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm); 1068 Fpscr = setVfpFpscr(Fpscr, state); 1069 ''' 1070 vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp", 1071 { "code": vcvtFpSFixedSCode, 1072 "predicate_test": predicateTest }, []) 1073 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop); 1074 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop); 1075 exec_output += PredOpExecute.subst(vcvtFpSFixedSIop); 1076 1077 vcvtFpSFixedDCode = ''' 1078 IntDoubleUnion cOp1; 1079 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1080 VfpSavedState state = prepVfpFpscr(Fpscr); 1081 uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm); 1082 Fpscr = setVfpFpscr(Fpscr, state); 1083 FpDestP0.uw = mid; 1084 FpDestP1.uw = mid >> 32; 1085 ''' 1086 vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp", 1087 { "code": vcvtFpSFixedDCode, 1088 "predicate_test": predicateTest }, []) 1089 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop); 1090 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop); 1091 exec_output += PredOpExecute.subst(vcvtFpSFixedDIop); 1092 1093 vcvtFpUFixedSCode = ''' 1094 VfpSavedState state = prepVfpFpscr(Fpscr); 1095 FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm); 1096 Fpscr = setVfpFpscr(Fpscr, state); 1097 ''' 1098 vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp", 1099 { "code": vcvtFpUFixedSCode, 1100 "predicate_test": predicateTest }, []) 1101 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop); 1102 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop); 1103 exec_output += PredOpExecute.subst(vcvtFpUFixedSIop); 1104 1105 vcvtFpUFixedDCode = ''' 1106 IntDoubleUnion cOp1; 1107 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1108 VfpSavedState state = prepVfpFpscr(Fpscr); 1109 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm); 1110 Fpscr = setVfpFpscr(Fpscr, state); 1111 FpDestP0.uw = mid; 1112 FpDestP1.uw = mid >> 32; 1113 ''' 1114 vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp", 1115 { "code": vcvtFpUFixedDCode, 1116 "predicate_test": predicateTest }, []) 1117 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop); 1118 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop); 1119 exec_output += PredOpExecute.subst(vcvtFpUFixedDIop); 1120 1121 vcvtSFixedFpSCode = ''' 1122 VfpSavedState state = prepVfpFpscr(Fpscr); 1123 FpDest = vfpSFixedToFpS(FpOp1.sw, false, imm); 1124 Fpscr = setVfpFpscr(Fpscr, state); 1125 ''' 1126 vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp", 1127 { "code": vcvtSFixedFpSCode, 1128 "predicate_test": predicateTest }, []) 1129 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop); 1130 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop); 1131 exec_output += PredOpExecute.subst(vcvtSFixedFpSIop); 1132 1133 vcvtSFixedFpDCode = ''' 1134 IntDoubleUnion cDest; 1135 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1136 VfpSavedState state = prepVfpFpscr(Fpscr); 1137 cDest.fp = vfpSFixedToFpD(mid, false, imm); 1138 Fpscr = setVfpFpscr(Fpscr, state); 1139 FpDestP0.uw = cDest.bits; 1140 FpDestP1.uw = cDest.bits >> 32; 1141 ''' 1142 vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp", 1143 { "code": vcvtSFixedFpDCode, 1144 "predicate_test": predicateTest }, []) 1145 header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop); 1146 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop); 1147 exec_output += PredOpExecute.subst(vcvtSFixedFpDIop); 1148 1149 vcvtUFixedFpSCode = ''' 1150 VfpSavedState state = prepVfpFpscr(Fpscr); 1151 FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm); 1152 Fpscr = setVfpFpscr(Fpscr, state); 1153 ''' 1154 vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp", 1155 { "code": vcvtUFixedFpSCode, 1156 "predicate_test": predicateTest }, []) 1157 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop); 1158 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop); 1159 exec_output += PredOpExecute.subst(vcvtUFixedFpSIop); 1160 1161 vcvtUFixedFpDCode = ''' 1162 IntDoubleUnion cDest; 1163 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1164 VfpSavedState state = prepVfpFpscr(Fpscr); 1165 cDest.fp = vfpUFixedToFpD(mid, false, imm); 1166 Fpscr = setVfpFpscr(Fpscr, state); 1167 FpDestP0.uw = cDest.bits; 1168 FpDestP1.uw = cDest.bits >> 32; 1169 ''' 1170 vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp", 1171 { "code": vcvtUFixedFpDCode, 1172 "predicate_test": predicateTest }, []) 1173 header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop); 1174 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop); 1175 exec_output += PredOpExecute.subst(vcvtUFixedFpDIop); 1176 1177 vcvtFpSHFixedSCode = ''' 1178 VfpSavedState state = prepVfpFpscr(Fpscr); 1179 FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm); 1180 Fpscr = setVfpFpscr(Fpscr, state); 1181 ''' 1182 vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS", 1183 "VfpRegRegImmOp", 1184 { "code": vcvtFpSHFixedSCode, 1185 "predicate_test": predicateTest }, []) 1186 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop); 1187 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop); 1188 exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop); 1189 1190 vcvtFpSHFixedDCode = ''' 1191 IntDoubleUnion cOp1; 1192 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1193 VfpSavedState state = prepVfpFpscr(Fpscr); 1194 uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm); 1195 Fpscr = setVfpFpscr(Fpscr, state); 1196 FpDestP0.uw = result; 1197 FpDestP1.uw = result >> 32; 1198 ''' 1199 vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD", 1200 "VfpRegRegImmOp", 1201 { "code": vcvtFpSHFixedDCode, 1202 "predicate_test": predicateTest }, []) 1203 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop); 1204 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop); 1205 exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop); 1206 1207 vcvtFpUHFixedSCode = ''' 1208 VfpSavedState state = prepVfpFpscr(Fpscr); 1209 FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm); 1210 Fpscr = setVfpFpscr(Fpscr, state); 1211 ''' 1212 vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS", 1213 "VfpRegRegImmOp", 1214 { "code": vcvtFpUHFixedSCode, 1215 "predicate_test": predicateTest }, []) 1216 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop); 1217 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop); 1218 exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop); 1219 1220 vcvtFpUHFixedDCode = ''' 1221 IntDoubleUnion cOp1; 1222 cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1223 VfpSavedState state = prepVfpFpscr(Fpscr); 1224 uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm); 1225 Fpscr = setVfpFpscr(Fpscr, state); 1226 FpDestP0.uw = mid; 1227 FpDestP1.uw = mid >> 32; 1228 ''' 1229 vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD", 1230 "VfpRegRegImmOp", 1231 { "code": vcvtFpUHFixedDCode, 1232 "predicate_test": predicateTest }, []) 1233 header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop); 1234 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop); 1235 exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop); 1236 1237 vcvtSHFixedFpSCode = ''' 1238 VfpSavedState state = prepVfpFpscr(Fpscr); 1239 FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm); 1240 Fpscr = setVfpFpscr(Fpscr, state); 1241 ''' 1242 vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS", 1243 "VfpRegRegImmOp", 1244 { "code": vcvtSHFixedFpSCode, 1245 "predicate_test": predicateTest }, []) 1246 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop); 1247 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop); 1248 exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop); 1249 1250 vcvtSHFixedFpDCode = ''' 1251 IntDoubleUnion cDest; 1252 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1253 VfpSavedState state = prepVfpFpscr(Fpscr); 1254 cDest.fp = vfpSFixedToFpD(mid, true, imm); 1255 Fpscr = setVfpFpscr(Fpscr, state); 1256 FpDestP0.uw = cDest.bits; 1257 FpDestP1.uw = cDest.bits >> 32; 1258 ''' 1259 vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD", 1260 "VfpRegRegImmOp", 1261 { "code": vcvtSHFixedFpDCode, 1262 "predicate_test": predicateTest }, []) 1263 header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop); 1264 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop); 1265 exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop); 1266 1267 vcvtUHFixedFpSCode = ''' 1268 VfpSavedState state = prepVfpFpscr(Fpscr); 1269 FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm); 1270 Fpscr = setVfpFpscr(Fpscr, state); 1271 ''' 1272 vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS", 1273 "VfpRegRegImmOp", 1274 { "code": vcvtUHFixedFpSCode, 1275 "predicate_test": predicateTest }, []) 1276 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop); 1277 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop); 1278 exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop); 1279 1280 vcvtUHFixedFpDCode = ''' 1281 IntDoubleUnion cDest; 1282 uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32)); 1283 VfpSavedState state = prepVfpFpscr(Fpscr); 1284 cDest.fp = vfpUFixedToFpD(mid, true, imm); 1285 Fpscr = setVfpFpscr(Fpscr, state); 1286 FpDestP0.uw = cDest.bits; 1287 FpDestP1.uw = cDest.bits >> 32; 1288 ''' 1289 vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD", 1290 "VfpRegRegImmOp", 1291 { "code": vcvtUHFixedFpDCode, 1292 "predicate_test": predicateTest }, []) 1293 header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop); 1294 decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop); 1295 exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop); 1296}}; 1297