fp.isa revision 7375:7095d84ffb36 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    vmsrIop = InstObjParams("vmsr", "Vmsr", "VfpRegRegOp",
47                            { "code": "MiscDest = Op1;",
48                              "predicate_test": predicateTest }, [])
49    header_output += VfpRegRegOpDeclare.subst(vmsrIop);
50    decoder_output += VfpRegRegOpConstructor.subst(vmsrIop);
51    exec_output += PredOpExecute.subst(vmsrIop);
52
53    vmrsIop = InstObjParams("vmrs", "Vmrs", "VfpRegRegOp",
54                            { "code": "Dest = MiscOp1;",
55                              "predicate_test": predicateTest }, [])
56    header_output += VfpRegRegOpDeclare.subst(vmrsIop);
57    decoder_output += VfpRegRegOpConstructor.subst(vmrsIop);
58    exec_output += PredOpExecute.subst(vmrsIop);
59
60    vmovImmSCode = '''
61        FpDest.uw = bits(imm, 31, 0);
62    '''
63    vmovImmSIop = InstObjParams("vmov", "VmovImmS", "VfpRegImmOp",
64                                { "code": vmovImmSCode,
65                                  "predicate_test": predicateTest }, [])
66    header_output += VfpRegImmOpDeclare.subst(vmovImmSIop);
67    decoder_output += VfpRegImmOpConstructor.subst(vmovImmSIop);
68    exec_output += PredOpExecute.subst(vmovImmSIop);
69
70    vmovImmDCode = '''
71        FpDestP0.uw = bits(imm, 31, 0);
72        FpDestP1.uw = bits(imm, 63, 32);
73    '''
74    vmovImmDIop = InstObjParams("vmov", "VmovImmD", "VfpRegImmOp",
75                                { "code": vmovImmDCode,
76                                  "predicate_test": predicateTest }, [])
77    header_output += VfpRegImmOpDeclare.subst(vmovImmDIop);
78    decoder_output += VfpRegImmOpConstructor.subst(vmovImmDIop);
79    exec_output += PredOpExecute.subst(vmovImmDIop);
80
81    vmovImmQCode = '''
82        FpDestP0.uw = bits(imm, 31, 0);
83        FpDestP1.uw = bits(imm, 63, 32);
84        FpDestP2.uw = bits(imm, 31, 0);
85        FpDestP3.uw = bits(imm, 63, 32);
86    '''
87    vmovImmQIop = InstObjParams("vmov", "VmovImmQ", "VfpRegImmOp",
88                                { "code": vmovImmQCode,
89                                  "predicate_test": predicateTest }, [])
90    header_output += VfpRegImmOpDeclare.subst(vmovImmQIop);
91    decoder_output += VfpRegImmOpConstructor.subst(vmovImmQIop);
92    exec_output += PredOpExecute.subst(vmovImmQIop);
93
94    vmovRegSCode = '''
95        FpDest.uw = FpOp1.uw;
96    '''
97    vmovRegSIop = InstObjParams("vmov", "VmovRegS", "VfpRegRegOp",
98                                { "code": vmovRegSCode,
99                                  "predicate_test": predicateTest }, [])
100    header_output += VfpRegRegOpDeclare.subst(vmovRegSIop);
101    decoder_output += VfpRegRegOpConstructor.subst(vmovRegSIop);
102    exec_output += PredOpExecute.subst(vmovRegSIop);
103
104    vmovRegDCode = '''
105        FpDestP0.uw = FpOp1P0.uw;
106        FpDestP1.uw = FpOp1P1.uw;
107    '''
108    vmovRegDIop = InstObjParams("vmov", "VmovRegD", "VfpRegRegOp",
109                                { "code": vmovRegDCode,
110                                  "predicate_test": predicateTest }, [])
111    header_output += VfpRegRegOpDeclare.subst(vmovRegDIop);
112    decoder_output += VfpRegRegOpConstructor.subst(vmovRegDIop);
113    exec_output += PredOpExecute.subst(vmovRegDIop);
114
115    vmovRegQCode = '''
116        FpDestP0.uw = FpOp1P0.uw;
117        FpDestP1.uw = FpOp1P1.uw;
118        FpDestP2.uw = FpOp1P2.uw;
119        FpDestP3.uw = FpOp1P3.uw;
120    '''
121    vmovRegQIop = InstObjParams("vmov", "VmovRegQ", "VfpRegRegOp",
122                                { "code": vmovRegQCode,
123                                  "predicate_test": predicateTest }, [])
124    header_output  += VfpRegRegOpDeclare.subst(vmovRegQIop);
125    decoder_output  += VfpRegRegOpConstructor.subst(vmovRegQIop);
126    exec_output += PredOpExecute.subst(vmovRegQIop);
127
128    vmovCoreRegBCode = '''
129        FpDest.uw = insertBits(FpDest.uw, imm * 8, imm * 8 + 7, Op1.ub);
130    '''
131    vmovCoreRegBIop = InstObjParams("vmov", "VmovCoreRegB", "VfpRegRegImmOp",
132                                    { "code": vmovCoreRegBCode,
133                                      "predicate_test": predicateTest }, [])
134    header_output  += VfpRegRegImmOpDeclare.subst(vmovCoreRegBIop);
135    decoder_output  += VfpRegRegImmOpConstructor.subst(vmovCoreRegBIop);
136    exec_output += PredOpExecute.subst(vmovCoreRegBIop);
137
138    vmovCoreRegHCode = '''
139        FpDest.uw = insertBits(FpDest.uw, imm * 16, imm * 16 + 15, Op1.uh);
140    '''
141    vmovCoreRegHIop = InstObjParams("vmov", "VmovCoreRegH", "VfpRegRegImmOp",
142                                    { "code": vmovCoreRegHCode,
143                                      "predicate_test": predicateTest }, [])
144    header_output  += VfpRegRegImmOpDeclare.subst(vmovCoreRegHIop);
145    decoder_output  += VfpRegRegImmOpConstructor.subst(vmovCoreRegHIop);
146    exec_output += PredOpExecute.subst(vmovCoreRegHIop);
147
148    vmovCoreRegWCode = '''
149        FpDest.uw = Op1.uw;
150    '''
151    vmovCoreRegWIop = InstObjParams("vmov", "VmovCoreRegW", "VfpRegRegOp",
152                                    { "code": vmovCoreRegWCode,
153                                      "predicate_test": predicateTest }, [])
154    header_output  += VfpRegRegOpDeclare.subst(vmovCoreRegWIop);
155    decoder_output  += VfpRegRegOpConstructor.subst(vmovCoreRegWIop);
156    exec_output += PredOpExecute.subst(vmovCoreRegWIop);
157
158    vmovRegCoreUBCode = '''
159        Dest = bits(FpOp1.uw, imm * 8, imm * 8 + 7);
160    '''
161    vmovRegCoreUBIop = InstObjParams("vmov", "VmovRegCoreUB", "VfpRegRegImmOp",
162                                     { "code": vmovRegCoreUBCode,
163                                       "predicate_test": predicateTest }, [])
164    header_output  += VfpRegRegImmOpDeclare.subst(vmovRegCoreUBIop);
165    decoder_output  += VfpRegRegImmOpConstructor.subst(vmovRegCoreUBIop);
166    exec_output += PredOpExecute.subst(vmovRegCoreUBIop);
167
168    vmovRegCoreUHCode = '''
169        Dest = bits(FpOp1.uw, imm * 16, imm * 16 + 15);
170    '''
171    vmovRegCoreUHIop = InstObjParams("vmov", "VmovRegCoreUH", "VfpRegRegImmOp",
172                                     { "code": vmovRegCoreUHCode,
173                                       "predicate_test": predicateTest }, [])
174    header_output  += VfpRegRegImmOpDeclare.subst(vmovRegCoreUHIop);
175    decoder_output  += VfpRegRegImmOpConstructor.subst(vmovRegCoreUHIop);
176    exec_output += PredOpExecute.subst(vmovRegCoreUHIop);
177
178    vmovRegCoreSBCode = '''
179        Dest = sext<8>(bits(FpOp1.uw, imm * 8, imm * 8 + 7));
180    '''
181    vmovRegCoreSBIop = InstObjParams("vmov", "VmovRegCoreSB", "VfpRegRegImmOp",
182                                     { "code": vmovRegCoreSBCode,
183                                       "predicate_test": predicateTest }, [])
184    header_output  += VfpRegRegImmOpDeclare.subst(vmovRegCoreSBIop);
185    decoder_output  += VfpRegRegImmOpConstructor.subst(vmovRegCoreSBIop);
186    exec_output += PredOpExecute.subst(vmovRegCoreSBIop);
187
188    vmovRegCoreSHCode = '''
189        Dest = sext<16>(bits(FpOp1.uw, imm * 16, imm * 16 + 15));
190    '''
191    vmovRegCoreSHIop = InstObjParams("vmov", "VmovRegCoreSH", "VfpRegRegImmOp",
192                                     { "code": vmovRegCoreSHCode,
193                                       "predicate_test": predicateTest }, [])
194    header_output  += VfpRegRegImmOpDeclare.subst(vmovRegCoreSHIop);
195    decoder_output  += VfpRegRegImmOpConstructor.subst(vmovRegCoreSHIop);
196    exec_output += PredOpExecute.subst(vmovRegCoreSHIop);
197
198    vmovRegCoreWCode = '''
199        Dest = FpOp1.uw;
200    '''
201    vmovRegCoreWIop = InstObjParams("vmov", "VmovRegCoreW", "VfpRegRegOp",
202                                     { "code": vmovRegCoreWCode,
203                                       "predicate_test": predicateTest }, [])
204    header_output  += VfpRegRegOpDeclare.subst(vmovRegCoreWIop);
205    decoder_output  += VfpRegRegOpConstructor.subst(vmovRegCoreWIop);
206    exec_output += PredOpExecute.subst(vmovRegCoreWIop);
207
208    vmov2Reg2CoreCode = '''
209        FpDestP0.uw = Op1.uw;
210        FpDestP1.uw = Op2.uw;
211    '''
212    vmov2Reg2CoreIop = InstObjParams("vmov", "Vmov2Reg2Core", "VfpRegRegRegOp",
213                                     { "code": vmov2Reg2CoreCode,
214                                       "predicate_test": predicateTest }, [])
215    header_output  += VfpRegRegRegOpDeclare.subst(vmov2Reg2CoreIop);
216    decoder_output  += VfpRegRegRegOpConstructor.subst(vmov2Reg2CoreIop);
217    exec_output += PredOpExecute.subst(vmov2Reg2CoreIop);
218
219    vmov2Core2RegCode = '''
220        Dest.uw = FpOp2P0.uw;
221        Op1.uw = FpOp2P1.uw;
222    '''
223    vmov2Core2RegIop = InstObjParams("vmov", "Vmov2Core2Reg", "VfpRegRegRegOp",
224                                     { "code": vmov2Core2RegCode,
225                                       "predicate_test": predicateTest }, [])
226    header_output  += VfpRegRegRegOpDeclare.subst(vmov2Core2RegIop);
227    decoder_output  += VfpRegRegRegOpConstructor.subst(vmov2Core2RegIop);
228    exec_output += PredOpExecute.subst(vmov2Core2RegIop);
229
230    vmulSCode = '''
231        FpDest = FpOp1 * FpOp2;
232        if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
233            FpDest = NAN;
234        }
235    '''
236    vmulSIop = InstObjParams("vmuls", "VmulS", "VfpRegRegRegOp",
237                                     { "code": vmulSCode,
238                                       "predicate_test": predicateTest }, [])
239    header_output  += VfpRegRegRegOpDeclare.subst(vmulSIop);
240    decoder_output  += VfpRegRegRegOpConstructor.subst(vmulSIop);
241    exec_output += PredOpExecute.subst(vmulSIop);
242
243    vmulDCode = '''
244        IntDoubleUnion cOp1, cOp2, cDest;
245        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
246        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
247        cDest.fp = cOp1.fp * cOp2.fp;
248        if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
249                (isinf(cOp2.fp) && cOp1.fp == 0)) {
250            cDest.fp = NAN;
251        }
252        FpDestP0.uw = cDest.bits;
253        FpDestP1.uw = cDest.bits >> 32;
254    '''
255    vmulDIop = InstObjParams("vmuld", "VmulD", "VfpRegRegRegOp",
256                                     { "code": vmulDCode,
257                                       "predicate_test": predicateTest }, [])
258    header_output += VfpRegRegRegOpDeclare.subst(vmulDIop);
259    decoder_output += VfpRegRegRegOpConstructor.subst(vmulDIop);
260    exec_output += PredOpExecute.subst(vmulDIop);
261
262    vnegSCode = '''
263        FpDest = -FpOp1;
264    '''
265    vnegSIop = InstObjParams("vnegs", "VnegS", "VfpRegRegOp",
266                                     { "code": vnegSCode,
267                                       "predicate_test": predicateTest }, [])
268    header_output += VfpRegRegOpDeclare.subst(vnegSIop);
269    decoder_output += VfpRegRegOpConstructor.subst(vnegSIop);
270    exec_output += PredOpExecute.subst(vnegSIop);
271
272    vnegDCode = '''
273        IntDoubleUnion cOp1, cDest;
274        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
275        cDest.fp = -cOp1.fp;
276        FpDestP0.uw = cDest.bits;
277        FpDestP1.uw = cDest.bits >> 32;
278    '''
279    vnegDIop = InstObjParams("vnegd", "VnegD", "VfpRegRegOp",
280                                     { "code": vnegDCode,
281                                       "predicate_test": predicateTest }, [])
282    header_output += VfpRegRegOpDeclare.subst(vnegDIop);
283    decoder_output += VfpRegRegOpConstructor.subst(vnegDIop);
284    exec_output += PredOpExecute.subst(vnegDIop);
285
286    vabsSCode = '''
287        FpDest = fabsf(FpOp1);
288    '''
289    vabsSIop = InstObjParams("vabss", "VabsS", "VfpRegRegOp",
290                                     { "code": vabsSCode,
291                                       "predicate_test": predicateTest }, [])
292    header_output += VfpRegRegOpDeclare.subst(vabsSIop);
293    decoder_output += VfpRegRegOpConstructor.subst(vabsSIop);
294    exec_output += PredOpExecute.subst(vabsSIop);
295
296    vabsDCode = '''
297        IntDoubleUnion cOp1, cDest;
298        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
299        cDest.fp = fabs(cOp1.fp);
300        FpDestP0.uw = cDest.bits;
301        FpDestP1.uw = cDest.bits >> 32;
302    '''
303    vabsDIop = InstObjParams("vabsd", "VabsD", "VfpRegRegOp",
304                                     { "code": vabsDCode,
305                                       "predicate_test": predicateTest }, [])
306    header_output += VfpRegRegOpDeclare.subst(vabsDIop);
307    decoder_output += VfpRegRegOpConstructor.subst(vabsDIop);
308    exec_output += PredOpExecute.subst(vabsDIop);
309
310    vaddSCode = '''
311        FpDest = FpOp1 + FpOp2;
312    '''
313    vaddSIop = InstObjParams("vadds", "VaddS", "VfpRegRegRegOp",
314                                     { "code": vaddSCode,
315                                       "predicate_test": predicateTest }, [])
316    header_output += VfpRegRegRegOpDeclare.subst(vaddSIop);
317    decoder_output += VfpRegRegRegOpConstructor.subst(vaddSIop);
318    exec_output += PredOpExecute.subst(vaddSIop);
319
320    vaddDCode = '''
321        IntDoubleUnion cOp1, cOp2, cDest;
322        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
323        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
324        cDest.fp = cOp1.fp + cOp2.fp;
325        FpDestP0.uw = cDest.bits;
326        FpDestP1.uw = cDest.bits >> 32;
327    '''
328    vaddDIop = InstObjParams("vaddd", "VaddD", "VfpRegRegRegOp",
329                                     { "code": vaddDCode,
330                                       "predicate_test": predicateTest }, [])
331    header_output += VfpRegRegRegOpDeclare.subst(vaddDIop);
332    decoder_output += VfpRegRegRegOpConstructor.subst(vaddDIop);
333    exec_output += PredOpExecute.subst(vaddDIop);
334
335    vsubSCode = '''
336        FpDest = FpOp1 - FpOp2;
337    '''
338    vsubSIop = InstObjParams("vsubs", "VsubS", "VfpRegRegRegOp",
339                                     { "code": vsubSCode,
340                                       "predicate_test": predicateTest }, [])
341    header_output += VfpRegRegRegOpDeclare.subst(vsubSIop);
342    decoder_output += VfpRegRegRegOpConstructor.subst(vsubSIop);
343    exec_output += PredOpExecute.subst(vsubSIop);
344
345    vsubDCode = '''
346        IntDoubleUnion cOp1, cOp2, cDest;
347        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
348        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
349        cDest.fp = cOp1.fp - cOp2.fp;
350        FpDestP0.uw = cDest.bits;
351        FpDestP1.uw = cDest.bits >> 32;
352    '''
353    vsubDIop = InstObjParams("vsubd", "VsubD", "VfpRegRegRegOp",
354                                     { "code": vsubDCode,
355                                       "predicate_test": predicateTest }, [])
356    header_output += VfpRegRegRegOpDeclare.subst(vsubDIop);
357    decoder_output += VfpRegRegRegOpConstructor.subst(vsubDIop);
358    exec_output += PredOpExecute.subst(vsubDIop);
359
360    vdivSCode = '''
361        FpDest = FpOp1 / FpOp2;
362    '''
363    vdivSIop = InstObjParams("vdivs", "VdivS", "VfpRegRegRegOp",
364                                     { "code": vdivSCode,
365                                       "predicate_test": predicateTest }, [])
366    header_output += VfpRegRegRegOpDeclare.subst(vdivSIop);
367    decoder_output += VfpRegRegRegOpConstructor.subst(vdivSIop);
368    exec_output += PredOpExecute.subst(vdivSIop);
369
370    vdivDCode = '''
371        IntDoubleUnion cOp1, cOp2, cDest;
372        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
373        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
374        cDest.fp = cOp1.fp / cOp2.fp;
375        FpDestP0.uw = cDest.bits;
376        FpDestP1.uw = cDest.bits >> 32;
377    '''
378    vdivDIop = InstObjParams("vdivd", "VdivD", "VfpRegRegRegOp",
379                                     { "code": vdivDCode,
380                                       "predicate_test": predicateTest }, [])
381    header_output += VfpRegRegRegOpDeclare.subst(vdivDIop);
382    decoder_output += VfpRegRegRegOpConstructor.subst(vdivDIop);
383    exec_output += PredOpExecute.subst(vdivDIop);
384
385    vsqrtSCode = '''
386        FpDest = sqrtf(FpOp1);
387        if (FpOp1 < 0) {
388            FpDest = NAN;
389        }
390    '''
391    vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "VfpRegRegOp",
392                                     { "code": vsqrtSCode,
393                                       "predicate_test": predicateTest }, [])
394    header_output += VfpRegRegOpDeclare.subst(vsqrtSIop);
395    decoder_output += VfpRegRegOpConstructor.subst(vsqrtSIop);
396    exec_output += PredOpExecute.subst(vsqrtSIop);
397
398    vsqrtDCode = '''
399        IntDoubleUnion cOp1, cDest;
400        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
401        cDest.fp = sqrt(cOp1.fp);
402        if (cOp1.fp < 0) {
403            cDest.fp = NAN;
404        }
405        FpDestP0.uw = cDest.bits;
406        FpDestP1.uw = cDest.bits >> 32;
407    '''
408    vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "VfpRegRegOp",
409                                     { "code": vsqrtDCode,
410                                       "predicate_test": predicateTest }, [])
411    header_output  += VfpRegRegOpDeclare.subst(vsqrtDIop);
412    decoder_output  += VfpRegRegOpConstructor.subst(vsqrtDIop);
413    exec_output += PredOpExecute.subst(vsqrtDIop);
414
415    vmlaSCode = '''
416        float mid = FpOp1 * FpOp2;
417        if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
418            mid = NAN;
419        }
420        FpDest = FpDest + mid;
421    '''
422    vmlaSIop = InstObjParams("vmlas", "VmlaS", "VfpRegRegRegOp",
423                                     { "code": vmlaSCode,
424                                       "predicate_test": predicateTest }, [])
425    header_output  += VfpRegRegRegOpDeclare.subst(vmlaSIop);
426    decoder_output  += VfpRegRegRegOpConstructor.subst(vmlaSIop);
427    exec_output += PredOpExecute.subst(vmlaSIop);
428
429    vmlaDCode = '''
430        IntDoubleUnion cOp1, cOp2, cDest;
431        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
432        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
433        cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
434        double mid = cOp1.fp * cOp2.fp;
435        if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
436                (isinf(cOp2.fp) && cOp1.fp == 0)) {
437            mid = NAN;
438        }
439        cDest.fp = cDest.fp + mid;
440        FpDestP0.uw = cDest.bits;
441        FpDestP1.uw = cDest.bits >> 32;
442    '''
443    vmlaDIop = InstObjParams("vmlad", "VmlaD", "VfpRegRegRegOp",
444                                     { "code": vmlaDCode,
445                                       "predicate_test": predicateTest }, [])
446    header_output  += VfpRegRegRegOpDeclare.subst(vmlaDIop);
447    decoder_output  += VfpRegRegRegOpConstructor.subst(vmlaDIop);
448    exec_output += PredOpExecute.subst(vmlaDIop);
449
450    vmlsSCode = '''
451        float mid = FpOp1 * FpOp2;
452        if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
453            mid = NAN;
454        }
455        FpDest = FpDest - mid;
456    '''
457    vmlsSIop = InstObjParams("vmlss", "VmlsS", "VfpRegRegRegOp",
458                                     { "code": vmlsSCode,
459                                       "predicate_test": predicateTest }, [])
460    header_output  += VfpRegRegRegOpDeclare.subst(vmlsSIop);
461    decoder_output  += VfpRegRegRegOpConstructor.subst(vmlsSIop);
462    exec_output += PredOpExecute.subst(vmlsSIop);
463
464    vmlsDCode = '''
465        IntDoubleUnion cOp1, cOp2, cDest;
466        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
467        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
468        cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
469        double mid = cOp1.fp * cOp2.fp;
470        if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
471                (isinf(cOp2.fp) && cOp1.fp == 0)) {
472            mid = NAN;
473        }
474        cDest.fp = cDest.fp - mid;
475        FpDestP0.uw = cDest.bits;
476        FpDestP1.uw = cDest.bits >> 32;
477    '''
478    vmlsDIop = InstObjParams("vmlsd", "VmlsD", "VfpRegRegRegOp",
479                                     { "code": vmlsDCode,
480                                       "predicate_test": predicateTest }, [])
481    header_output  += VfpRegRegRegOpDeclare.subst(vmlsDIop);
482    decoder_output  += VfpRegRegRegOpConstructor.subst(vmlsDIop);
483    exec_output += PredOpExecute.subst(vmlsDIop);
484
485    vnmlaSCode = '''
486        float mid = FpOp1 * FpOp2;
487        if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
488            mid = NAN;
489        }
490        FpDest = -FpDest - mid;
491    '''
492    vnmlaSIop = InstObjParams("vnmlas", "VnmlaS", "VfpRegRegRegOp",
493                                     { "code": vnmlaSCode,
494                                       "predicate_test": predicateTest }, [])
495    header_output  += VfpRegRegRegOpDeclare.subst(vnmlaSIop);
496    decoder_output  += VfpRegRegRegOpConstructor.subst(vnmlaSIop);
497    exec_output += PredOpExecute.subst(vnmlaSIop);
498
499    vnmlaDCode = '''
500        IntDoubleUnion cOp1, cOp2, cDest;
501        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
502        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
503        cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
504        double mid = cOp1.fp * cOp2.fp;
505        if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
506                (isinf(cOp2.fp) && cOp1.fp == 0)) {
507            mid = NAN;
508        }
509        cDest.fp = -cDest.fp - mid;
510        FpDestP0.uw = cDest.bits;
511        FpDestP1.uw = cDest.bits >> 32;
512    '''
513    vnmlaDIop = InstObjParams("vnmlad", "VnmlaD", "VfpRegRegRegOp",
514                                     { "code": vnmlaDCode,
515                                       "predicate_test": predicateTest }, [])
516    header_output  += VfpRegRegRegOpDeclare.subst(vnmlaDIop);
517    decoder_output  += VfpRegRegRegOpConstructor.subst(vnmlaDIop);
518    exec_output += PredOpExecute.subst(vnmlaDIop);
519
520    vnmlsSCode = '''
521        float mid = FpOp1 * FpOp2;
522        if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
523            mid = NAN;
524        }
525        FpDest = -FpDest + mid;
526    '''
527    vnmlsSIop = InstObjParams("vnmlss", "VnmlsS", "VfpRegRegRegOp",
528                                     { "code": vnmlsSCode,
529                                       "predicate_test": predicateTest }, [])
530    header_output  += VfpRegRegRegOpDeclare.subst(vnmlsSIop);
531    decoder_output  += VfpRegRegRegOpConstructor.subst(vnmlsSIop);
532    exec_output += PredOpExecute.subst(vnmlsSIop);
533
534    vnmlsDCode = '''
535        IntDoubleUnion cOp1, cOp2, cDest;
536        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
537        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
538        cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
539        double mid = cOp1.fp * cOp2.fp;
540        if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
541                (isinf(cOp2.fp) && cOp1.fp == 0)) {
542            mid = NAN;
543        }
544        cDest.fp = -cDest.fp + mid;
545        FpDestP0.uw = cDest.bits;
546        FpDestP1.uw = cDest.bits >> 32;
547    '''
548    vnmlsDIop = InstObjParams("vnmlsd", "VnmlsD", "VfpRegRegRegOp",
549                                     { "code": vnmlsDCode,
550                                       "predicate_test": predicateTest }, [])
551    header_output  += VfpRegRegRegOpDeclare.subst(vnmlsDIop);
552    decoder_output  += VfpRegRegRegOpConstructor.subst(vnmlsDIop);
553    exec_output += PredOpExecute.subst(vnmlsDIop);
554
555    vnmulSCode = '''
556        float mid = FpOp1 * FpOp2;
557        if ((isinf(FpOp1) && FpOp2 == 0) || (isinf(FpOp2) && FpOp1 == 0)) {
558            mid = NAN;
559        }
560        FpDest = -mid;
561    '''
562    vnmulSIop = InstObjParams("vnmuls", "VnmulS", "VfpRegRegRegOp",
563                                     { "code": vnmulSCode,
564                                       "predicate_test": predicateTest }, [])
565    header_output  += VfpRegRegRegOpDeclare.subst(vnmulSIop);
566    decoder_output  += VfpRegRegRegOpConstructor.subst(vnmulSIop);
567    exec_output += PredOpExecute.subst(vnmulSIop);
568
569    vnmulDCode = '''
570        IntDoubleUnion cOp1, cOp2, cDest;
571        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
572        cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
573        cDest.bits = ((uint64_t)FpDestP0.uw | ((uint64_t)FpDestP1.uw << 32));
574        double mid = cOp1.fp * cOp2.fp;
575        if ((isinf(cOp1.fp) && cOp2.fp == 0) ||
576                (isinf(cOp2.fp) && cOp1.fp == 0)) {
577            mid = NAN;
578        }
579        cDest.fp = -mid;
580        FpDestP0.uw = cDest.bits;
581        FpDestP1.uw = cDest.bits >> 32;
582    '''
583    vnmulDIop = InstObjParams("vnmuld", "VnmulD", "VfpRegRegRegOp",
584                                     { "code": vnmulDCode,
585                                       "predicate_test": predicateTest }, [])
586    header_output += VfpRegRegRegOpDeclare.subst(vnmulDIop);
587    decoder_output += VfpRegRegRegOpConstructor.subst(vnmulDIop);
588    exec_output += PredOpExecute.subst(vnmulDIop);
589
590    vcvtUIntFpSCode = '''
591        FpDest = FpOp1.uw;
592    '''
593    vcvtUIntFpSIop = InstObjParams("vcvt", "VcvtUIntFpS", "VfpRegRegOp",
594                                     { "code": vcvtUIntFpSCode,
595                                       "predicate_test": predicateTest }, [])
596    header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpSIop);
597    decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpSIop);
598    exec_output += PredOpExecute.subst(vcvtUIntFpSIop);
599
600    vcvtUIntFpDCode = '''
601        IntDoubleUnion cDest;
602        cDest.fp = (uint64_t)FpOp1P0.uw;
603        FpDestP0.uw = cDest.bits;
604        FpDestP1.uw = cDest.bits >> 32;
605    '''
606    vcvtUIntFpDIop = InstObjParams("vcvt", "VcvtUIntFpD", "VfpRegRegOp",
607                                     { "code": vcvtUIntFpDCode,
608                                       "predicate_test": predicateTest }, [])
609    header_output += VfpRegRegOpDeclare.subst(vcvtUIntFpDIop);
610    decoder_output += VfpRegRegOpConstructor.subst(vcvtUIntFpDIop);
611    exec_output += PredOpExecute.subst(vcvtUIntFpDIop);
612
613    vcvtSIntFpSCode = '''
614        FpDest = FpOp1.sw;
615    '''
616    vcvtSIntFpSIop = InstObjParams("vcvt", "VcvtSIntFpS", "VfpRegRegOp",
617                                     { "code": vcvtSIntFpSCode,
618                                       "predicate_test": predicateTest }, [])
619    header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpSIop);
620    decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpSIop);
621    exec_output += PredOpExecute.subst(vcvtSIntFpSIop);
622
623    vcvtSIntFpDCode = '''
624        IntDoubleUnion cDest;
625        cDest.fp = FpOp1P0.sw;
626        FpDestP0.uw = cDest.bits;
627        FpDestP1.uw = cDest.bits >> 32;
628    '''
629    vcvtSIntFpDIop = InstObjParams("vcvt", "VcvtSIntFpD", "VfpRegRegOp",
630                                     { "code": vcvtSIntFpDCode,
631                                       "predicate_test": predicateTest }, [])
632    header_output += VfpRegRegOpDeclare.subst(vcvtSIntFpDIop);
633    decoder_output += VfpRegRegOpConstructor.subst(vcvtSIntFpDIop);
634    exec_output += PredOpExecute.subst(vcvtSIntFpDIop);
635
636    vcvtFpUIntSCode = '''
637        FpDest.uw = FpOp1;
638    '''
639    vcvtFpUIntSIop = InstObjParams("vcvt", "VcvtFpUIntS", "VfpRegRegOp",
640                                     { "code": vcvtFpUIntSCode,
641                                       "predicate_test": predicateTest }, [])
642    header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntSIop);
643    decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntSIop);
644    exec_output += PredOpExecute.subst(vcvtFpUIntSIop);
645
646    vcvtFpUIntDCode = '''
647        IntDoubleUnion cOp1;
648        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
649        uint64_t result = cOp1.fp;
650        FpDestP0.uw = result;
651    '''
652    vcvtFpUIntDIop = InstObjParams("vcvt", "VcvtFpUIntD", "VfpRegRegOp",
653                                     { "code": vcvtFpUIntDCode,
654                                       "predicate_test": predicateTest }, [])
655    header_output += VfpRegRegOpDeclare.subst(vcvtFpUIntDIop);
656    decoder_output += VfpRegRegOpConstructor.subst(vcvtFpUIntDIop);
657    exec_output += PredOpExecute.subst(vcvtFpUIntDIop);
658
659    vcvtFpSIntSCode = '''
660        FpDest.sw = FpOp1;
661    '''
662    vcvtFpSIntSIop = InstObjParams("vcvt", "VcvtFpSIntS", "VfpRegRegOp",
663                                     { "code": vcvtFpSIntSCode,
664                                       "predicate_test": predicateTest }, [])
665    header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntSIop);
666    decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntSIop);
667    exec_output += PredOpExecute.subst(vcvtFpSIntSIop);
668
669    vcvtFpSIntDCode = '''
670        IntDoubleUnion cOp1;
671        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
672        int64_t result = cOp1.fp;
673        FpDestP0.uw = result;
674    '''
675    vcvtFpSIntDIop = InstObjParams("vcvt", "VcvtFpSIntD", "VfpRegRegOp",
676                                     { "code": vcvtFpSIntDCode,
677                                       "predicate_test": predicateTest }, [])
678    header_output += VfpRegRegOpDeclare.subst(vcvtFpSIntDIop);
679    decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSIntDIop);
680    exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
681
682    vcvtFpSFpDCode = '''
683        IntDoubleUnion cDest;
684        cDest.fp = FpOp1;
685        FpDestP0.uw = cDest.bits;
686        FpDestP1.uw = cDest.bits >> 32;
687    '''
688    vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "VfpRegRegOp",
689                                     { "code": vcvtFpSFpDCode,
690                                       "predicate_test": predicateTest }, [])
691    header_output += VfpRegRegOpDeclare.subst(vcvtFpSFpDIop);
692    decoder_output += VfpRegRegOpConstructor.subst(vcvtFpSFpDIop);
693    exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
694
695    vcvtFpDFpSCode = '''
696        IntDoubleUnion cOp1;
697        cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
698        FpDest = cOp1.fp;
699    '''
700    vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "VfpRegRegOp",
701                                     { "code": vcvtFpDFpSCode,
702                                       "predicate_test": predicateTest }, [])
703    header_output += VfpRegRegOpDeclare.subst(vcvtFpDFpSIop);
704    decoder_output += VfpRegRegOpConstructor.subst(vcvtFpDFpSIop);
705    exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
706}};
707