div.isa revision 8588:ef28ed90449d 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41    sdivCode = '''
42    if (Op2_sw == 0) {
43        if (((SCTLR)Sctlr).dz) {
44#if FULL_SYSTEM
45            return new UndefinedInstruction;
46#else
47            return new UndefinedInstruction(false, mnemonic);
48#endif
49        }
50        Dest_sw = 0;
51    } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
52        Dest_sw = INT_MIN;
53    } else {
54        Dest_sw = Op1_sw / Op2_sw;
55    }
56    '''
57    sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
58                            { "code": sdivCode,
59                              "predicate_test": predicateTest,
60                              "op_class": "IntDivOp"}, [])
61    header_output = RegRegRegOpDeclare.subst(sdivIop)
62    decoder_output = RegRegRegOpConstructor.subst(sdivIop)
63    exec_output = PredOpExecute.subst(sdivIop)
64
65    udivCode = '''
66    if (Op2_uw == 0) {
67        if (((SCTLR)Sctlr).dz) {
68#if FULL_SYSTEM
69            return new UndefinedInstruction;
70#else
71            return new UndefinedInstruction(false, mnemonic);
72#endif
73        }
74        Dest_uw = 0;
75    } else {
76        Dest_uw = Op1_uw / Op2_uw;
77    }
78    '''
79    udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
80                            { "code": udivCode,
81                              "predicate_test": predicateTest,
82                              "op_class": "IntDivOp"}, [])
83    header_output += RegRegRegOpDeclare.subst(udivIop)
84    decoder_output += RegRegRegOpConstructor.subst(udivIop)
85    exec_output += PredOpExecute.subst(udivIop)
86}};
87