div.isa revision 7318:64352bcff9f3 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
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24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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37//
38// Authors: Gabe Black
39
40let {{
41    sdivCode = '''
42    if (Op2.sw == 0) {
43        Dest.sw = 0;
44    } else if (Op1.sw == INT_MIN && Op2.sw == -1) {
45        Dest.sw = INT_MIN;
46    } else {
47        Dest.sw = Op1.sw / Op2.sw;
48    }
49    '''
50    sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
51                            { "code": sdivCode,
52                              "predicate_test": predicateTest }, [])
53    header_output = RegRegRegOpDeclare.subst(sdivIop)
54    decoder_output = RegRegRegOpConstructor.subst(sdivIop)
55    exec_output = PredOpExecute.subst(sdivIop)
56}};
57