xref: /gem5/src/arch/arm/isa/insts/div.isa

// -*- mode:c++ -*-

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// Authors: Gabe Black

let {{
    sdivCode = '''
    if (Op2.sw == 0) {
        if (((SCTLR)Sctlr).dz) {
#if FULL_SYSTEM
            return new UndefinedInstruction;
#else
            return new UndefinedInstruction(false, mnemonic);
#endif
        }
        Dest.sw = 0;
    } else if (Op1.sw == INT_MIN && Op2.sw == -1) {
        Dest.sw = INT_MIN;
    } else {
        Dest.sw = Op1.sw / Op2.sw;
    }
    '''
    sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
                            { "code": sdivCode,
                              "predicate_test": predicateTest,
                              "op_class": "IntDivOp"}, [])
    header_output = RegRegRegOpDeclare.subst(sdivIop)
    decoder_output = RegRegRegOpConstructor.subst(sdivIop)
    exec_output = PredOpExecute.subst(sdivIop)

    udivCode = '''
    if (Op2.uw == 0) {
        if (((SCTLR)Sctlr).dz) {
#if FULL_SYSTEM
            return new UndefinedInstruction;
#else
            return new UndefinedInstruction(false, mnemonic);
#endif
        }
        Dest.uw = 0;
    } else {
        Dest.uw = Op1.uw / Op2.uw;
    }
    '''
    udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
                            { "code": udivCode,
                              "predicate_test": predicateTest,
                              "op_class": "IntDivOp"}, [])
    header_output += RegRegRegOpDeclare.subst(udivIop)
    decoder_output += RegRegRegOpConstructor.subst(udivIop)
    exec_output += PredOpExecute.subst(udivIop)
}};